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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MB96350_Softune_Dice_Kit/] [START.ASM] - Blame information for rev 604

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1 584 jeremybenn
;====================================================================
2
; $Id: START.ASM 2 2011-07-17 20:13:17Z filepang@gmail.com $
3
;====================================================================
4
; THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS.
5
;  FUJITSU MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY
6
;         FOR ANY ERRORS OR ELIGIBILITY FOR ANY PURPOSES.
7
;
8
;    Startup file for memory and basic controller initialisation
9
;
10
;    MB96300 Family C Compiler
11
;
12
;    (C) FUJITSU MICROELECTRONICS EUROPE 1998-2008
13
;====================================================================
14
 
15
          .PROGRAM  STARTUP
16
          .TITLE    "STARTUP FILE FOR MEMORY INITIALISATION"
17
 
18
;====================================================================
19
; 1  Contents
20
;====================================================================
21
; 1   Contents
22
; 2   Disclaimer
23
; 3   History
24
;
25
; 4   SETTINGS              (USER INTERFACE)
26
; 4.1   Controller Series, Device
27
; 4.2   C-language Memory model
28
; 4.3   Function-Call Interface
29
; 4.4   Constant Data Handling
30
; 4.5   Stack Type and Stack Size
31
; 4.6   General Register Bank
32
; 4.7   Low-Level Library Interface
33
 
34
; 4.8   Clock Selection
35
; 4.9   Clock Stabilization Time
36
; 4.10  External Bus Interface
37
; 4.11  ROM Mirror configuration
38
; 4.12  Flash Security
39
; 4.13  Flash Write Protection
40
; 4.14  Boot Vector
41
; 4.15  UART scanning
42
; 4.16  Enable RAMCODE Copying
43
; 4.17  Enable information stamp in ROM
44
; 4.18  Enable Background Debugging Mode
45
;
46
; 5   Section and Data Declaration
47
; 5.1   Several fixed addresses (fixed for MB963xx controllers)
48
; 5.2   Declaration of __near addressed data sections
49
; 5.3   Declaration of RAMCODE section and labels
50
; 5.4   Declaration of sections containing other sections description
51
; 5.5   Stack area and stack top definition/declaration
52
; 5.6   Direct page register dummy label definition
53
; 5.7   Set Flash Security
54
; 5.8   Set Flash write protection
55
; 5.9   Debug address specification
56
;
57
; 6   Start-Up Code
58
; 6.1   Import external symbols
59
; 6.2   Program start (the boot vector should point here)
60
; 6.3   "NOT RESET YET" WARNING
61
; 6.4   Initialisation of processor status
62
; 6.5   Set clock ratio (ignore subclock)
63
; 6.6   Set external bus configuration
64
; 6.7   Prepare stacks and set the active stack type
65
; 6.8   Copy initial values to data areas
66
; 6.9   Clear uninitialized data areas to zero
67
; 6.10  Set Data Bank Register (DTB) and Direct Page Register (DPR)
68
; 6.11  ICU register initialization workaround
69
; 6.12  Wait for PLL to stabilize
70
; 6.13  Initialise Low-Level Library Interface
71
; 6.14  Call C-language main function
72
; 6.15  Shut down library
73
; 6.16  Program end loop
74
;
75
;====================================================================
76
; 2  Disclaimer
77
;====================================================================
78
;                  FUJITSU MICROELECTRONICS EUROPE GMBH
79
;                  Pittlerstrasse 47, 63225 Langen, Germany
80
;                  Tel.:++49 6103 690-0, Fax -122
81
;
82
;    The following software is for demonstration purposes only.
83
;    It is not fully tested, nor validated in order to fulfil
84
;    its task under all circumstances. Therefore, this software
85
;    or any part of it must only be used in an evaluation
86
;    laboratory environment.
87
;    This software is subject to the rules of our standard
88
;    DISCLAIMER, that is delivered with our SW-tools on the
89
;    Fujitsu Microcontrollers DVD (V5.0 or higher "\START.HTM") or
90
;    on our Internet Pages:
91
;    http://www.fme.gsdc.de/gsdc.htm
92
;    http://emea.fujitsu.com/microelectronics
93
;
94
;====================================================================
95
; 3  History
96
;====================================================================
97
; $Id: START.ASM 2 2011-07-17 20:13:17Z filepang@gmail.com $
98
 
99
#define VERSION  "1.31"
100
/*
101
$Log: START.ASM,v $
102
Revision 1.31  2008/02/27 10:23:34  mcuae
103
- CPU_48MHZ_CLKP1_32MHZ_CLKP2_16MHZ clock setting added
104
 
105
Revision 1.30  2008/02/26 15:28:21  mcuae
106
- clock settings corrected
107
- Main/Satellite Flash term outdated, now: Flash A, Flash B
108
 
109
Revision 1.29  2008/02/11 15:26:33  mwilla
110
- device configuration for ext. bus i/f settings updated
111
 
112
Revision 1.28  2008/01/25 08:03:48  mwilla
113
- clock settings corrected and optimized
114
 
115
Revision 1.27  2008/01/04 12:26:08  mwilla
116
- device list expanded
117
- clock settings optimized
118
 
119
Revision 1.26  2007/10/17 11:53:34  mwilla
120
- device list expanded
121
- ICU initialization workaround added
122
- sections settings grouped
123
 
124
Revision 1.25  2007/09/28 07:33:18  mwilla
125
- Bug in BDM baudrate calculation corrected
126
 
127
Revision 1.24  2007/09/26 14:03:08  mwilla
128
- Device list for MB96340 series updated and expanded
129
 
130
Revision 1.23  2007/08/06 14:48:16  mwilla
131
- BDM section always reserved, filled with 0xFF, if not configured
132
 
133
Revision 1.22  2007/08/02 08:34:03  mwilla
134
- communication mode bits of BDM configuration grouped
135
 
136
Revision 1.21  2007/07/13 08:23:05  mwilla
137
- device selection for BDM baud rate improved
138
 
139
Revision 1.20  2007/06/12 10:43:57  mwilla
140
- BDM-Baud-Rate calculation includes crystal frequency
141
 
142
Revision 1.19  2007/06/06 07:46:55  mwilla
143
- add Background Debugging Configuration
144
- Stack initialization moved before variable initialization
145
- values of cystal frequency and device macros changed
146
 
147
Revision 1.18  2007/04/16 07:56:02  phuene
148
- update clock settings when crystal is 8 MHz so that the CLKVCO is low
149
 
150
Revision 1.17  2007/04/10 11:30:43  phuene
151
- add MB96320 Series
152
- Clock settings optimized for CPU_8MHZ_CLKP2_8MHZ, CPU_12MHZ_CLKP2_12MHZ, CPU_16MHZ_CLKP2_16MHZ, CPU_24MHZ_CLKP2_24MHZ, CPU_32MHZ_CLKP2_32MHZ
153
- make the selection for the individual devices also consider the selected Series
154
- support 8 MHz crystal
155
- add clock setting CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ
156
- prohibit CPU_32MHZ_CLKP2_16MHZ, CPU_CLKP1_16MHZ_CLKP2_16MHZ for MB96F348H and MB96F348T according to functional limitation 16FXFL0014
157
 
158
Revision 1.16  2007/02/07 12:38:10  phuene
159
- support disabling the UART scanning in Internal Vector Mode
160
- distinguish between Reset Vector and Boot Vector: the Boot Vector points to the start of the user application
161
 
162
Revision 1.15  2007/02/07 09:00:19  phuene
163
- add .SKIP instructions to occupy the whole ROM configuration block area
164
 
165
Revision 1.14  2007/01/29 13:15:06  phuene
166
- fix CPU_4MHZ_MAIN_CLKP2_4MHZ clock setting
167
 
168
Revision 1.13  2007/01/03 10:40:14  phuene
169
- change clock setting CPU_24MHZ_CLKP2_16MHZ to CPU_24MHZ_CLKP2_12MHZ; this allows for better performance of MB96F348H/T
170
- use additional preprocessor statements to avoid checking for PLL ready twice in some cases
171
 
172
Revision 1.12  2007/01/02 10:16:20  phuene
173
- correct CLKP2 (CAN) clock for CPU_32MHZ and MB96F348H/T
174
- correct CLKP2 (CAN) clock for CPU_24MHZ for all other devices than MB96F348H/T
175
 
176
Revision 1.11  2006/12/28 10:49:52  phuene
177
- corrected PLL setting for CPU_16MHZ for MB96348H, MB96348T
178
 
179
Revision 1.10  2006/12/28 08:41:57  phuene
180
- correct revision number at new location
181
 
182
Revision 1.1  2006/12/28 07:20:01  phuene
183
- new location in CVS
184
 
185
Revision 1.9  2006/12/27 13:00:45  phuene
186
- add support for ROM Mirror when using the Simulator
187
- add support for 16FXFL0022, 16FXFL0023
188
 
189
Revision 1.8  2006/12/11 16:43:37  phuene
190
- fix typo
191
 
192
Revision 1.7  2006/12/11 16:35:08  phuene
193
- add setting for Clock Stabilization Times
194
- modify clock settings:
195
  - CLKP2 < 28 MHz
196
  - remove clock settings using more wait cycles than absolutely required
197
 
198
Revision 1.6  2006/11/03 13:38:45  phuene
199
- modify clock settings to also set the Flash Memory Timing
200
- add support for both parameter passing models
201
 
202
Revision 1.5  2006/08/07 14:01:44  phuene
203
- change default clock setting to PLLx4 for CLKS1, CLKS2
204
- correct clock setting
205
- disable Flash Security by default for Main Flash, Satellite Flash
206
- disable availability of Satellite Flash by default
207
 
208
Revision 0.1  2006/01/25 15:37:46  phu
209
- initial version based on start.asm for MB90340 Series, version 3.8
210
Revision 0.2  2006/07/14 15:37:46  phu
211
- include PIER settings for External Bus operation
212
Revision 0.3  2006/07/14 15:37:46  phu
213
- add MB96350 Series
214
- correct PIER settings for HRQ and RDY signals
215
Revision 0.4  2006/08/07 15:35:35  phu
216
- change default clock setting to PLLx4 for CLKS1, CLKS2
217
- correct clock setting
218
- disable Flash Security by default for Main Flash, Satellite Flash
219
- disable availability of Satellite Flash by default
220
*/
221
;====================================================================
222
 
223
;====================================================================
224
; 4  Settings
225
;====================================================================
226
;
227
; CHECK ALL OPTIONS WHETHER THEY FIT TO THE APPLICATION
228
;
229
; Configure this startup file in the "Settings" section. Search for
230
; comments with leading "; <<<". This points to the items to be set.
231
;====================================================================
232
#set      OFF       0
233
#set      ON        1
234
 
235
;====================================================================
236
; 4.1  Controller Series, Device
237
;====================================================================
238
 
239
#set      MB96320   0
240
#set      MB96330   1
241
#set      MB96340   2
242
#set      MB96350   3
243
#set      MB96360   4
244
#set      MB96370   5
245
#set      MB96380   6
246
#set      MB96390   7
247
 
248
#set      SERIES    MB96350        ; <<< select Series
249
 
250
 
251
; Please specify the device according to the following selection;
252
; x = {W, S}.
253
; Note: Do not change order because of device number dependency in
254
; 6.5 Clock settings, 5.9 Debug address specification,
255
; and 6.11 ICU register initialization workaround!
256
 
257
; MB96320 series
258
#set      MB96326RxA   1
259
#set      MB96326YxA   2
260
 
261
; MB96330 series
262
#set      MB96338RxA   1
263
#set      MB96338UxA   2
264
 
265
; MB96340 series
266
#set      MB96348HxA   1
267
#set      MB96348TxA   2
268
#set      MB96346RxA   3
269
#set      MB96346YxA   4
270
#set      MB96346AxA   5
271
#set      MB96347RxA   6
272
#set      MB96347YxA   7
273
#set      MB96347AxA   8
274
#set      MB96348RxA   9
275
#set      MB96348YxA  10
276
#set      MB96348AxA  11
277
#set      MB96346RxB  12
278
#set      MB96346AxB  13
279
#set      MB96346YxB  14
280
#set      MB96347RxB  15
281
#set      MB96347AxB  16
282
#set      MB96347YxB  17
283
#set      MB96348CxA  18
284
#set      MB96348HxB  19
285
#set      MB96348TxB  20
286
#set      MB96348RxB  21
287
#set      MB96348AxB  22
288
#set      MB96348YxB  23
289
#set      MB96348CxC  24
290
#set      MB96348HxC  25
291
#set      MB96348TxC  26
292
 
293
; MB96350 series
294
#set      MB96356RxA   1
295
#set      MB96356YxA   2
296
 
297
; MB96360 series
298
#set      MB96365RxA   1
299
#set      MB96365YxA   2
300
 
301
; MB96370 series
302
#set      MB96379RxA   1
303
#set      MB96379YxA   2
304
 
305
; MB96380 series
306
#set      MB96384RxA   1
307
#set      MB96384YxA   2
308
#set      MB96385RxA   3
309
#set      MB96385YxA   4
310
#set      MB96386RxA   5
311
#set      MB96386YxA   6
312
#set      MB96387RxA   7
313
#set      MB96387YxA   8
314
#set      MB96386RxB   9
315
#set      MB96386YxB  10
316
#set      MB96387RxB  11
317
#set      MB96387YxB  12
318
 
319
; MB96390 series
320
#set      MB96395RxA   1
321
 
322
 
323
#set      DEVICE    MB96356RxA      ; <<< select device
324
 
325
;====================================================================
326
; 4.2  C-language Memory model
327
;====================================================================
328
 
329
                                   ;      data      code
330
#set      SMALL     0              ;     16 Bit    16 Bit
331
#set      MEDIUM    1              ;     16 Bit    24 Bit
332
#set      COMPACT   2              ;     24 Bit    16 Bit
333
#set      LARGE     3              ;     24 Bit    24 Bit
334
#set      AUTOMODEL 4              ; works always, might occupy two
335
                                   ; additional bytes
336
 
337
 
338
#set      MEMMODEL  AUTOMODEL      ; <<< C-memory model
339
 
340
; The selected memory model should be set in order to fit to the
341
; model selected for the compiler.
342
; Note, in this startup version AUTOMODEL will work for all
343
; C-models. However, if the compiler is configured for SMALL or
344
; COMPACT, two additional bytes on stack are occupied. If this is not
345
; acceptable, the above setting should be set to the correct model.
346
 
347
;====================================================================
348
; 4.3  Function-Call Interface
349
;====================================================================
350
 
351
          #if __REG_PASS__
352
            .REG_PASS
353
          #endif
354
 
355
; Above statement informs Assembler on compatibility of start-up code
356
; to  Function Call Interface  as selected for the application. There
357
; is nothing to configure.
358
; The Function-Call Interface specifies the method of passing parame-
359
; ter from function caller to callee.  The standard method of FCC907S
360
; compiler  uses  "stack argument passing".  Alternatively,  language
361
; tools can be configured for "register argument passing".
362
; For details see the compiler manual.
363
; This start-up file is compatible to both interfaces.
364
 
365
;====================================================================
366
; 4.4  Constant Data Handling
367
;====================================================================
368
 
369
#set      ROMCONST    0            ; works only with compiler ROMCONST
370
#set      RAMCONST    1            ; works with BOTH compiler settings
371
#set      AUTOCONST   RAMCONST     ; works with BOTH compiler settings
372
 
373
#set      CONSTDATA   AUTOCONST    ; <<< set RAM/ROM/AUTOCONST
374
 
375
; - AUTOCONST (default) is the same as RAMCONST
376
; - RAMCONST/AUTOCONST should always work, even if compiler is set to
377
;   ROMCONST. If compiler is set to ROMCONST and this startup file is
378
;   set to RAMCONST or AUTOCONST, this startup file will generate an
379
;   empty section CINIT in RAM. However, the code, which copies from
380
;   CONST to CINIT will not have any effect, because size of section is 0.
381
; - It is highly recommended to set the compiler to ROMCONST for
382
;   single-chip mode or internal ROM+ext bus. The start-up file
383
;   should be set to AUTOCONST.
384
; - ROMCONST setting on systems with full external bus requires exter-
385
;   nal address mapping.
386
;   Single-chip can be emulated by the emulator debugger.
387
;   ROM mirror can also be used with simulator.
388
;
389
; see also ROM MIRROR options
390
 
391
;====================================================================
392
; 4.5  Stack Type and Stack Size
393
;====================================================================
394
 
395
#set      USRSTACK       0      ; user stack: for main program
396
#set      SYSSTACK       1      ; system stack: for main program and interrupts
397
 
398
#set      STACKUSE  SYSSTACK    ; <<< set active stack
399
 
400
#set      STACK_RESERVE  ON     ; <<< reserve stack area in this module
401
#set      STACK_SYS_SIZE 200   ; <<< byte size of System stack
402
#set      STACK_USR_SIZE 2      ; <<< byte size of User stack
403
 
404
#set      STACK_FILL     ON     ; <<< fills the stack area with pattern
405
#set      STACK_PATTERN  0x55AA ; <<< the pattern to write to stack
406
 
407
; - If the active stack is set to SYSSTACK, it is used for main program
408
;   and interrupts. In this case, the user stack can be set to a dummy
409
;   size.
410
;   If the active stack is set to user stack, it is used for the main
411
;   program but the system stack is automatically activated, if an inter-
412
;   rupt is serviced. Both stack areas must have a reasonable size.
413
; - If STACK_RESERVE is ON, the sections USTACK and SSTACK are reserved
414
;   in this module. Otherwise, they have to be reserved in other modules.
415
;   If STACK_RESERVE is OFF, the size definitions STACK_SYS_SIZE and
416
;   STACK_USR_SIZE have no meaning.
417
; - Even if they are reserved in other modules, they are still initialised
418
;   in this start-up file.
419
; - Filling the stack with a pattern allows to dynamically check the stack
420
;   area, which had already been used.
421
;
422
; - If only system stack is used and SSB is linked to a different bank
423
;   than USB, make sure that all C-modules (which generate far pointers
424
;   to stack data) have "#pragma SSB". Applies only to exclusive confi-
425
;   gurations.
426
; - Note, several library functions require quite a big stack (due to
427
;   ANSI). Check the stack information files (*.stk) in the LIB\907
428
;   directory.
429
 
430
;====================================================================
431
; 4.6  General Register Bank
432
;====================================================================
433
 
434
#set      REGBANK   0           ; <<< set default register bank
435
 
436
; set the General Register Bank that is to be used after startup.
437
; Usually, this is bank 0, which applies to address H'180..H'18F. Set
438
; in the range from 0 to 31.
439
; Note: All used register banks have to be reserved (linker options).
440
 
441
#if REGBANK > 31 || REGBANK < 0
442
#  error REGBANK setting out of range
443
#endif
444
 
445
;====================================================================
446
; 4.7  Low-Level Library Interface
447
;====================================================================
448
 
449
#set      CLIBINIT       OFF    ; <<< select extended library usage
450
 
451
; This option has only to be set, if stream-IO/standard-IO function of
452
; the C-library have to be used (printf(), fopen()...). This also
453
; requires low-level functions to be defined by the application
454
; software.
455
; For other library functions (like e.g. sprintf()) all this is not
456
; necessary. However, several functions consume a large amount of stack.
457
 
458
;====================================================================
459
; 4.8  Clock Selection
460
;====================================================================
461
 
462
; The clock selection requires that a 4 MHz external clock is provided
463
; as the Main Clock. If a different frequency is used, the Flash Memory
464
; Timing settings must be checked!
465
 
466
#set      CLOCKWAIT      ON     ; <<< wait for stabilized clock, if
467
                                ;     Main Clock or PLL is used
468
 
469
; The clock is set quite early. However, if CLOCKWAIT is ON, polling
470
; for machine clock to be switched to Main Clock or PLL is done at
471
; the end of this file. Therefore, the stabilization time is not
472
; wasted. Main() will finally start at correct speed. Resources can
473
; be used immediately.
474
; Note: Some frequency settings (below) necessarily need a stabilized
475
; PLL for final settings. In these cases, the CLOCKWAIT setting above
476
; does not have any effect.
477
;
478
; This startup file version does not support subclock.
479
 
480
#set      FREQ_4MHZ       D'4000000L
481
#set      FREQ_8MHZ       D'8000000L
482
 
483
#set      CRYSTAL         FREQ_4MHZ  ; <<< select external crystal frequency
484
 
485
#set      CPU_4MHZ_MAIN_CLKP2_4MHZ            0x0004
486
#set      CPU_4MHZ_PLL_CLKP2_4MHZ             0x0104
487
#set      CPU_8MHZ_CLKP2_8MHZ                 0x0108
488
#set      CPU_12MHZ_CLKP2_12MHZ               0x010C
489
#set      CPU_16MHZ_CLKP2_16MHZ               0x0110
490
#set      CPU_24MHZ_CLKP2_12MHZ               0x0118
491
#set      CPU_32MHZ_CLKP2_16MHZ               0x0120
492
#set      CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ   0x0220
493
#set      CPU_48MHZ_CLKP2_16MHZ               0x0130
494
#set      CPU_48MHZ_CLKP1_32MHZ_CLKP2_16MHZ   0x0230
495
#set      CPU_56MHZ_CLKP2_14MHZ               0x0138
496
 
497
#set      CLOCK_SPEED     CPU_56MHZ_CLKP2_14MHZ               ; <<< set clock speeds
498
 
499
; The peripheral clock CLKP1 is set to the same frequency than the CPU.
500
; The peripheral clock CLKP2 has its setting. This is because it
501
; feeds only the CAN controllers and Sound Generators. These do not
502
; need high frequency clocks.
503
 
504
;====================================================================
505
; 4.9  Clock Stabilization Time
506
;====================================================================
507
 
508
#set      MC_2_10_CYCLES   0
509
#set      MC_2_12_CYCLES   1
510
#set      MC_2_13_CYCLES   2
511
#set      MC_2_14_CYCLES   3
512
#set      MC_2_15_CYCLES   4
513
#set      MC_2_16_CYCLES   5
514
#set      MC_2_17_CYCLES   6
515
#set      MC_2_18_CYCLES   7
516
 
517
#set      MC_STAB_TIME     MC_2_15_CYCLES ; <<< select Main Clock Stabilization Time
518
 
519
;====================================================================
520
; 4.10 External Bus Interface
521
;====================================================================
522
 
523
#set      SINGLE_CHIP     0        ; all internal
524
#set      INTROM_EXTBUS   1        ; mask ROM or FLASH memory used
525
#set      EXTROM_EXTBUS   2        ; full external bus (INROM not used)
526
 
527
#set      BUSMODE SINGLE_CHIP      ; <<< set bus mode (see mode pins)
528
 
529
#set      MULTIPLEXED     0        ;
530
#set      NON_MULTIPLEXED 1        ; only if supported by the device
531
 
532
#set      ADDRESSMODE MULTIPLEXED  ; <<< set address-mode
533
 
534
; Some devices support multiplexed and/or non-multiplexed Bus mode
535
; please refer to the related datasheet/hardwaremanual
536
 
537
 
538
; If BUSMODE is "SINGLE_CHIP", ignore remaining bus settings.
539
 
540
; Select the used Chip Select areas
541
#set      CHIP_SELECT0       OFF   ; <<< enable chip select area
542
#set      CHIP_SELECT1       OFF   ; <<< enable chip select area
543
#set      CHIP_SELECT2       OFF   ; <<< enable chip select area
544
#set      CHIP_SELECT3       OFF   ; <<< enable chip select area
545
#set      CHIP_SELECT4       OFF   ; <<< enable chip select area
546
#set      CHIP_SELECT5       OFF   ; <<< enable chip select area
547
 
548
#set      HOLD_REQ           OFF   ; <<< select Hold function
549
#set      EXT_READY          OFF   ; <<< select external Ready function
550
#set      EXT_CLOCK_ENABLE   OFF   ; <<< select external bus clock output
551
#set      EXT_CLOCK_INVERT   OFF   ; <<< select clock inversion
552
#set      EXT_CLOCK_SUSPEND  OFF   ; <<< select if external clock is suspended when no transfer in progress
553
 
554
; The external bus clock is derived from core clock CLKB. Select the divider for the external bus clock.
555
 
556
#set      EXT_CLOCK_DIV1     0
557
#set      EXT_CLOCK_DIV2     1
558
#set      EXT_CLOCK_DIV4     2
559
#set      EXT_CLOCK_DIV8     3
560
#set      EXT_CLOCK_DIV16    4
561
#set      EXT_CLOCK_DIV32    5
562
#set      EXT_CLOCK_DIV64    6
563
#set      EXT_CLOCK_DIV128   7
564
 
565
#set      EXT_CLOCK_DIVISION  EXT_CLOCK_DIV1 ; <<< select clock divider
566
 
567
#set      ADDR_PINS_23_16    B'00000000     ; <<< select used address lines
568
                                            ;     A23..A16 to be output.
569
#set      ADDR_PINS_15_8     B'00000000     ; <<< select used address lines
570
                                            ;     A15..A8 to be output.
571
#set      ADDR_PINS_7_0      B'00000000     ; <<< select used address lines
572
                                            ;     A7..A0 to be output.
573
 
574
#set      LOW_BYTE_SIGNAL    OFF   ; <<< select low byte signal LBX
575
#set      HIGH_BYTE_SIGNAL   OFF   ; <<< select high byte signal UBX
576
#set      LOW_WRITE_STROBE   OFF   ; <<< select write strobe signal WRLX/WRX
577
#set      HIGH_WRITE_STROBE  OFF   ; <<< select write strobe signal WRHX
578
#set      READ_STROBE        OFF   ; <<< select read strobe signal RDX
579
#set      ADDRESS_STROBE     OFF   ; <<< select address strobe signal ALE/ASX
580
#set      ADDRESS_STROBE_LVL OFF   ; <<< select address strobe function: OFF - active low; ON - active high
581
 
582
 
583
#set      CS0_CONFIG  B'0000000000000000    ; <<< select Chip Select Area 0 configuration
584
;                       |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32)
585
;                       ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle)
586
;                       |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1)
587
;                       ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe)
588
;                       |||||||||+-------- Endianess (0: little endian, 1: big endian)
589
;                       ||||||||+--------- Bus width (0: 16bit, 1: 8bit)
590
;                       |||||+++---------- ignored
591
;                       ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled)
592
;                       |||+-------------- Chip Select level (0: low active, 1: high active)
593
;                       ||+--------------- Access type limitation (0: code and data, 1: data only)
594
;                       ++---------------- ignored
595
 
596
#set      CS1_CONFIG  B'0000000000000000    ; <<< select Chip Select Area 1 configuration
597
;                       |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32)
598
;                       ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle)
599
;                       |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1)
600
;                       ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe)
601
;                       |||||||||+-------- Endianess (0: little endian, 1: big endian)
602
;                       ||||||||+--------- Bus width (0: 16bit, 1: 8bit)
603
;                       |||||+++---------- ignored
604
;                       ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled)
605
;                       |||+-------------- Chip Select level (0: low active, 1: high active)
606
;                       ||+--------------- Access type limitation (0: code and data, 1: data only)
607
;                       ++---------------- ignored
608
 
609
#set      CS2_CONFIG  B'0000011000000000    ; <<< select Chip Select Area 2 configuration
610
;                       |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32)
611
;                       ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle)
612
;                       |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1)
613
;                       ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe)
614
;                       |||||||||+-------- Endianess (0: little endian, 1: big endian)
615
;                       ||||||||+--------- Bus width (0: 16bit, 1: 8bit)
616
;                       |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB)
617
;                       ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled)
618
;                       |||+-------------- Chip Select level (0: low active, 1: high active)
619
;                       ||+--------------- Access type limitation (0: code and data, 1: data only)
620
;                       ++---------------- ignored
621
 
622
#set      CS3_CONFIG  B'0000011000000000    ; <<< select Chip Select Area 3 configuration
623
;                       |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32)
624
;                       ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle)
625
;                       |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1)
626
;                       ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe)
627
;                       |||||||||+-------- Endianess (0: little endian, 1: big endian)
628
;                       ||||||||+--------- Bus width (0: 16bit, 1: 8bit)
629
;                       |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB)
630
;                       ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled)
631
;                       |||+-------------- Chip Select level (0: low active, 1: high active)
632
;                       ||+--------------- Access type limitation (0: code and data, 1: data only)
633
;                       ++---------------- ignored
634
 
635
#set      CS4_CONFIG  B'0000011000000000    ; <<< select Chip Select Area 4 configuration
636
;                       |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32)
637
;                       ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle)
638
;                       |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1)
639
;                       ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe)
640
;                       |||||||||+-------- Endianess (0: little endian, 1: big endian)
641
;                       ||||||||+--------- Bus width (0: 16bit, 1: 8bit)
642
;                       |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB)
643
;                       ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled)
644
;                       |||+-------------- Chip Select level (0: low active, 1: high active)
645
;                       ||+--------------- Access type limitation (0: code and data, 1: data only)
646
;                       ++---------------- ignored
647
 
648
#set      CS5_CONFIG  B'0000011000000000    ; <<< select Chip Select Area 5 configuration
649
;                       |||||||||||||+++-- Automatic wait cycles (0: 0, 1: 1, 2: 2, 3: 3, 4: 4, 5: 8, 6: 16, 7: 32)
650
;                       ||||||||||||+----- Address Cycle Extension (0: not extended, 1: extension by 1 cycle)
651
;                       |||||||||||+------ Strobe timing (0: scheme 0, 1: scheme 1)
652
;                       ||||||||||+------- Write strobe function (0: WRLX strobe, 1: WRX strobe)
653
;                       |||||||||+-------- Endianess (0: little endian, 1: big endian)
654
;                       ||||||||+--------- Bus width (0: 16bit, 1: 8bit)
655
;                       |||||+++---------- External area size (0: 64kB, 1: 128kB, 2: 256kB, 3: 512kB, 4: 1MB, 5: 2MB, 6: 4MB, 7: 8MB)
656
;                       ||||+------------- Chip Select output enable (0: CS disabled, 1: CS enabled)
657
;                       |||+-------------- Chip Select level (0: low active, 1: high active)
658
;                       ||+--------------- Access type limitation (0: code and data, 1: data only)
659
;                       ++---------------- ignored
660
 
661
 
662
#set      CS2_START  0x00       ; <<< select start bank of chip select area; valid values: 0x00..0xFF
663
#set      CS3_START  0x40       ; <<< select start bank of chip select area; valid values: 0x00..0xFF
664
#set      CS4_START  0x80       ; <<< select start bank of chip select area; valid values: 0x00..0xFF
665
#set      CS5_START  0xC0       ; <<< select start bank of chip select area; valid values: 0x00..0xFF
666
 
667
 
668
;====================================================================
669
; 4.11 ROM Mirror configuration
670
;====================================================================
671
 
672
#set      MIRROR_8KB    0
673
#set      MIRROR_16KB   1
674
#set      MIRROR_24KB   2
675
#set      MIRROR_32KB   3
676
 
677
#set      ROMMIRROR     ON          ; <<< ROM mirror function ON/OFF
678
#set      MIRROR_BANK   0xF         ; <<< ROM Mirror bank, allowed entries: 0x0..0xF for the banks 0xF0..0xFF
679
#set      MIRROR_SIZE   MIRROR_32KB ; <<< ROM Mirror size
680
 
681
; One can select which ROM area to mirror into the upper half of bank 00.
682
; If ROMMIRROR = OFF is selected, the address range 0x008000..0x00FFFF
683
; shows the contents of the respective area of bank 1: 0x018000..0x01FFFF.
684
; If ROMMIRROR = ON is selected, the memory bank to mirror can be selected.
685
; Available banks are 0xF0 to 0xFF. Furthermore, the ROM Mirror area size can
686
; be selected. 4 sizes are available: 8 kB, 16 kB, 24 kB, or 32 kB. The ROM Mirror
687
; from the highest address of the selected bank downwards, e.g. if bank 0xFF and
688
; mirror size 24 kB is selected, the memory range 0xFFA000..0xFFFFFF is mirrored
689
; to address range 0x00A000..0x00FFFF. The memory area not selected for
690
; ROM Mirror is still mirrored from bank 0x01.
691
; This is necessary to get the compiler ROMCONST option working. This is intended
692
; to increase performance, if a lot of dynamic data have to be accessed.
693
; In SMALL and MEDIUM model these data can be accessed within bank 0,
694
; which allows to use near addressing. Please make sure to have the linker
695
; setting adjusted accordingly!
696
 
697
 
698
;====================================================================
699
; 4.12 Flash Security
700
;====================================================================
701
 
702
#set      FLASH_A_SECURITY_ENABLE    OFF ; <<< enable Flash Security for Flash A (old "Main Flash")
703
#set      FLASH_B_AVAILABLE          OFF ; <<< select if Flash B is available
704
#set      FLASH_B_SECURITY_ENABLE    OFF ; <<< enable Flash Security for Flash B (old "Satellite Flash")
705
 
706
; set the Flash Security unlock key (16 bytes)
707
; all 0: unlock not possible
708
#set      FLASH_A_UNLOCK_0           0x00
709
#set      FLASH_A_UNLOCK_1           0x00
710
#set      FLASH_A_UNLOCK_2           0x00
711
#set      FLASH_A_UNLOCK_3           0x00
712
#set      FLASH_A_UNLOCK_4           0x00
713
#set      FLASH_A_UNLOCK_5           0x00
714
#set      FLASH_A_UNLOCK_6           0x00
715
#set      FLASH_A_UNLOCK_7           0x00
716
#set      FLASH_A_UNLOCK_8           0x00
717
#set      FLASH_A_UNLOCK_9           0x00
718
#set      FLASH_A_UNLOCK_10          0x00
719
#set      FLASH_A_UNLOCK_11          0x00
720
#set      FLASH_A_UNLOCK_12          0x00
721
#set      FLASH_A_UNLOCK_13          0x00
722
#set      FLASH_A_UNLOCK_14          0x00
723
#set      FLASH_A_UNLOCK_15          0x00
724
 
725
#set      FLASH_B_UNLOCK_0           0x00
726
#set      FLASH_B_UNLOCK_1           0x00
727
#set      FLASH_B_UNLOCK_2           0x00
728
#set      FLASH_B_UNLOCK_3           0x00
729
#set      FLASH_B_UNLOCK_4           0x00
730
#set      FLASH_B_UNLOCK_5           0x00
731
#set      FLASH_B_UNLOCK_6           0x00
732
#set      FLASH_B_UNLOCK_7           0x00
733
#set      FLASH_B_UNLOCK_8           0x00
734
#set      FLASH_B_UNLOCK_9           0x00
735
#set      FLASH_B_UNLOCK_10          0x00
736
#set      FLASH_B_UNLOCK_11          0x00
737
#set      FLASH_B_UNLOCK_12          0x00
738
#set      FLASH_B_UNLOCK_13          0x00
739
#set      FLASH_B_UNLOCK_14          0x00
740
#set      FLASH_B_UNLOCK_15          0x00
741
 
742
 
743
;====================================================================
744
; 4.13  Flash Write Protection
745
;====================================================================
746
 
747
#set      FLASH_A_WRITE_PROTECT           OFF       ; <<< select Flash A write protection
748
#set      PROTECT_SECTOR_SA0              OFF       ; <<< select individual sector to protect
749
#set      PROTECT_SECTOR_SA1              OFF       ; <<< select individual sector to protect
750
#set      PROTECT_SECTOR_SA2              OFF       ; <<< select individual sector to protect
751
#set      PROTECT_SECTOR_SA3              OFF       ; <<< select individual sector to protect
752
#set      PROTECT_SECTOR_SA32             OFF       ; <<< select individual sector to protect
753
#set      PROTECT_SECTOR_SA33             OFF       ; <<< select individual sector to protect
754
#set      PROTECT_SECTOR_SA34             OFF       ; <<< select individual sector to protect
755
#set      PROTECT_SECTOR_SA35             OFF       ; <<< select individual sector to protect
756
#set      PROTECT_SECTOR_SA36             OFF       ; <<< select individual sector to protect
757
#set      PROTECT_SECTOR_SA37             OFF       ; <<< select individual sector to protect
758
#set      PROTECT_SECTOR_SA38             OFF       ; <<< select individual sector to protect
759
#set      PROTECT_SECTOR_SA39             OFF       ; <<< select individual sector to protect
760
 
761
#set      FLASH_B_WRITE_PROTECT           OFF       ; <<< select Flash write protection
762
#set      PROTECT_SECTOR_SB0              OFF       ; <<< select individual sector to protect
763
#set      PROTECT_SECTOR_SB1              OFF       ; <<< select individual sector to protect
764
#set      PROTECT_SECTOR_SB2              OFF       ; <<< select individual sector to protect
765
#set      PROTECT_SECTOR_SB3              OFF       ; <<< select individual sector to protect
766
 
767
 
768
;====================================================================
769
; 4.14  Boot Vector
770
;====================================================================
771
 
772
#set      BOOT_VECTOR_TABLE  1              ; enable boot vector
773
#set      BOOT_VECTOR_FIXED  2              ; enable boot vector
774
 
775
#set      BOOT_VECTOR   BOOT_VECTOR_TABLE   ; <<< select type of boot vector
776
 
777
; If boot vector generation is enabled (BOOT_VECTOR_TABLE, BOOT_VECTOR_FIXED),
778
; appropriate code is generated. If it is disabled (OFF), start-up file does
779
; not care about.
780
;
781
;   BOOT_VECTOR_TABLE: - Create table entry at address oxFFFFDC.
782
;                      - Any start address can be set and start-up file will
783
;                        set address of this start code.
784
;   BOOT_VECTOR_FIXED: - Instead of table entry, a special marker is set in
785
;                        ROM Configuration Block, which enables the fixed
786
;                        start address 0xDF0080. This is prefered setting
787
;                        for user boot loaders.
788
;                 OFF: - Do not set table entry and marker. This might be used
789
;                        for application to be loaded by boot loader.
790
;
791
; Note
792
; BOOT_VECTOR_TABLE setting can also be used, if all other interrupt vectors
793
; are specified via "pragma intvect". Only if interrupts 0..7 are specified
794
; via "pragma intvect", these will conflict with the vector in this module.
795
; The reason is the INTVECT section, which includes the whole area from the
796
; lowest to the highest specified vector.
797
 
798
#if BOOT_VECTOR == BOOT_VECTOR_TABLE
799
          .SECTION        RESVECT, CONST, LOCATE=H'FFFFDC
800
          .DATA.E _start
801
          .SECTION        BOOT_SELECT, CONST, LOCATE=H'DF0030
802
          .DATA.L 0xFFFFFFFF
803
 
804
#else
805
#  if BOOT_VECTOR == BOOT_VECTOR_FIXED
806
          .SECTION        BOOT_SELECT, CONST, LOCATE=H'DF0030
807
          .DATA.L 0x292D3A7B        ; "Magic Word"
808
#  else
809
          .SECTION        BOOT_SELECT, CONST, LOCATE=H'DF0030
810
          .SKIP   4
811
#  endif
812
#endif
813
 
814
;====================================================================
815
; 4.15  UART scanning
816
;====================================================================
817
 
818
#set      UART_SCANNING   OFF        ; <<< enable UART scanning in
819
                                     ;     Internal Vector Mode
820
;
821
; By default, the MCU scans in Internal Vector Mode for a UART
822
; communication after reset. This enables to establish a serial
823
; communication without switching to Serial Communication Mode.
824
; For the final application, set this switch to OFF to achieve the
825
; fastest start-up time.
826
 
827
#if UART_SCANNING == ON
828
#  if ((SERIES == MB96340) && (DEVICE < 3))
829
#    error Device does not support UART scanning on/off
830
#  else
831
          .SECTION        UART_SCAN_SELECT, CONST, LOCATE=H'DF0034
832
          .DATA.L 0xFFFFFFFF
833
#  endif ; (SERIES == MB96340 && DEVICE < 3)
834
#else
835
          .SECTION        UART_SCAN_SELECT, CONST, LOCATE=H'DF0034
836
          .DATA.L 0x292D3A7B        ; Decativation "Magic Word"
837
#endif
838
          .SKIP   0x08
839
 
840
 
841
;====================================================================
842
; 4.16  Enable RAMCODE Copying
843
;====================================================================
844
 
845
#set      COPY_RAMCODE      OFF     ; <<< enable RAMCODE section to
846
                                    ; be copied from ROM to RAM
847
 
848
; To get this option properly working the code to be executed has to
849
; be linked to section RAMCODE (e.g. by #pragma section). The section
850
; RAMCODE has be located in RAM and the section @RAMCODE has to be
851
; located at a fixed address in ROM by linker settings.
852
 
853
;====================================================================
854
; 4.17  Enable information stamp in ROM
855
;====================================================================
856
 
857
#set      VERSION_STAMP     OFF     ; <<< enable version number in
858
                                    ; separated section
859
 
860
 
861
#if VERSION_STAMP == ON
862
          .SECTION  VERSIONS, CONST ; change name, if necessary
863
          .SDATA    "Start ", VERSION, "\n\0"
864
#endif
865
 
866
;====================================================================
867
; 4.18  Enable Background Debugging Mode
868
;====================================================================
869
 
870
#set      BACKGROUND_DEBUGGING  ON  ; <<< enable Background Debugging
871
                                    ; mode
872
 
873
#set      BDM_CONFIGURATION  B'0000000000010011  ; <<< set BDM configuration
874
;                                    ||||||||++--- BdmUART
875
;                                    ||||||||      (0: A, 1: B, 2: C, 3: D)
876
;                                    ||||||++----- BdmSynchMode
877
;                                    ||||||        (0: Async., 1: Sync.
878
;                                    ||||||        2: BdmKLine, 3: res.)
879
;                                    |||||+------- BdmAutoStart
880
;                                    ||||+-------- BdmExtBreakpointCfg
881
;                                    |||+--------- BdmKeepRClock
882
;                                    ||+---------- BdmCaliRClock
883
;                                    |+----------- BdmKeepBCD
884
;                                    +------------ BdmUserKernel
885
 
886
#set      BDM_BAUDRATE    115200   ; <<< set Baudrate in Bits/s for BDM
887
 
888
#set      BDM_EXT_CONFIG  0xFFFFFF ; <<< set external Config/Kernel
889
 
890
#set      BDM_WD_PATTERN  0x00     ; <<< set watchdog pattern
891
 
892
#set      BDM_PFCS0       0x0000   ; <<< set default breakpoint
893
#set      BDM_PFCS1       0x0000   ;     configurations
894
#set      BDM_PFCS2       0x0000
895
#set      BDM_PFCS3       0x0000
896
 
897
#set      BDM_PFA0        0xFFFFFF ; <<< set address
898
#set      BDM_PFA1        0xFFFFFF ;     configurations
899
#set      BDM_PFA2        0xFFFFFF
900
#set      BDM_PFA3        0xFFFFFF
901
#set      BDM_PFA4        0xFFFFFF
902
#set      BDM_PFA5        0xFFFFFF
903
#set      BDM_PFA6        0xFFFFFF
904
#set      BDM_PFA7        0xFFFFFF
905
 
906
#set      BDM_PFD0        0xFFFF   ; <<< set patch data
907
#set      BDM_PFD1        0xFFFF   ;     configurations
908
#set      BDM_PFD2        0xFFFF
909
#set      BDM_PFD3        0xFFFF
910
#set      BDM_PFD4        0xFFFF
911
#set      BDM_PFD5        0xFFFF
912
#set      BDM_PFD6        0xFFFF
913
#set      BDM_PFD7        0xFFFF
914
 
915
 
916
; <<< END OF SETTINGS >>>
917
 
918
;====================================================================
919
; 5  Section and Data Declaration
920
;====================================================================
921
 
922
;====================================================================
923
; 5.1  Several fixed addresses (fixed for MB963xx controllers)
924
;====================================================================
925
 
926
MCSRA      .EQU      0x03F1          ; Flash A Memory configuration register
927
MTCRA      .EQU      0x03F2          ; Flash A Memory timing register
928
MCSRB      .EQU      0x03F5          ; Flash B Memory configuration register
929
MTCRB      .EQU      0x03F6          ; Flash B Memory timing register
930
ROMM       .EQU      0x03AE          ; ROM mirror control register
931
CKSR       .EQU      0x0401          ; Clock select control register
932
CKSSR      .EQU      0x0402          ; Clock stabilization select register
933
CKMR       .EQU      0x0403          ; Clock monitor register
934
CKFCR      .EQU      0x0404          ; Clock frequency control register
935
PLLCR      .EQU      0x0406          ; PLL control register
936
VRCR       .EQU      0x042C          ; Voltage Regulator Control register
937
ICE01      .EQU      0x0041          ; Input capture 0/1 source
938
ICE67      .EQU      0x0053          ; Input capture 6/7 source
939
ICE89      .EQU      0x0515          ; Input capture 8/9 source
940
ICE1011    .EQU      0x051B          ; Input capture 10/11 source
941
ICS89      .EQU      0x0514          ; Input capture 8/9 edge select
942
ICS1011    .EQU      0x051A          ; Input capture 10/11 edge select
943
TCCSL2     .EQU      0x0502          ; Free running timer 2 control/status register
944
TCCSL3     .EQU      0x0506          ; Free running timer 3 control/status register
945
#if BUSMODE != SINGLE_CHIP           ; only for devices with external bus
946
PIER00     .EQU      0x0444
947
PIER01     .EQU      0x0445
948
PIER02     .EQU      0x0446
949
PIER03     .EQU      0x0447
950
PIER12     .EQU      0x0450
951
EACL0      .EQU      0x06E0
952
EACH0      .EQU      0x06E1
953
EACL1      .EQU      0x06E2
954
EACH1      .EQU      0x06E3
955
EACL2      .EQU      0x06E4
956
EACH2      .EQU      0x06E5
957
EACL3      .EQU      0x06E6
958
EACH3      .EQU      0x06E7
959
EACL4      .EQU      0x06E8
960
EACH4      .EQU      0x06E9
961
EACL5      .EQU      0x06EA
962
EACH5      .EQU      0x06EB
963
EAS2       .EQU      0x06EC
964
EAS3       .EQU      0x06ED
965
EAS4       .EQU      0x06EE
966
EAS5       .EQU      0x06EF
967
EBM        .EQU      0x06F0
968
EBCF       .EQU      0x06F1
969
EBAE0      .EQU      0x06F2
970
EBAE1      .EQU      0x06F3
971
EBAE2      .EQU      0x06F4
972
EBCS       .EQU      0x06F5
973
#endif ; BUSMODE != SINGLE_CHIP
974
 
975
;====================================================================
976
; 5.2  Declaration of __near addressed data sections
977
;====================================================================
978
 
979
; sections to be cleared
980
          .SECTION  DATA,      DATA,   ALIGN=2  ; zero clear area
981
          .SECTION  DATA2,     DATA,   ALIGN=2  ; zero clear area
982
          .SECTION  DIRDATA,   DIR,    ALIGN=2  ; zero clear direct
983
          .SECTION  LIBDATA,   DATA,   ALIGN=2  ; zero clear lib area
984
 
985
; sections to be initialised with start-up values
986
          .SECTION  INIT,      DATA,   ALIGN=2  ; initialised area
987
          .SECTION  INIT2,     DATA,   ALIGN=2  ; initialised area
988
          .SECTION  DIRINIT,   DIR,    ALIGN=2  ; initialised dir
989
          .SECTION  LIBINIT,   DATA,   ALIGN=2  ; initialised lib area
990
#if CONSTDATA == RAMCONST
991
          .SECTION  CINIT,     DATA,   ALIGN=2  ; initialised const
992
          .SECTION  CINIT2,    DATA,   ALIGN=2  ; initialised const
993
#endif
994
 
995
; sections containing start-up values for initialised sections above
996
          .SECTION  DCONST,    CONST,  ALIGN=2  ; DINIT initialisers
997
          .SECTION  DIRCONST, DIRCONST,ALIGN=2  ; DIRINIT initialisers
998
          .SECTION  LIBDCONST, CONST,  ALIGN=2  ; LIBDCONST init val
999
 
1000
          ; following section is either copied to CINIT (RAMCONST) or
1001
          ; mapped by ROM-mirror function (ROMCONST)
1002
          .SECTION  CONST,     CONST,  ALIGN=2  ; CINIT initialisers
1003
          .SECTION  CONST2,    CONST,  ALIGN=2  ; CINIT initialisers
1004
 
1005
;====================================================================
1006
; 5.3  Declaration of RAMCODE section and labels
1007
;====================================================================
1008
 
1009
#if COPY_RAMCODE == ON
1010
          .SECTION  RAMCODE,   CODE,  ALIGN=1
1011
          .IMPORT _RAM_RAMCODE                  ; provided by linker
1012
          .IMPORT _ROM_RAMCODE                  ; provided by linker
1013
#endif
1014
 
1015
 
1016
;====================================================================
1017
; 5.4  Declaration of sections containing other sections description
1018
;====================================================================
1019
 
1020
; DCLEAR contains start address and size of all sections to be cleared
1021
; DTRANS contains source and destination address and size of all
1022
; sections to be initialised with start-up values
1023
; The compiler automatically adds a descriptor for each __far addressed
1024
; data section to DCLEAR or DTRANS. These __far sections are separated
1025
; for each C-module.
1026
 
1027
; In addition the start-up file adds the descriptors of the previously
1028
; declared __near section here. This way the same code in the start-up
1029
; file can be used for initialising all sections.
1030
 
1031
   .SECTION  DCLEAR,    CONST,  ALIGN=2  ; zero clear table
1032
   ;    Address         Bank            Size
1033
   .DATA.H DATA,    BNKSEC DATA,    SIZEOF(DATA   )
1034
   .DATA.H DIRDATA, BNKSEC DIRDATA, SIZEOF(DIRDATA)
1035
   .DATA.H LIBDATA, BNKSEC LIBDATA, SIZEOF(LIBDATA)
1036
 
1037
   .SECTION  DTRANS,    CONST,  ALIGN=2  ; copy table
1038
   ;    Address         Bank               Address     Bank          Size
1039
   .DATA.H DCONST,   BNKSEC DCONST,   INIT,   BNKSEC INIT,   SIZEOF INIT
1040
   .DATA.H DIRCONST, BNKSEC DIRCONST, DIRINIT,BNKSEC DIRINIT,SIZEOF DIRINIT
1041
   .DATA.H LIBDCONST,BNKSEC LIBDCONST,LIBINIT,BNKSEC LIBINIT,SIZEOF LIBINIT
1042
 
1043
#if CONSTDATA == RAMCONST
1044
   .DATA.H CONST,    BNKSEC CONST,    CINIT,  BNKSEC CINIT,  SIZEOF CINIT
1045
   .DATA.H CONST2,   BNKSEC CONST,    CINIT2, BNKSEC CINIT2, SIZEOF CINIT2
1046
#endif
1047
 
1048
#if COPY_RAMCODE == ON
1049
   .DATA.L _ROM_RAMCODE, _RAM_RAMCODE
1050
   .DATA.H SIZEOF RAMCODE
1051
#endif
1052
 
1053
;====================================================================
1054
; 5.5  Stack area and stack top definition/declaration
1055
;====================================================================
1056
#if STACK_RESERVE == ON
1057
            .SECTION  SSTACK, STACK, ALIGN=2
1058
 
1059
            .EXPORT __systemstack, __systemstack_top
1060
__systemstack:
1061
            .RES.B    (STACK_SYS_SIZE + 1) & 0xFFFE
1062
__systemstack_top:
1063
SSTACK_TOP:
1064
 
1065
            .SECTION  USTACK, STACK, ALIGN=2
1066
 
1067
            .EXPORT __userstack, __userstack_top
1068
__userstack:
1069
            .RES.B    (STACK_USR_SIZE + 1) & 0xFFFE
1070
__userstack_top:
1071
USTACK_TOP:
1072
 
1073
#else
1074
            .SECTION  SSTACK, STACK, ALIGN=2
1075
            .SECTION  USTACK, STACK, ALIGN=2
1076
 
1077
            .IMPORT __systemstack, __systemstack_top
1078
            .IMPORT __userstack, __userstack_top
1079
#endif
1080
 
1081
;====================================================================
1082
; 5.6  Direct page register dummy label definition
1083
;====================================================================
1084
 
1085
          .SECTION  DIRDATA  ; zero clear direct
1086
DIRDATA_S:                                      ; label for DPR init
1087
 
1088
; This label is used to get the page of the __direct data.
1089
; Depending on the linkage order of this startup file the label is
1090
; placed anywhere within the __direct data page. However, the
1091
; statement "PAGE (DIRDATA_S)" is processed. Therefore, the lower
1092
; 8 Bit of the address of DIRDATA_S are not relevant and this feature
1093
; becomes linkage order independent.
1094
; Note, the linker settings have to make sure that all __direct
1095
; data are located within the same physical page (256 Byte block).
1096
 
1097
;====================================================================
1098
; 5.7  Set Flash Security
1099
;====================================================================
1100
 
1101
          .SECTION FLASH_A_SECURITY, CONST, LOCATE=H'DF0000
1102
#if FLASH_A_SECURITY_ENABLE == 0
1103
              .DATA.W 0xFFFF ; Security DISABLED
1104
              .SKIP   16
1105
#else FLASH_A_SECURITY_ENABLE == 1
1106
              .DATA.W 0x0099 ; Security ENABLED
1107
              .DATA.W ((FLASH_A_UNLOCK_1  << 8) | FLASH_A_UNLOCK_0)
1108
              .DATA.W ((FLASH_A_UNLOCK_3  << 8) | FLASH_A_UNLOCK_2)
1109
              .DATA.W ((FLASH_A_UNLOCK_5  << 8) | FLASH_A_UNLOCK_4)
1110
              .DATA.W ((FLASH_A_UNLOCK_7  << 8) | FLASH_A_UNLOCK_6)
1111
              .DATA.W ((FLASH_A_UNLOCK_9  << 8) | FLASH_A_UNLOCK_8)
1112
              .DATA.W ((FLASH_A_UNLOCK_11 << 8) | FLASH_A_UNLOCK_10)
1113
              .DATA.W ((FLASH_A_UNLOCK_13 << 8) | FLASH_A_UNLOCK_12)
1114
              .DATA.W ((FLASH_A_UNLOCK_15 << 8) | FLASH_A_UNLOCK_14)
1115
#endif
1116
              .SKIP   4
1117
              .SKIP   6
1118
 
1119
#if FLASH_B_AVAILABLE == ON
1120
          .SECTION FLASH_B_SECURITY, CONST, LOCATE=H'DE0000
1121
#  if FLASH_B_SECURITY_ENABLE == 0
1122
              .DATA.W 0xFFFF ; Security DISABLED
1123
              .SKIP   16
1124
#  else FLASH_B_SECURITY_ENABLE == 1
1125
              .DATA.W 0x0099 ; Security ENABLED
1126
              .DATA.W ((FLASH_B_UNLOCK_1  << 8) | FLASH_B_UNLOCK_0)
1127
              .DATA.W ((FLASH_B_UNLOCK_3  << 8) | FLASH_B_UNLOCK_2)
1128
              .DATA.W ((FLASH_B_UNLOCK_5  << 8) | FLASH_B_UNLOCK_4)
1129
              .DATA.W ((FLASH_B_UNLOCK_7  << 8) | FLASH_B_UNLOCK_6)
1130
              .DATA.W ((FLASH_B_UNLOCK_9  << 8) | FLASH_B_UNLOCK_8)
1131
              .DATA.W ((FLASH_B_UNLOCK_11 << 8) | FLASH_B_UNLOCK_10)
1132
              .DATA.W ((FLASH_B_UNLOCK_13 << 8) | FLASH_B_UNLOCK_12)
1133
              .DATA.W ((FLASH_B_UNLOCK_15 << 8) | FLASH_B_UNLOCK_14)
1134
#  endif
1135
              .SKIP   4
1136
              .SKIP   6
1137
#endif ; FLASH_B_AVAILABLE == ON
1138
 
1139
 
1140
;====================================================================
1141
; 5.8  Set Flash write protection
1142
;====================================================================
1143
 
1144
          .SECTION FLASH_A_PROTECT, CONST, LOCATE=H'DF001C
1145
#if FLASH_A_WRITE_PROTECT == ON
1146
          .DATA.L 0x292D3A7B
1147
          .DATA.B ~((PROTECT_SECTOR_SA3 << 3) | (PROTECT_SECTOR_SA2 << 2) | (PROTECT_SECTOR_SA1 << 1) | PROTECT_SECTOR_SA0)
1148
          .DATA.E 0xFFFFFF
1149
          .DATA.B ~((PROTECT_SECTOR_SA39 << 7) | (PROTECT_SECTOR_SA38 << 6) | (PROTECT_SECTOR_SA37 << 5) | (PROTECT_SECTOR_SA36 << 4) | (PROTECT_SECTOR_SA35 << 3) | (PROTECT_SECTOR_SA34 << 2) | (PROTECT_SECTOR_SA33 << 1) | PROTECT_SECTOR_SA32)
1150
          .SKIP   3
1151
#else
1152
          .DATA.L 0xFFFFFFFF
1153
          .SKIP   8
1154
#endif ; FLASH_A_WRITE_PROTECT
1155
          .SKIP   8
1156
 
1157
#if FLASH_B_AVAILABLE == ON
1158
          .SECTION FLASH_B_PROTECT, CONST, LOCATE=H'DE001C
1159
#  if FLASH_B_WRITE_PROTECT == ON
1160
          .DATA.L 0x292D3A7B
1161
          .DATA.B ~((PROTECT_SECTOR_SB3 << 3) | (PROTECT_SECTOR_SB2 << 2) | (PROTECT_SECTOR_SB1 << 1) | PROTECT_SECTOR_SB0)
1162
          .SKIP   7
1163
#  else
1164
          .DATA.L 0xFFFFFFFF
1165
          .SKIP   8
1166
#  endif ; FLASH_B_WRITE_PROTECT
1167
          .SKIP   8
1168
#endif ; FLASH_B_AVAILABLE == ON
1169
 
1170
 
1171
;====================================================================
1172
; 5.9  Debug address specification
1173
;====================================================================
1174
;
1175
; BDM configuration section should always be defined for later
1176
; configuration by e.g. debugger tool or (special) programmer tool.
1177
 
1178
          .SECTION BDM_CONFIG, CONST, LOCATE=H'DF0040
1179
 
1180
#if BACKGROUND_DEBUGGING == ON
1181
 
1182
          .DATA.L 0x292D3A7B
1183
 
1184
          .ORG    H'DF0044
1185
          .DATA.W BDM_CONFIGURATION
1186
 
1187
          .ORG    H'DF0046
1188
#  if ((SERIES == MB96340) && (DEVICE < 3))
1189
#    error Device does not support background debugging
1190
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1191
 
1192
#  if ((SERIES == MB96340) && (DEVICE < 12))
1193
          .DATA.W (D'16 * CRYSTAL + BDM_BAUDRATE) / BDM_BAUDRATE
1194
#  else
1195
          .DATA.W (D'32 * CRYSTAL + BDM_BAUDRATE) / BDM_BAUDRATE
1196
#  endif ; ((SERIES == MB96340) && (DEVICE < 12))
1197
 
1198
          .ORG    H'DF0048
1199
          .DATA.E BDM_EXT_CONFIG
1200
 
1201
          .ORG    H'DF004B
1202
          .DATA.B BDM_WD_PATTERN
1203
 
1204
          .ORG    H'DF0050
1205
          .DATA.W BDM_PFCS0
1206
          .DATA.W BDM_PFCS1
1207
          .DATA.W BDM_PFCS2
1208
          .DATA.W BDM_PFCS3
1209
 
1210
          .DATA.E BDM_PFA0, BDM_PFA1
1211
          .DATA.E BDM_PFA2, BDM_PFA3
1212
          .DATA.E BDM_PFA4, BDM_PFA5
1213
          .DATA.E BDM_PFA6, BDM_PFA7
1214
 
1215
          .DATA.W BDM_PFD0, BDM_PFD1
1216
          .DATA.W BDM_PFD2, BDM_PFD3
1217
          .DATA.W BDM_PFD4, BDM_PFD5
1218
          .DATA.W BDM_PFD6, BDM_PFD7
1219
#else
1220
          .DATAB.B 64, 0xFF        ; fill section with 0xFF
1221
 
1222
#endif ; BACKGROUND_DEBUGGING == ON
1223
 
1224
          .ORG    0xDF0080
1225
 
1226
;====================================================================
1227
; 6  Start-Up Code
1228
;====================================================================
1229
 
1230
;====================================================================
1231
; 6.1  Import external symbols
1232
;====================================================================
1233
 
1234
          .IMPORT   _main                    ; user code entrance
1235
#if CLIBINIT == ON
1236
          .IMPORT   __stream_init
1237
          .IMPORT   _exit
1238
          .EXPORT   __exit
1239
#endif
1240
          .EXPORT   _start
1241
 
1242
;====================================================================
1243
;   ___  _____   __    ___  _____
1244
;  /       |    /  \  |   \   |
1245
;  \___    |   |    | |___/   |
1246
;      \   |   |----| |  \    |
1247
;   ___/   |   |    | |   \   |      Begin of actual code section
1248
;
1249
;====================================================================
1250
          .SECTION  CODE_START, CODE, ALIGN=1
1251
 
1252
;====================================================================
1253
; 6.2  Program start (the reset vector should point here)
1254
;====================================================================
1255
_start:
1256
          NOP  ; This NOP is only for debugging. On debugger the IP
1257
               ; (instruction pointer) should point here after reset
1258
 
1259
;====================================================================
1260
; 6.3  "NOT RESET YET" WARNING
1261
;====================================================================
1262
notresetyet:
1263
          NOP  ; read hint below!!!!!!!
1264
; If the debugger stays at this NOP after download, the controller has
1265
; not been reset yet. In order to reset all hardware registers it is
1266
; highly recommended to reset the controller.
1267
; However, if no reset vector has been defined on purpose, this start
1268
; address can also be used.
1269
; This mechanism is using the .END instruction at the end of this mo-
1270
; dule. It is not necessary for controller operation but improves
1271
; security during debugging (mainly emulator debugger).
1272
; If the debugger stays here after a single step from label "_start"
1273
; to label "notresetyet", this note can be ignored.
1274
 
1275
;====================================================================
1276
; 6.4  Initialisation of processor status
1277
;====================================================================
1278
          AND  CCR, #0x80          ; disable interrupts
1279
          MOV  ILM,#7              ; set interrupt level mask to ALL
1280
          MOV  RP,#REGBANK         ; set register bank pointer
1281
 
1282
;====================================================================
1283
; 6.5  Set clock ratio (ignore subclock)
1284
;====================================================================
1285
          MOVN A, #0               ; set bank 0 in DTB for the case that
1286
          MOV  DTB, A              ; start-up code was not jumped by reset
1287
 
1288
          MOV  CKSSR, #(0xF8 | MC_STAB_TIME)  ; set clock stabilization time
1289
 
1290
#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ)
1291
          MOV  CKSR,  #0xB5
1292
#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ)
1293
 
1294
#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ)
1295
          CLRB MCSRA:4
1296
          CLRB MCSRA:5
1297
          CLRB MCSRB:4
1298
          CLRB MCSRB:5
1299
          MOVW CKFCR, #0x1111
1300
          MOVW MTCRA, #0x2128
1301
#    if FLASH_B_AVAILABLE == ON
1302
          MOVW MTCRB, #0x2128
1303
#    endif ; FLASH_B_AVAILABLE == ON
1304
          MOV  CKSR,  #0xB5
1305
#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ)
1306
 
1307
#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ)
1308
#  if ((SERIES == MB96340) && (DEVICE < 3))
1309
          MOVW PLLCR, #0x00E0
1310
          MOV  CKSR,  #0xFA
1311
#  else
1312
          MOVW PLLCR, #0x00A1
1313
          MOVW CKFCR, #0x1111
1314
          MOVW MTCRA, #0x2128
1315
#    if FLASH_B_AVAILABLE == ON
1316
          MOVW MTCRB, #0x2128
1317
#    endif ; FLASH_B_AVAILABLE == ON
1318
          MOV  CKSR,  #0xFA
1319
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1320
#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ)
1321
 
1322
#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ)
1323
#  if ((SERIES == MB96340) && (DEVICE < 3))
1324
          MOVW PLLCR, #0x0060
1325
          CLRB MCSRA:4
1326
          CLRB MCSRA:5
1327
          CLRB MCSRB:4
1328
          CLRB MCSRB:5
1329
          MOVW CKFCR, #0x1111
1330
          MOV  CKSR,  #0xFA
1331
#  else
1332
          MOVW PLLCR, #0x0060
1333
          MOVW CKFCR, #0x1111
1334
          MOVW MTCRA, #0x2128
1335
#    if FLASH_B_AVAILABLE == ON
1336
          MOVW MTCRB, #0x2128
1337
#    endif ; FLASH_B_AVAILABLE == ON
1338
          MOV  CKSR,  #0xFA
1339
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1340
#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ)
1341
 
1342
#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ)
1343
#  if ((SERIES == MB96340) && (DEVICE < 3))
1344
          MOVW PLLCR, #0x00A1
1345
          MOV  CKSR,  #0xFA
1346
#  else
1347
          MOVW PLLCR, #0x0043
1348
          MOVW CKFCR, #0x1111
1349
          MOVW MTCRA, #0x2128
1350
#    if FLASH_B_AVAILABLE == ON
1351
          MOVW MTCRB, #0x2128
1352
#    endif ; FLASH_B_AVAILABLE == ON
1353
          MOV  CKSR,  #0xFA
1354
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1355
#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ)
1356
 
1357
#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ)
1358
#  if ((SERIES == MB96340) && (DEVICE < 3))
1359
          MOVW PLLCR, #0x0060
1360
          MOV  CKSR,  #0xFA
1361
#  else
1362
          MOVW PLLCR, #0x0081
1363
          MOVW CKFCR, #0x1111
1364
          MOVW MTCRA, #0x2128
1365
#    if FLASH_B_AVAILABLE == ON
1366
          MOVW MTCRB, #0x2128
1367
#    endif ; FLASH_B_AVAILABLE == ON
1368
          MOV  CKSR,  #0xFA
1369
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1370
#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ)
1371
 
1372
#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ)
1373
#  if ((SERIES == MB96340) && (DEVICE < 3))
1374
          MOVW PLLCR, #0x0062
1375
          MOV  CKSR,  #0xFA
1376
#  else
1377
          MOVW PLLCR, #0x0025
1378
          MOVW CKFCR, #0x1111
1379
          MOVW MTCRA, #0x2128
1380
#    if FLASH_B_AVAILABLE == ON
1381
          MOVW MTCRB, #0x2128
1382
#    endif ; FLASH_B_AVAILABLE == ON
1383
          MOV  CKSR,  #0xFA
1384
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1385
#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ)
1386
 
1387
#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ)
1388
#  if ((SERIES == MB96340) && (DEVICE < 3))
1389
          MOVW PLLCR, #0x0061
1390
          CLRB MCSRA:4
1391
          CLRB MCSRA:5
1392
          CLRB MCSRB:4
1393
          CLRB MCSRB:5
1394
          MOVW CKFCR, #0x1111
1395
          MOV  CKSR,  #0xFA
1396
#  else
1397
          MOVW PLLCR, #0x0061
1398
          MOVW CKFCR, #0x1111
1399
          MOVW MTCRA, #0x2128
1400
#    if FLASH_B_AVAILABLE == ON
1401
          MOVW MTCRB, #0x2128
1402
#    endif ; FLASH_B_AVAILABLE == ON
1403
          MOV  CKSR,  #0xFA
1404
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1405
#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ)
1406
 
1407
#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ)
1408
#  if ((SERIES == MB96340) && (DEVICE < 3))
1409
          MOVW PLLCR, #0x0043
1410
          MOV  CKSR,  #0xFA
1411
#  else
1412
          MOVW PLLCR, #0x0027
1413
          MOVW CKFCR, #0x1111
1414
          MOVW MTCRA, #0x2128
1415
          MOV  MCSRA, #0x70
1416
#    if FLASH_B_AVAILABLE == ON
1417
          MOVW MTCRB, #0x2128
1418
          MOV  MCSRB, #0x70
1419
#    endif ; FLASH_B_AVAILABLE == ON
1420
          MOV  VRCR,  #0xF6
1421
          MOV  CKSR,  #0xFA
1422
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1423
#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ)
1424
 
1425
#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ)
1426
#  if ((SERIES == MB96340) && (DEVICE < 3))
1427
          MOVW PLLCR, #0x0081
1428
          MOV  CKSR,  #0xFA
1429
#  else
1430
          MOVW PLLCR, #0x0003
1431
          MOVW CKFCR, #0x1111
1432
          MOVW MTCRA, #0x2128
1433
          MOV  MCSRA, #0x70
1434
#    if FLASH_B_AVAILABLE == ON
1435
          MOVW MTCRB, #0x2128
1436
          MOV  MCSRB, #0x70
1437
#    endif ; FLASH_B_AVAILABLE == ON
1438
          MOV  VRCR,  #0xF6
1439
          MOV  CKSR,  #0xFA
1440
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1441
#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ)
1442
 
1443
#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ)
1444
#  if ((SERIES == MB96340) && (DEVICE < 3))
1445
          MOVW PLLCR, #0x0025
1446
          MOVW CKFCR, #0x1001
1447
          MOV  CKSR,  #0xFA
1448
#  else
1449
          MOVW PLLCR, #0x000B
1450
          MOVW CKFCR, #0x3111
1451
          MOVW MTCRA, #0x4C09
1452
#    if FLASH_B_AVAILABLE == ON
1453
          MOVW MTCRB, #0x4C09
1454
#    endif ; FLASH_B_AVAILABLE == ON
1455
          MOV  CKSR,  #0xFA
1456
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1457
#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ)
1458
 
1459
#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ)
1460
#  if ((SERIES == MB96340) && (DEVICE < 3))
1461
          MOVW PLLCR, #0x0082
1462
          MOVW CKFCR, #0x1001
1463
          MOV  CKSR,  #0xFA
1464
#  else
1465
          MOVW PLLCR, #0x0005
1466
          MOVW CKFCR, #0x3111
1467
          MOVW MTCRA, #0x4C09
1468
#    if FLASH_B_AVAILABLE == ON
1469
          MOVW MTCRB, #0x4C09
1470
#    endif ; FLASH_B_AVAILABLE == ON
1471
          MOV  CKSR,  #0xFA
1472
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1473
#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ)
1474
 
1475
#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ)
1476
#  if ((SERIES == MB96340) && (DEVICE < 3))
1477
#    error Setting prohibited due to 16FXFL0014
1478
#  else
1479
          MOVW PLLCR, #0x0027
1480
          MOVW CKFCR, #0x1001
1481
          MOVW MTCRA, #0x2129
1482
          MOV  MCSRA, #0x70
1483
#    if FLASH_B_AVAILABLE == ON
1484
          MOVW MTCRB, #0x2129
1485
          MOV  MCSRB, #0x70
1486
#    endif ; FLASH_B_AVAILABLE == ON
1487
          MOV  VRCR,  #0xF6
1488
          MOV  CKSR,  #0xFA
1489
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1490
#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ)
1491
 
1492
#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ)
1493
#  if ((SERIES == MB96340) && (DEVICE < 3))
1494
#    error Setting prohibited due to 16FXFL0014
1495
#  else
1496
          MOVW PLLCR, #0x0003
1497
          MOVW CKFCR, #0x1001
1498
          MOVW MTCRA, #0x2129
1499
          MOV  MCSRA, #0x70
1500
#    if FLASH_B_AVAILABLE == ON
1501
          MOVW MTCRB, #0x2129
1502
          MOV  MCSRB, #0x70
1503
#    endif ; FLASH_B_AVAILABLE == ON
1504
          MOV  VRCR,  #0xF6
1505
          MOV  CKSR,  #0xFA
1506
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1507
#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP2_16MHZ)
1508
 
1509
#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ)
1510
#  if ((SERIES == MB96340) && (DEVICE < 3))
1511
#    error Setting prohibited due to 16FXFL0014
1512
#  else
1513
          MOVW PLLCR, #0x0027
1514
          MOVW CKFCR, #0x1101
1515
          MOVW MTCRA, #0x2129
1516
          MOV  MCSRA, #0x70
1517
#    if FLASH_B_AVAILABLE == ON
1518
          MOVW MTCRB, #0x2129
1519
          MOV  MCSRB, #0x70
1520
#    endif ; FLASH_B_AVAILABLE == ON
1521
          MOV  VRCR,  #0xF6
1522
          MOV  CKSR,  #0xFA
1523
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1524
#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ)
1525
 
1526
#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ)
1527
#  if ((SERIES == MB96340) && (DEVICE < 3))
1528
#    error Setting prohibited due to 16FXFL0014
1529
#  else
1530
          MOVW PLLCR, #0x0003
1531
          MOVW CKFCR, #0x1101
1532
          MOVW MTCRA, #0x2129
1533
          MOV  MCSRA, #0x70
1534
#    if FLASH_B_AVAILABLE == ON
1535
          MOVW MTCRB, #0x2129
1536
          MOV  MCSRB, #0x70
1537
#    endif ; FLASH_B_AVAILABLE == ON
1538
          MOV  VRCR,  #0xF6
1539
          MOV  CKSR,  #0xFA
1540
#  endif ; ((SERIES == MB96340) && (DEVICE < 3))
1541
#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_32MHZ_CLKP1_16MHZ_CLKP2_16MHZ)
1542
 
1543
#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ)
1544
          MOVW PLLCR, #0x0017
1545
          MOVW CKFCR, #0x5111
1546
          MOVW MTCRA, #0x6E3D
1547
          MOV  MCSRA, #0x70
1548
#  if FLASH_B_AVAILABLE == ON
1549
          MOVW MTCRB, #0x6E3D
1550
          MOV  MCSRB, #0x70
1551
#  endif ; FLASH_B_AVAILABLE == ON
1552
          MOV  VRCR,  #0xF6
1553
          MOV  CKSR,  #0xFA
1554
#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ)
1555
 
1556
#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ)
1557
          MOVW PLLCR, #0x000B
1558
          MOVW CKFCR, #0x5111
1559
          MOVW MTCRA, #0x6E3D
1560
          MOV  MCSRA, #0x70
1561
#  if FLASH_B_AVAILABLE == ON
1562
          MOVW MTCRB, #0x6E3D
1563
          MOV  MCSRB, #0x70
1564
#  endif ; FLASH_B_AVAILABLE == ON
1565
          MOV  VRCR,  #0xF6
1566
          MOV  CKSR,  #0xFA
1567
#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ)
1568
 
1569
#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP1_32MHZ_CLKP2_16MHZ)
1570
          MOVW PLLCR, #0x0017
1571
          MOVW CKFCR, #0x5211
1572
          MOVW MTCRA, #0x6E3D
1573
          MOV  MCSRA, #0x70
1574
#  if FLASH_B_AVAILABLE == ON
1575
          MOVW MTCRB, #0x6E3D
1576
          MOV  MCSRB, #0x70
1577
#  endif ; FLASH_B_AVAILABLE == ON
1578
          MOV  VRCR,  #0xF6
1579
          MOV  CKSR,  #0xFA
1580
#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP1_32MHZ_CLKP2_16MHZ)
1581
 
1582
#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP1_32MHZ_CLKP2_16MHZ)
1583
          MOVW PLLCR, #0x000B
1584
          MOVW CKFCR, #0x5211
1585
          MOVW MTCRA, #0x6E3D
1586
          MOV  MCSRA, #0x70
1587
#  if FLASH_B_AVAILABLE == ON
1588
          MOVW MTCRB, #0x6E3D
1589
          MOV  MCSRB, #0x70
1590
#  endif ; FLASH_B_AVAILABLE == ON
1591
          MOV  VRCR,  #0xF6
1592
          MOV  CKSR,  #0xFA
1593
#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_48MHZ_CLKP1_32MHZ_CLKP2_16MHZ)
1594
 
1595
#if (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ)
1596
          MOVW PLLCR, #0x000D
1597
          MOVW CKFCR, #0x3001
1598
          MOVW MTCRA, #0x233A
1599
          MOV  MCSRA, #0x70
1600
#  if FLASH_B_AVAILABLE == ON
1601
          MOVW MTCRB, #0x233A
1602
          MOV  MCSRB, #0x70
1603
#  endif ; FLASH_B_AVAILABLE == ON
1604
          MOV  VRCR,  #0xF6
1605
          MOV  CKSR,  #0xFA
1606
#endif ; (CRYSTAL == FREQ_4MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ)
1607
 
1608
#if (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ)
1609
          MOVW PLLCR, #0x0006
1610
          MOVW CKFCR, #0x3001
1611
          MOVW MTCRA, #0x233A
1612
          MOV  MCSRA, #0x70
1613
#  if FLASH_B_AVAILABLE == ON
1614
          MOVW MTCRB, #0x233A
1615
          MOV  MCSRB, #0x70
1616
#  endif ; FLASH_B_AVAILABLE == ON
1617
          MOV  VRCR,  #0xF6
1618
          MOV  CKSR,  #0xFA
1619
#endif ; (CRYSTAL == FREQ_8MHZ) && (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ)
1620
 
1621
 
1622
;====================================================================
1623
; 6.6  Set external bus configuaration
1624
;====================================================================
1625
 
1626
#if BUSMODE != SINGLE_CHIP         ; ext bus used
1627
           MOV  EBCF, #((HOLD_REQ << 7) | (EXT_READY << 6) | (EXT_CLOCK_ENABLE << 5) | (EXT_CLOCK_INVERT << 4) | (EXT_CLOCK_SUSPEND << 3) | EXT_CLOCK_DIVISION)
1628
           MOV  EBAE0,#ADDR_PINS_7_0
1629
           MOV  EBAE1,#ADDR_PINS_15_8
1630
           MOV  EBAE2,#ADDR_PINS_23_16
1631
           MOV  EBCS, #((ADDRESS_STROBE_LVL << 6) | (ADDRESS_STROBE << 5) | (READ_STROBE << 4) | (HIGH_WRITE_STROBE << 3) | (LOW_WRITE_STROBE << 2) | (HIGH_BYTE_SIGNAL << 1) | LOW_BYTE_SIGNAL)
1632
           MOVW EACL0,#CS0_CONFIG
1633
           MOVW EACL1,#CS1_CONFIG
1634
           MOVW EACL2,#CS2_CONFIG
1635
           MOVW EACL3,#CS3_CONFIG
1636
           MOVW EACL4,#CS4_CONFIG
1637
           MOVW EACL5,#CS5_CONFIG
1638
           MOV  EAS2, #CS2_START
1639
           MOV  EAS3, #CS3_START
1640
           MOV  EAS4, #CS4_START
1641
           MOV  EAS5, #CS5_START
1642
           MOV  EBM,  #((ADDRESSMODE << 7) | ((BUSMODE-1) << 6) | (CHIP_SELECT5 << 5) | (CHIP_SELECT4 << 4) | (CHIP_SELECT3 << 3) | (CHIP_SELECT2 << 2) | (CHIP_SELECT1 << 1) | CHIP_SELECT0) ; set address mode, ROM access
1643
 
1644
#  if SERIES == MB96320 || SERIES == MB96330 || SERIES == MB96340 || SERIES == MB96350
1645
           MOV  PIER00,#0xFF
1646
#    if (CS0_CONFIG & 0x0080) == 0 || (CS1_CONFIG & 0x0080) == 0 || (CS2_CONFIG & 0x0080) == 0 || (CS3_CONFIG & 0x0080) == 0 || (CS4_CONFIG & 0x0080) == 0 || (CS5_CONFIG & 0x0080) == 0
1647
           MOV  PIER01,#0xFF
1648
#    endif
1649
#    if HOLD_REQ == ON
1650
           SETB PIER03:4
1651
#    endif
1652
#    if EXT_READY == ON
1653
           SETB PIER03:6
1654
#    endif
1655
 
1656
#  else if SERIES == MB96370 || SERIES == MB96380
1657
           MOV  PIER01,#0xFF
1658
#    if (CS0_CONFIG & 0x0080) == 0 || (CS1_CONFIG & 0x0080) == 0 || (CS2_CONFIG & 0x0080) == 0 || (CS3_CONFIG & 0x0080) == 0 || (CS4_CONFIG & 0x0080) == 0 || (CS5_CONFIG & 0x0080) == 0
1659
           MOV  PIER02,#0xFF
1660
#    endif
1661
#    if HOLD_REQ == ON
1662
           SETB PIER12:7
1663
#    endif
1664
#    if EXT_READY == ON
1665
           SETB PIER00:2
1666
#    endif
1667
#  endif
1668
 
1669
#endif
1670
 
1671
#if BUSMODE == INTROM_EXTBUS     ; EXTBUS and INTROM/EXTROM
1672
#  if ROMMIRROR == OFF && CONSTDATA == ROMCONST
1673
#    error Mirror function must be ON to mirror internal ROM
1674
#  endif
1675
#endif
1676
 
1677
ROMM_CONFIG    .EQU     ((MIRROR_BANK << 4) | (MIRROR_SIZE << 1) | (ROMMIRROR))
1678
           MOV  ROMM, #ROMM_CONFIG
1679
 
1680
 
1681
;====================================================================
1682
; 6.7  Prepare stacks and set the default stack type
1683
;====================================================================
1684
 
1685
          AND  CCR,#H'DF            ; clear system stack flag
1686
          MOVL A, #(__userstack_top) & ~1
1687
          MOVW SP,A                 ; load offset of stack top to pointer
1688
          SWAPW                     ; swap higher word to AL
1689
          MOV  USB, A               ; set bank
1690
 
1691
#if STACK_FILL == ON                ; preset the stack
1692
          MOV  ADB, A
1693
          MOVW A, #USTACK           ; load start stack address to AL
1694
          MOVW A, #STACK_PATTERN    ; AL -> AH, pattern in AL
1695
          MOVW RW0, #SIZEOF(USTACK) / 2 ; get byte count
1696
          FILSWI    ADB             ; write pattern to stack
1697
#endif
1698
 
1699
          OR   CCR,#H'20            ; set System stack flag
1700
          MOVL A, #(__systemstack_top) & ~1
1701
          MOVW SP,A                 ; load offset of stack top to pointer
1702
          SWAPW                     ; swap higher word to AL
1703
          MOV  SSB, A               ; set bank
1704
 
1705
#if STACK_FILL == ON                ; preset the stack
1706
          MOV  ADB, A
1707
          MOVW A, #SSTACK           ; load start stack address to AL
1708
          MOVW A, #STACK_PATTERN    ; AL -> AH, pattern in AL
1709
          MOVW RW0, #SIZEOF(SSTACK) / 2; get byte count
1710
          FILSWI    ADB             ; write pattern to stack
1711
#endif
1712
 
1713
#if STACKUSE == USRSTACK
1714
          AND  CCR,#H'DF            ; clear system stack flag
1715
#endif
1716
 
1717
 
1718
;   The following macro is needed because of the AUTOMODEL option. If the
1719
;   model is not known while assembling the module, one has to expect
1720
;   completion of streaminit() by RET or RETP. Because RET removes 2 bytes
1721
;   from stack and RETP removes 4 bytes from stack, SP is reloaded.
1722
 
1723
#  macro RELOAD_SP
1724
 
1725
#if STACKUSE == USRSTACK
1726
          MOVW A, #(__userstack_top) & ~1
1727
#else
1728
          MOVW A, #(__systemstack_top) & ~1
1729
#endif
1730
          MOVW SP,A
1731
#  endm
1732
 
1733
 
1734
;====================================================================
1735
; 6.8  Copy initial values to data areas.
1736
;====================================================================
1737
;
1738
; Each C-module has its own __far INIT section. The names are generic.
1739
; DCONST_module contains the initializers for the far data of the one
1740
; module. INIT_module reserves the RAM area, which has to be loaded
1741
; with the data from DCONST_module. ("module" is the name of the *.c
1742
; file)
1743
; All separated DCONST_module/INIT_module areas are described in
1744
; DTRANS section by start addresses and length of each far section.
1745
;   0000 1. source address (ROM)
1746
;   0004 1. destination address (RAM)
1747
;   0008 length of sections 1
1748
;   000A 2. source address  (ROM)
1749
;   000E 2. destination address (RAM)
1750
;   0012 length of sections 2
1751
;   0014 3. source address ...
1752
; In addition the start-up file adds the descriptors of the __near
1753
; sections to this table. The order of the descriptors in this table
1754
; depends on the linkage order.
1755
;====================================================================
1756
          MOV  A, #BNKSEC DTRANS   ; get bank of table
1757
          MOV  DTB, A              ; store bank in DTB
1758
          MOVW RW1, #DTRANS        ; get start offset of table
1759
          OR   CCR, #H'20          ; System stack flag set (SSB used)
1760
          BRA  LABEL2              ; branch to loop condition
1761
LABEL1:
1762
          MOVW A, @RW1+6           ; get bank of destination
1763
          MOV  SSB, A              ; save dest bank in SSB
1764
          MOVW A, @RW1+2           ; get source bank
1765
          MOV  ADB, A              ; save source bank in ADB
1766
          MOVW A, @RW1+4           ; move destination addr in AL
1767
          MOVW A, @RW1             ; AL -> AH, src addr -> AL
1768
          MOVW RW0, @RW1+8         ; number of bytes to copy -> RW0
1769
          MOVSI     SPB, ADB       ; copy data
1770
          MOVN A, #10              ; length of one table entry is 10
1771
          ADDW RW1, A              ; set pointer to next table entry
1772
LABEL2:
1773
          MOVW A, RW1              ; get address of next block
1774
          SUBW A, #DTRANS          ; sub address of first block
1775
          CMPW A, #SIZEOF (DTRANS) ; all blocks processed ?
1776
          BNE  LABEL1              ; if not, branch
1777
 
1778
 
1779
;====================================================================
1780
; 6.9   Clear uninitialized data areas to zero
1781
;====================================================================
1782
;
1783
; Each C-module has its own __far DATA section. The names are generic.
1784
; DATA_module contains the reserved area (RAM) to be cleared.
1785
; ("module" is the name of the *.c file)
1786
; All separated DATA_module areas are described in DCLEAR section by
1787
; start addresses and length of all far section.
1788
;   0000 1. section address (RAM)
1789
;   0004 length of section 1
1790
;   0006 2. section address (RAM)
1791
;   000A length of section 2
1792
;   000C 3. section address (RAM)
1793
;   0010 length of section 3 ...
1794
; In addition the start-up file adds the descriptors of the __near
1795
; sections to this table. The order of the descriptors in this table
1796
; depends on the linkage order.
1797
;====================================================================
1798
          MOV  A, #BNKSEC DCLEAR   ; get bank of table
1799
          MOV  DTB, A              ; store bank in DTB
1800
          MOVW RW1, #DCLEAR        ; get start offset of table
1801
          BRA  LABEL4              ; branch to loop condition
1802
LABEL3:
1803
          MOV  A, @RW1+2           ; get section bank
1804
          MOV  ADB, A              ; save section bank in ADB
1805
          MOVW RW0, @RW1+4         ; number of bytes to copy -> RW0
1806
          MOVW A, @RW1             ; move section addr in AL
1807
          MOVN A, #0               ; AL -> AH, init value -> AL
1808
          FILSI     ADB            ; write 0 to section
1809
          MOVN A, #6               ; length of one table entry is 6
1810
          ADDW RW1, A              ; set pointer to next table entry
1811
LABEL4:
1812
          MOVW A, RW1              ; get address of next block
1813
          SUBW A, #DCLEAR          ; sub address of first block
1814
          CMPW A, #SIZEOF (DCLEAR) ; all blocks processed ?
1815
          BNE  LABEL3              ; if not, branch
1816
 
1817
 
1818
 
1819
;====================================================================
1820
; 6.10  Set Data Bank Register (DTB) and Direct Page Register (DPR)
1821
;====================================================================
1822
          MOV  A,#BNKSEC DATA          ; User data bank offset
1823
          MOV  DTB,A
1824
 
1825
          MOV  A,#PAGE DIRDATA_S       ; User direct page
1826
          MOV  DPR,A
1827
 
1828
;====================================================================
1829
; 6.11  ICU register initialization workaround
1830
;====================================================================
1831
 
1832
#if (UART_SCANNING == ON)
1833
#  if (((SERIES == MB96320) && (DEVICE < 3)) || \
1834
       ((SERIES == MB96350) && (DEVICE < 3)))
1835
          MOVN A, #0
1836
          MOV  TCCSL2, A
1837
          MOV  TCCSL3, A
1838
          MOV  ICE67, A
1839
          MOV  ICE89, A
1840
          MOV  ICE1011, A
1841
          MOV  ICS89, A
1842
          MOV  ICS1011, A
1843
#  endif ; ((SERIES == 96350) && ...
1844
#  if (((SERIES == MB96330) && (DEVICE < 2))  || \
1845
       ((SERIES == MB96340) && (DEVICE < 27)) || \
1846
       ((SERIES == MB96370) && (DEVICE < 3))  || \
1847
       ((SERIES == MB96380) && (DEVICE < 13)))
1848
          MOVN A, #0
1849
          MOV  ICE01, A
1850
          MOV  ICE67, A
1851
#  endif ; (((SERIES == MB96330) && (DEVICE < 2)) || ...
1852
#endif ; (UART_SCANNING == ON)
1853
 
1854
;====================================================================
1855
; 6.12  Wait for clocks to stabilize
1856
;====================================================================
1857
 
1858
#if (CLOCK_SPEED == CPU_4MHZ_MAIN_CLKP2_4MHZ) && (CLOCKWAIT == ON)
1859
no_MC_yet:
1860
          BBC  CKMR:5,no_MC_yet        ; check MCM and wait for
1861
                                       ; Main Clock to stabilize
1862
#endif ; wait for Main Clock
1863
 
1864
#if (((CRYSTAL == FREQ_4MHZ) ||(CRYSTAL == FREQ_8MHZ)) && \
1865
     ((CLOCK_SPEED == CPU_12MHZ_CLKP2_12MHZ) || \
1866
     (CLOCK_SPEED == CPU_16MHZ_CLKP2_16MHZ) || \
1867
     (CLOCK_SPEED == CPU_24MHZ_CLKP2_12MHZ)))
1868
no_PLL_0WS:
1869
          BBC  CKMR:6, no_PLL_0WS
1870
 
1871
#  if ! ((SERIES == MB96340) && (DEVICE < 3))
1872
          MOVW MTCRA, #0x2208
1873
#    if FLASH_B_AVAILABLE == ON
1874
          MOVW MTCRB, #0x2208
1875
#    endif ; FLASH_B_AVAILABLE == ON
1876
#  endif ; ! ((SERIES == MB96340) && (DEVICE < 3))
1877
#endif
1878
 
1879
#if ((CRYSTAL == FREQ_4MHZ) || (CRYSTAL == FREQ_8MHZ)) && \
1880
     ((CLOCK_SPEED == CPU_48MHZ_CLKP2_16MHZ) || \
1881
      (CLOCK_SPEED == CPU_48MHZ_CLKP1_32MHZ_CLKP2_16MHZ)) && \
1882
     ! ((SERIES == MB96340) && (DEVICE < 3))
1883
no_PLL_1WS:
1884
          BBC  CKMR:6, no_PLL_1WS
1885
 
1886
          MOVW MTCRA, #0x6B09
1887
#  if FLASH_B_AVAILABLE == ON
1888
          MOVW MTCRB, #0x6B09
1889
#  endif ; FLASH_B_AVAILABLE == ON
1890
#endif
1891
 
1892
#if (CLOCKWAIT == ON) && \
1893
    ((CLOCK_SPEED == CPU_4MHZ_PLL_CLKP2_4MHZ) || \
1894
     (CLOCK_SPEED == CPU_8MHZ_CLKP2_8MHZ) || \
1895
     (CLOCK_SPEED == CPU_56MHZ_CLKP2_14MHZ))
1896
no_PLL_yet:
1897
          BBC  CKMR:6,no_PLL_yet       ; check PCM and wait for
1898
                                       ; PLL to stabilize
1899
#endif ; wait for PLL
1900
 
1901
;====================================================================
1902
; 6.13  Initialise Low-Level Library Interface
1903
;====================================================================
1904
;
1905
; Call lib init function and reload stack afterwards, if AUTOMODEL
1906
;====================================================================
1907
#if CLIBINIT == ON
1908
#  if MEMMODEL == SMALL || MEMMODEL == COMPACT
1909
          CALL __stream_init       ; initialise library IO
1910
#  else                            ; MEDIUM, LARGE, AUTOMODEL
1911
          CALLP __stream_init      ; initialise library IO
1912
#    if MEMMODEL == AUTOMODEL
1913
          RELOAD_SP                ; reload stack since stream_init was
1914
                                   ; possibly left by RET (not RETP)
1915
#    endif  ; AUTOMODEL
1916
#  endif  ; MEDIUM, LARGE, AUTOMODEL
1917
#endif  ; LIBINI
1918
 
1919
;====================================================================
1920
; 6.14  Call C-language main function
1921
;====================================================================
1922
#if MEMMODEL == SMALL || MEMMODEL == COMPACT
1923
          CALL _main               ; Start main function
1924
#else                              ; MEDIUM, LARGE, AUTOMODEL
1925
          CALLP _main              ; Start main function
1926
                                   ; ignore remaining word on stack,
1927
                                   ; if main was completed by RET
1928
#endif
1929
;====================================================================
1930
; 6.15  Shut down library
1931
;====================================================================
1932
#if CLIBINIT == ON
1933
#  if MEMMODEL == SMALL || MEMMODEL == COMPACT
1934
          CALL _exit
1935
#  else                            ; MEDIUM, LARGE, AUTOMODEL
1936
          CALLP _exit              ; ignore remaining word on stack,
1937
                                   ; if main was completed by RET
1938
#  endif
1939
__exit:
1940
#endif
1941
 
1942
;====================================================================
1943
; 6.16  Program end loop
1944
;====================================================================
1945
 
1946
end:      BRA  end                 ; Loop
1947
 
1948
          .END notresetyet         ; define debugger start address
1949
 
1950
 
1951
;====================================================================
1952
; ----------------------- End of Start-up file ---------------------
1953
;====================================================================

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