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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MCF5235_GCC/] [include/] [arch/] [mcf523x/] [mcf523x_intc1.h] - Blame information for rev 584

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Line No. Rev Author Line
1 584 jeremybenn
/*
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 * These files are taken from the MCF523X source code example package
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 * which is available on the Freescale website. Freescale explicitly
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 * grants the redistribution and modification of these source files.
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 * The complete licensing information is available in the file
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 * LICENSE_FREESCALE.TXT.
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 *
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 * File:        mcf523x_intc1.h
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 * Purpose:     Register and bit definitions for the MCF523X
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 *
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 * Notes:
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 *
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 */
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#ifndef __MCF523X_INTC1_H__
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#define __MCF523X_INTC1_H__
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/*********************************************************************
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*
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* Interrupt Controller 1 (INTC1)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_INTC1_IPRH         (*(vuint32*)(void*)(&__IPSBAR[0x000D00]))
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#define MCF_INTC1_IPRL         (*(vuint32*)(void*)(&__IPSBAR[0x000D04]))
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#define MCF_INTC1_IMRH         (*(vuint32*)(void*)(&__IPSBAR[0x000D08]))
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#define MCF_INTC1_IMRL         (*(vuint32*)(void*)(&__IPSBAR[0x000D0C]))
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#define MCF_INTC1_INTFRCH      (*(vuint32*)(void*)(&__IPSBAR[0x000D10]))
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#define MCF_INTC1_INTFRCL      (*(vuint32*)(void*)(&__IPSBAR[0x000D14]))
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#define MCF_INTC1_IRLR         (*(vuint8 *)(void*)(&__IPSBAR[0x000D18]))
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#define MCF_INTC1_IACKLPR      (*(vuint8 *)(void*)(&__IPSBAR[0x000D19]))
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#define MCF_INTC1_ICR0         (*(vuint8 *)(void*)(&__IPSBAR[0x000D40]))
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#define MCF_INTC1_ICR1         (*(vuint8 *)(void*)(&__IPSBAR[0x000D41]))
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#define MCF_INTC1_ICR2         (*(vuint8 *)(void*)(&__IPSBAR[0x000D42]))
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#define MCF_INTC1_ICR3         (*(vuint8 *)(void*)(&__IPSBAR[0x000D43]))
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#define MCF_INTC1_ICR4         (*(vuint8 *)(void*)(&__IPSBAR[0x000D44]))
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#define MCF_INTC1_ICR5         (*(vuint8 *)(void*)(&__IPSBAR[0x000D45]))
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#define MCF_INTC1_ICR6         (*(vuint8 *)(void*)(&__IPSBAR[0x000D46]))
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#define MCF_INTC1_ICR7         (*(vuint8 *)(void*)(&__IPSBAR[0x000D47]))
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#define MCF_INTC1_ICR8         (*(vuint8 *)(void*)(&__IPSBAR[0x000D48]))
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#define MCF_INTC1_ICR9         (*(vuint8 *)(void*)(&__IPSBAR[0x000D49]))
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#define MCF_INTC1_ICR10        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4A]))
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#define MCF_INTC1_ICR11        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4B]))
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#define MCF_INTC1_ICR12        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4C]))
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#define MCF_INTC1_ICR13        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4D]))
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#define MCF_INTC1_ICR14        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4E]))
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#define MCF_INTC1_ICR15        (*(vuint8 *)(void*)(&__IPSBAR[0x000D4F]))
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#define MCF_INTC1_ICR16        (*(vuint8 *)(void*)(&__IPSBAR[0x000D50]))
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#define MCF_INTC1_ICR17        (*(vuint8 *)(void*)(&__IPSBAR[0x000D51]))
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#define MCF_INTC1_ICR18        (*(vuint8 *)(void*)(&__IPSBAR[0x000D52]))
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#define MCF_INTC1_ICR19        (*(vuint8 *)(void*)(&__IPSBAR[0x000D53]))
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#define MCF_INTC1_ICR20        (*(vuint8 *)(void*)(&__IPSBAR[0x000D54]))
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#define MCF_INTC1_ICR21        (*(vuint8 *)(void*)(&__IPSBAR[0x000D55]))
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#define MCF_INTC1_ICR22        (*(vuint8 *)(void*)(&__IPSBAR[0x000D56]))
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#define MCF_INTC1_ICR23        (*(vuint8 *)(void*)(&__IPSBAR[0x000D57]))
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#define MCF_INTC1_ICR24        (*(vuint8 *)(void*)(&__IPSBAR[0x000D58]))
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#define MCF_INTC1_ICR25        (*(vuint8 *)(void*)(&__IPSBAR[0x000D59]))
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#define MCF_INTC1_ICR26        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5A]))
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#define MCF_INTC1_ICR27        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5B]))
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#define MCF_INTC1_ICR28        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5C]))
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#define MCF_INTC1_ICR29        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5D]))
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#define MCF_INTC1_ICR30        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5E]))
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#define MCF_INTC1_ICR31        (*(vuint8 *)(void*)(&__IPSBAR[0x000D5F]))
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#define MCF_INTC1_ICR32        (*(vuint8 *)(void*)(&__IPSBAR[0x000D60]))
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#define MCF_INTC1_ICR33        (*(vuint8 *)(void*)(&__IPSBAR[0x000D61]))
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#define MCF_INTC1_ICR34        (*(vuint8 *)(void*)(&__IPSBAR[0x000D62]))
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#define MCF_INTC1_ICR35        (*(vuint8 *)(void*)(&__IPSBAR[0x000D63]))
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#define MCF_INTC1_ICR36        (*(vuint8 *)(void*)(&__IPSBAR[0x000D64]))
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#define MCF_INTC1_ICR37        (*(vuint8 *)(void*)(&__IPSBAR[0x000D65]))
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#define MCF_INTC1_ICR38        (*(vuint8 *)(void*)(&__IPSBAR[0x000D66]))
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#define MCF_INTC1_ICR39        (*(vuint8 *)(void*)(&__IPSBAR[0x000D67]))
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#define MCF_INTC1_ICR40        (*(vuint8 *)(void*)(&__IPSBAR[0x000D68]))
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#define MCF_INTC1_ICR41        (*(vuint8 *)(void*)(&__IPSBAR[0x000D69]))
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#define MCF_INTC1_ICR42        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6A]))
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#define MCF_INTC1_ICR43        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6B]))
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#define MCF_INTC1_ICR44        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6C]))
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#define MCF_INTC1_ICR45        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6D]))
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#define MCF_INTC1_ICR46        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6E]))
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#define MCF_INTC1_ICR47        (*(vuint8 *)(void*)(&__IPSBAR[0x000D6F]))
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#define MCF_INTC1_ICR48        (*(vuint8 *)(void*)(&__IPSBAR[0x000D70]))
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#define MCF_INTC1_ICR49        (*(vuint8 *)(void*)(&__IPSBAR[0x000D71]))
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#define MCF_INTC1_ICR50        (*(vuint8 *)(void*)(&__IPSBAR[0x000D72]))
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#define MCF_INTC1_ICR51        (*(vuint8 *)(void*)(&__IPSBAR[0x000D73]))
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#define MCF_INTC1_ICR52        (*(vuint8 *)(void*)(&__IPSBAR[0x000D74]))
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#define MCF_INTC1_ICR53        (*(vuint8 *)(void*)(&__IPSBAR[0x000D75]))
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#define MCF_INTC1_ICR54        (*(vuint8 *)(void*)(&__IPSBAR[0x000D76]))
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#define MCF_INTC1_ICR55        (*(vuint8 *)(void*)(&__IPSBAR[0x000D77]))
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#define MCF_INTC1_ICR56        (*(vuint8 *)(void*)(&__IPSBAR[0x000D78]))
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#define MCF_INTC1_ICR57        (*(vuint8 *)(void*)(&__IPSBAR[0x000D79]))
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#define MCF_INTC1_ICR58        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7A]))
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#define MCF_INTC1_ICR59        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7B]))
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#define MCF_INTC1_ICR60        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7C]))
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#define MCF_INTC1_ICR61        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7D]))
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#define MCF_INTC1_ICR62        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7E]))
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#define MCF_INTC1_ICR63        (*(vuint8 *)(void*)(&__IPSBAR[0x000D7F]))
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#define MCF_INTC1_ICRn(x)      (*(vuint8 *)(void*)(&__IPSBAR[0x000D40+((x)*0x001)]))
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#define MCF_INTC1_SWIACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DE0]))
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#define MCF_INTC1_L1IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4]))
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#define MCF_INTC1_L2IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DE8]))
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#define MCF_INTC1_L3IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DEC]))
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#define MCF_INTC1_L4IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DF0]))
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#define MCF_INTC1_L5IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DF4]))
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#define MCF_INTC1_L6IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DF8]))
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#define MCF_INTC1_L7IACK       (*(vuint8 *)(void*)(&__IPSBAR[0x000DFC]))
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#define MCF_INTC1_LnIACK(x)    (*(vuint8 *)(void*)(&__IPSBAR[0x000DE4+((x)*0x004)]))
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/* Bit definitions and macros for MCF_INTC1_IPRH */
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#define MCF_INTC1_IPRH_INT32          (0x00000001)
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#define MCF_INTC1_IPRH_INT33          (0x00000002)
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#define MCF_INTC1_IPRH_INT34          (0x00000004)
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#define MCF_INTC1_IPRH_INT35          (0x00000008)
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#define MCF_INTC1_IPRH_INT36          (0x00000010)
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#define MCF_INTC1_IPRH_INT37          (0x00000020)
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#define MCF_INTC1_IPRH_INT38          (0x00000040)
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#define MCF_INTC1_IPRH_INT39          (0x00000080)
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#define MCF_INTC1_IPRH_INT40          (0x00000100)
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#define MCF_INTC1_IPRH_INT41          (0x00000200)
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#define MCF_INTC1_IPRH_INT42          (0x00000400)
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#define MCF_INTC1_IPRH_INT43          (0x00000800)
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#define MCF_INTC1_IPRH_INT44          (0x00001000)
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#define MCF_INTC1_IPRH_INT45          (0x00002000)
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#define MCF_INTC1_IPRH_INT46          (0x00004000)
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#define MCF_INTC1_IPRH_INT47          (0x00008000)
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#define MCF_INTC1_IPRH_INT48          (0x00010000)
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#define MCF_INTC1_IPRH_INT49          (0x00020000)
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#define MCF_INTC1_IPRH_INT50          (0x00040000)
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#define MCF_INTC1_IPRH_INT51          (0x00080000)
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#define MCF_INTC1_IPRH_INT52          (0x00100000)
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#define MCF_INTC1_IPRH_INT53          (0x00200000)
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#define MCF_INTC1_IPRH_INT54          (0x00400000)
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#define MCF_INTC1_IPRH_INT55          (0x00800000)
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#define MCF_INTC1_IPRH_INT56          (0x01000000)
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#define MCF_INTC1_IPRH_INT57          (0x02000000)
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#define MCF_INTC1_IPRH_INT58          (0x04000000)
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#define MCF_INTC1_IPRH_INT59          (0x08000000)
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#define MCF_INTC1_IPRH_INT60          (0x10000000)
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#define MCF_INTC1_IPRH_INT61          (0x20000000)
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#define MCF_INTC1_IPRH_INT62          (0x40000000)
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#define MCF_INTC1_IPRH_INT63          (0x80000000)
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/* Bit definitions and macros for MCF_INTC1_IPRL */
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#define MCF_INTC1_IPRL_INT1           (0x00000002)
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#define MCF_INTC1_IPRL_INT2           (0x00000004)
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#define MCF_INTC1_IPRL_INT3           (0x00000008)
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#define MCF_INTC1_IPRL_INT4           (0x00000010)
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#define MCF_INTC1_IPRL_INT5           (0x00000020)
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#define MCF_INTC1_IPRL_INT6           (0x00000040)
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#define MCF_INTC1_IPRL_INT7           (0x00000080)
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#define MCF_INTC1_IPRL_INT8           (0x00000100)
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#define MCF_INTC1_IPRL_INT9           (0x00000200)
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#define MCF_INTC1_IPRL_INT10          (0x00000400)
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#define MCF_INTC1_IPRL_INT11          (0x00000800)
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#define MCF_INTC1_IPRL_INT12          (0x00001000)
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#define MCF_INTC1_IPRL_INT13          (0x00002000)
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#define MCF_INTC1_IPRL_INT14          (0x00004000)
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#define MCF_INTC1_IPRL_INT15          (0x00008000)
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#define MCF_INTC1_IPRL_INT16          (0x00010000)
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#define MCF_INTC1_IPRL_INT17          (0x00020000)
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#define MCF_INTC1_IPRL_INT18          (0x00040000)
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#define MCF_INTC1_IPRL_INT19          (0x00080000)
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#define MCF_INTC1_IPRL_INT20          (0x00100000)
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#define MCF_INTC1_IPRL_INT21          (0x00200000)
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#define MCF_INTC1_IPRL_INT22          (0x00400000)
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#define MCF_INTC1_IPRL_INT23          (0x00800000)
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#define MCF_INTC1_IPRL_INT24          (0x01000000)
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#define MCF_INTC1_IPRL_INT25          (0x02000000)
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#define MCF_INTC1_IPRL_INT26          (0x04000000)
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#define MCF_INTC1_IPRL_INT27          (0x08000000)
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#define MCF_INTC1_IPRL_INT28          (0x10000000)
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#define MCF_INTC1_IPRL_INT29          (0x20000000)
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#define MCF_INTC1_IPRL_INT30          (0x40000000)
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#define MCF_INTC1_IPRL_INT31          (0x80000000)
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/* Bit definitions and macros for MCF_INTC1_IMRH */
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#define MCF_INTC1_IMRH_INT_MASK32     (0x00000001)
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#define MCF_INTC1_IMRH_INT_MASK33     (0x00000002)
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#define MCF_INTC1_IMRH_INT_MASK34     (0x00000004)
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#define MCF_INTC1_IMRH_INT_MASK35     (0x00000008)
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#define MCF_INTC1_IMRH_INT_MASK36     (0x00000010)
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#define MCF_INTC1_IMRH_INT_MASK37     (0x00000020)
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#define MCF_INTC1_IMRH_INT_MASK38     (0x00000040)
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#define MCF_INTC1_IMRH_INT_MASK39     (0x00000080)
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#define MCF_INTC1_IMRH_INT_MASK40     (0x00000100)
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#define MCF_INTC1_IMRH_INT_MASK41     (0x00000200)
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#define MCF_INTC1_IMRH_INT_MASK42     (0x00000400)
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#define MCF_INTC1_IMRH_INT_MASK43     (0x00000800)
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#define MCF_INTC1_IMRH_INT_MASK44     (0x00001000)
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#define MCF_INTC1_IMRH_INT_MASK45     (0x00002000)
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#define MCF_INTC1_IMRH_INT_MASK46     (0x00004000)
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#define MCF_INTC1_IMRH_INT_MASK47     (0x00008000)
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#define MCF_INTC1_IMRH_INT_MASK48     (0x00010000)
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#define MCF_INTC1_IMRH_INT_MASK49     (0x00020000)
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#define MCF_INTC1_IMRH_INT_MASK50     (0x00040000)
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#define MCF_INTC1_IMRH_INT_MASK51     (0x00080000)
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#define MCF_INTC1_IMRH_INT_MASK52     (0x00100000)
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#define MCF_INTC1_IMRH_INT_MASK53     (0x00200000)
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#define MCF_INTC1_IMRH_INT_MASK54     (0x00400000)
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#define MCF_INTC1_IMRH_INT_MASK55     (0x00800000)
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#define MCF_INTC1_IMRH_INT_MASK56     (0x01000000)
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#define MCF_INTC1_IMRH_INT_MASK57     (0x02000000)
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#define MCF_INTC1_IMRH_INT_MASK58     (0x04000000)
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#define MCF_INTC1_IMRH_INT_MASK59     (0x08000000)
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#define MCF_INTC1_IMRH_INT_MASK60     (0x10000000)
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#define MCF_INTC1_IMRH_INT_MASK61     (0x20000000)
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#define MCF_INTC1_IMRH_INT_MASK62     (0x40000000)
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#define MCF_INTC1_IMRH_INT_MASK63     (0x80000000)
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/* Bit definitions and macros for MCF_INTC1_IMRL */
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#define MCF_INTC1_IMRL_MASKALL        (0x00000001)
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#define MCF_INTC1_IMRL_INT_MASK1      (0x00000002)
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#define MCF_INTC1_IMRL_INT_MASK2      (0x00000004)
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#define MCF_INTC1_IMRL_INT_MASK3      (0x00000008)
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#define MCF_INTC1_IMRL_INT_MASK4      (0x00000010)
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#define MCF_INTC1_IMRL_INT_MASK5      (0x00000020)
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#define MCF_INTC1_IMRL_INT_MASK6      (0x00000040)
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#define MCF_INTC1_IMRL_INT_MASK7      (0x00000080)
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#define MCF_INTC1_IMRL_INT_MASK8      (0x00000100)
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#define MCF_INTC1_IMRL_INT_MASK9      (0x00000200)
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#define MCF_INTC1_IMRL_INT_MASK10     (0x00000400)
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#define MCF_INTC1_IMRL_INT_MASK11     (0x00000800)
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#define MCF_INTC1_IMRL_INT_MASK12     (0x00001000)
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#define MCF_INTC1_IMRL_INT_MASK13     (0x00002000)
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#define MCF_INTC1_IMRL_INT_MASK14     (0x00004000)
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#define MCF_INTC1_IMRL_INT_MASK15     (0x00008000)
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#define MCF_INTC1_IMRL_INT_MASK16     (0x00010000)
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#define MCF_INTC1_IMRL_INT_MASK17     (0x00020000)
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#define MCF_INTC1_IMRL_INT_MASK18     (0x00040000)
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#define MCF_INTC1_IMRL_INT_MASK19     (0x00080000)
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#define MCF_INTC1_IMRL_INT_MASK20     (0x00100000)
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#define MCF_INTC1_IMRL_INT_MASK21     (0x00200000)
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#define MCF_INTC1_IMRL_INT_MASK22     (0x00400000)
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#define MCF_INTC1_IMRL_INT_MASK23     (0x00800000)
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#define MCF_INTC1_IMRL_INT_MASK24     (0x01000000)
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#define MCF_INTC1_IMRL_INT_MASK25     (0x02000000)
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#define MCF_INTC1_IMRL_INT_MASK26     (0x04000000)
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#define MCF_INTC1_IMRL_INT_MASK27     (0x08000000)
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#define MCF_INTC1_IMRL_INT_MASK28     (0x10000000)
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#define MCF_INTC1_IMRL_INT_MASK29     (0x20000000)
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#define MCF_INTC1_IMRL_INT_MASK30     (0x40000000)
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#define MCF_INTC1_IMRL_INT_MASK31     (0x80000000)
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/* Bit definitions and macros for MCF_INTC1_INTFRCH */
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#define MCF_INTC1_INTFRCH_INTFRC32    (0x00000001)
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#define MCF_INTC1_INTFRCH_INTFRC33    (0x00000002)
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#define MCF_INTC1_INTFRCH_INTFRC34    (0x00000004)
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#define MCF_INTC1_INTFRCH_INTFRC35    (0x00000008)
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#define MCF_INTC1_INTFRCH_INTFRC36    (0x00000010)
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#define MCF_INTC1_INTFRCH_INTFRC37    (0x00000020)
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#define MCF_INTC1_INTFRCH_INTFRC38    (0x00000040)
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#define MCF_INTC1_INTFRCH_INTFRC39    (0x00000080)
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#define MCF_INTC1_INTFRCH_INTFRC40    (0x00000100)
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#define MCF_INTC1_INTFRCH_INTFRC41    (0x00000200)
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#define MCF_INTC1_INTFRCH_INTFRC42    (0x00000400)
255
#define MCF_INTC1_INTFRCH_INTFRC43    (0x00000800)
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#define MCF_INTC1_INTFRCH_INTFRC44    (0x00001000)
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#define MCF_INTC1_INTFRCH_INTFRC45    (0x00002000)
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#define MCF_INTC1_INTFRCH_INTFRC46    (0x00004000)
259
#define MCF_INTC1_INTFRCH_INTFRC47    (0x00008000)
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#define MCF_INTC1_INTFRCH_INTFRC48    (0x00010000)
261
#define MCF_INTC1_INTFRCH_INTFRC49    (0x00020000)
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#define MCF_INTC1_INTFRCH_INTFRC50    (0x00040000)
263
#define MCF_INTC1_INTFRCH_INTFRC51    (0x00080000)
264
#define MCF_INTC1_INTFRCH_INTFRC52    (0x00100000)
265
#define MCF_INTC1_INTFRCH_INTFRC53    (0x00200000)
266
#define MCF_INTC1_INTFRCH_INTFRC54    (0x00400000)
267
#define MCF_INTC1_INTFRCH_INTFRC55    (0x00800000)
268
#define MCF_INTC1_INTFRCH_INTFRC56    (0x01000000)
269
#define MCF_INTC1_INTFRCH_INTFRC57    (0x02000000)
270
#define MCF_INTC1_INTFRCH_INTFRC58    (0x04000000)
271
#define MCF_INTC1_INTFRCH_INTFRC59    (0x08000000)
272
#define MCF_INTC1_INTFRCH_INTFRC60    (0x10000000)
273
#define MCF_INTC1_INTFRCH_INTFRC61    (0x20000000)
274
#define MCF_INTC1_INTFRCH_INTFRC62    (0x40000000)
275
#define MCF_INTC1_INTFRCH_INTFRC63    (0x80000000)
276
 
277
/* Bit definitions and macros for MCF_INTC1_INTFRCL */
278
#define MCF_INTC1_INTFRCL_INTFRC1     (0x00000002)
279
#define MCF_INTC1_INTFRCL_INTFRC2     (0x00000004)
280
#define MCF_INTC1_INTFRCL_INTFRC3     (0x00000008)
281
#define MCF_INTC1_INTFRCL_INTFRC4     (0x00000010)
282
#define MCF_INTC1_INTFRCL_INTFRC5     (0x00000020)
283
#define MCF_INTC1_INTFRCL_INT6        (0x00000040)
284
#define MCF_INTC1_INTFRCL_INT7        (0x00000080)
285
#define MCF_INTC1_INTFRCL_INT8        (0x00000100)
286
#define MCF_INTC1_INTFRCL_INT9        (0x00000200)
287
#define MCF_INTC1_INTFRCL_INT10       (0x00000400)
288
#define MCF_INTC1_INTFRCL_INTFRC11    (0x00000800)
289
#define MCF_INTC1_INTFRCL_INTFRC12    (0x00001000)
290
#define MCF_INTC1_INTFRCL_INTFRC13    (0x00002000)
291
#define MCF_INTC1_INTFRCL_INTFRC14    (0x00004000)
292
#define MCF_INTC1_INTFRCL_INT15       (0x00008000)
293
#define MCF_INTC1_INTFRCL_INTFRC16    (0x00010000)
294
#define MCF_INTC1_INTFRCL_INTFRC17    (0x00020000)
295
#define MCF_INTC1_INTFRCL_INTFRC18    (0x00040000)
296
#define MCF_INTC1_INTFRCL_INTFRC19    (0x00080000)
297
#define MCF_INTC1_INTFRCL_INTFRC20    (0x00100000)
298
#define MCF_INTC1_INTFRCL_INTFRC21    (0x00200000)
299
#define MCF_INTC1_INTFRCL_INTFRC22    (0x00400000)
300
#define MCF_INTC1_INTFRCL_INTFRC23    (0x00800000)
301
#define MCF_INTC1_INTFRCL_INTFRC24    (0x01000000)
302
#define MCF_INTC1_INTFRCL_INTFRC25    (0x02000000)
303
#define MCF_INTC1_INTFRCL_INTFRC26    (0x04000000)
304
#define MCF_INTC1_INTFRCL_INTFRC27    (0x08000000)
305
#define MCF_INTC1_INTFRCL_INTFRC28    (0x10000000)
306
#define MCF_INTC1_INTFRCL_INTFRC29    (0x20000000)
307
#define MCF_INTC1_INTFRCL_INTFRC30    (0x40000000)
308
#define MCF_INTC1_INTFRCL_INTFRC31    (0x80000000)
309
 
310
/* Bit definitions and macros for MCF_INTC1_IRLR */
311
#define MCF_INTC1_IRLR_IRQ(x)         (((x)&0x7F)<<1)
312
 
313
/* Bit definitions and macros for MCF_INTC1_IACKLPR */
314
#define MCF_INTC1_IACKLPR_PRI(x)      (((x)&0x0F)<<0)
315
#define MCF_INTC1_IACKLPR_LEVEL(x)    (((x)&0x07)<<4)
316
 
317
/* Bit definitions and macros for MCF_INTC1_ICRn */
318
#define MCF_INTC1_ICRn_IP(x)          (((x)&0x07)<<0)
319
#define MCF_INTC1_ICRn_IL(x)          (((x)&0x07)<<3)
320
 
321
/********************************************************************/
322
 
323
#endif /* __MCF523X_INTC1_H__ */

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