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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MCF5235_GCC/] [include/] [arch/] [mcf523x/] [mcf523x_qspi.h] - Blame information for rev 584

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1 584 jeremybenn
/*
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 * These files are taken from the MCF523X source code example package
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 * which is available on the Freescale website. Freescale explicitly
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 * grants the redistribution and modification of these source files.
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 * The complete licensing information is available in the file
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 * LICENSE_FREESCALE.TXT.
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 *
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 * File:        mcf523x_qspi.h
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 * Purpose:     Register and bit definitions for the MCF523X
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 *
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 * Notes:
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 *
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 */
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#ifndef __MCF523X_QSPI_H__
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#define __MCF523X_QSPI_H__
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/*********************************************************************
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*
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* Queued Serial Peripheral Interface (QSPI)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_QSPI_QMR      (*(vuint16*)(void*)(&__IPSBAR[0x000340]))
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#define MCF_QSPI_QDLYR    (*(vuint16*)(void*)(&__IPSBAR[0x000344]))
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#define MCF_QSPI_QWR      (*(vuint16*)(void*)(&__IPSBAR[0x000348]))
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#define MCF_QSPI_QIR      (*(vuint16*)(void*)(&__IPSBAR[0x00034C]))
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#define MCF_QSPI_QAR      (*(vuint16*)(void*)(&__IPSBAR[0x000350]))
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#define MCF_QSPI_QDR      (*(vuint16*)(void*)(&__IPSBAR[0x000354]))
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/* Bit definitions and macros for MCF_QSPI_QMR */
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#define MCF_QSPI_QMR_BAUD(x)     (((x)&0x00FF)<<0)
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#define MCF_QSPI_QMR_CPHA        (0x0100)
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#define MCF_QSPI_QMR_CPOL        (0x0200)
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#define MCF_QSPI_QMR_BITS(x)     (((x)&0x000F)<<10)
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#define MCF_QSPI_QMR_DOHIE       (0x4000)
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#define MCF_QSPI_QMR_MSTR        (0x8000)
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/* Bit definitions and macros for MCF_QSPI_QDLYR */
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#define MCF_QSPI_QDLYR_DTL(x)    (((x)&0x00FF)<<0)
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#define MCF_QSPI_QDLYR_QCD(x)    (((x)&0x007F)<<8)
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#define MCF_QSPI_QDLYR_SPE       (0x8000)
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/* Bit definitions and macros for MCF_QSPI_QWR */
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#define MCF_QSPI_QWR_NEWQP(x)    (((x)&0x000F)<<0)
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#define MCF_QSPI_QWR_ENDQP(x)    (((x)&0x000F)<<8)
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#define MCF_QSPI_QWR_CSIV        (0x1000)
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#define MCF_QSPI_QWR_WRTO        (0x2000)
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#define MCF_QSPI_QWR_WREN        (0x4000)
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#define MCF_QSPI_QWR_HALT        (0x8000)
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/* Bit definitions and macros for MCF_QSPI_QIR */
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#define MCF_QSPI_QIR_SPIF        (0x0001)
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#define MCF_QSPI_QIR_ABRT        (0x0004)
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#define MCF_QSPI_QIR_WCEF        (0x0008)
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#define MCF_QSPI_QIR_SPIFE       (0x0100)
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#define MCF_QSPI_QIR_ABRTE       (0x0400)
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#define MCF_QSPI_QIR_WCEFE       (0x0800)
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#define MCF_QSPI_QIR_ABRTL       (0x1000)
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#define MCF_QSPI_QIR_ABRTB       (0x4000)
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#define MCF_QSPI_QIR_WCEFB       (0x8000)
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/* Bit definitions and macros for MCF_QSPI_QAR */
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#define MCF_QSPI_QAR_ADDR(x)     (((x)&0x003F)<<0)
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/********************************************************************/
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#endif /* __MCF523X_QSPI_H__ */

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