OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MCF5235_GCC/] [include/] [arch/] [mcf523x/] [mcf523x_scm.h] - Blame information for rev 584

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 584 jeremybenn
/*
2
 * These files are taken from the MCF523X source code example package
3
 * which is available on the Freescale website. Freescale explicitly
4
 * grants the redistribution and modification of these source files.
5
 * The complete licensing information is available in the file
6
 * LICENSE_FREESCALE.TXT.
7
 *
8
 * File:        mcf523x_scm.h
9
 * Purpose:     Register and bit definitions for the MCF523X
10
 *
11
 * Notes:
12
 *
13
 */
14
 
15
#ifndef __MCF523X_SCM_H__
16
#define __MCF523X_SCM_H__
17
 
18
/*********************************************************************
19
*
20
* System Control Module (SCM)
21
*
22
*********************************************************************/
23
 
24
/* Register read/write macros */
25
#define MCF_SCM_IPSBAR     (*(vuint32*)(void*)(&__IPSBAR[0x000000]))
26
#define MCF_SCM_RAMBAR     (*(vuint32*)(void*)(&__IPSBAR[0x000008]))
27
#define MCF_SCM_CRSR       (*(vuint8 *)(void*)(&__IPSBAR[0x000010]))
28
#define MCF_SCM_CWCR       (*(vuint8 *)(void*)(&__IPSBAR[0x000011]))
29
#define MCF_SCM_LPICR      (*(vuint8 *)(void*)(&__IPSBAR[0x000012]))
30
#define MCF_SCM_CWSR       (*(vuint8 *)(void*)(&__IPSBAR[0x000013]))
31
#define MCF_SCM_DMAREQC    (*(vuint32*)(void*)(&__IPSBAR[0x000014]))
32
#define MCF_SCM_MPARK      (*(vuint32*)(void*)(&__IPSBAR[0x00001C]))
33
#define MCF_SCM_MPR        (*(vuint8 *)(void*)(&__IPSBAR[0x000020]))
34
#define MCF_SCM_PACR0      (*(vuint8 *)(void*)(&__IPSBAR[0x000024]))
35
#define MCF_SCM_PACR1      (*(vuint8 *)(void*)(&__IPSBAR[0x000025]))
36
#define MCF_SCM_PACR2      (*(vuint8 *)(void*)(&__IPSBAR[0x000026]))
37
#define MCF_SCM_PACR3      (*(vuint8 *)(void*)(&__IPSBAR[0x000027]))
38
#define MCF_SCM_PACR4      (*(vuint8 *)(void*)(&__IPSBAR[0x000028]))
39
#define MCF_SCM_PACR5      (*(vuint8 *)(void*)(&__IPSBAR[0x00002A]))
40
#define MCF_SCM_PACR6      (*(vuint8 *)(void*)(&__IPSBAR[0x00002B]))
41
#define MCF_SCM_PACR7      (*(vuint8 *)(void*)(&__IPSBAR[0x00002C]))
42
#define MCF_SCM_PACR8      (*(vuint8 *)(void*)(&__IPSBAR[0x00002E]))
43
#define MCF_SCM_GPACR0     (*(vuint8 *)(void*)(&__IPSBAR[0x000030]))
44
 
45
/* Bit definitions and macros for MCF_SCM_IPSBAR */
46
#define MCF_SCM_IPSBAR_V                 (0x00000001)
47
#define MCF_SCM_IPSBAR_BA(x)             (((x)&0x00000003)<<30)
48
 
49
/* Bit definitions and macros for MCF_SCM_RAMBAR */
50
#define MCF_SCM_RAMBAR_BDE               (0x00000200)
51
#define MCF_SCM_RAMBAR_BA(x)             (((x)&0x0000FFFF)<<16)
52
 
53
/* Bit definitions and macros for MCF_SCM_CRSR */
54
#define MCF_SCM_CRSR_CWDR                (0x20)
55
#define MCF_SCM_CRSR_EXT                 (0x80)
56
 
57
/* Bit definitions and macros for MCF_SCM_CWCR */
58
#define MCF_SCM_CWCR_CWTIC               (0x01)
59
#define MCF_SCM_CWCR_CWTAVAL             (0x02)
60
#define MCF_SCM_CWCR_CWTA                (0x04)
61
#define MCF_SCM_CWCR_CWT(x)              (((x)&0x07)<<3)
62
#define MCF_SCM_CWCR_CWRI                (0x40)
63
#define MCF_SCM_CWCR_CWE                 (0x80)
64
 
65
/* Bit definitions and macros for MCF_SCM_LPICR */
66
#define MCF_SCM_LPICR_XLPM_IPL(x)        (((x)&0x07)<<4)
67
#define MCF_SCM_LPICR_ENBSTOP            (0x80)
68
 
69
/* Bit definitions and macros for MCF_SCM_DMAREQC */
70
#define MCF_SCM_DMAREQC_DMAC0(x)         (((x)&0x0000000F)<<0)
71
#define MCF_SCM_DMAREQC_DMAC1(x)         (((x)&0x0000000F)<<4)
72
#define MCF_SCM_DMAREQC_DMAC2(x)         (((x)&0x0000000F)<<8)
73
#define MCF_SCM_DMAREQC_DMAC3(x)         (((x)&0x0000000F)<<12)
74
 
75
/* Bit definitions and macros for MCF_SCM_MPARK */
76
#define MCF_SCM_MPARK_LCKOUT_TIME(x)     (((x)&0x0000000F)<<8)
77
#define MCF_SCM_MPARK_PRKLAST            (0x00001000)
78
#define MCF_SCM_MPARK_TIMEOUT            (0x00002000)
79
#define MCF_SCM_MPARK_FIXED              (0x00004000)
80
#define MCF_SCM_MPARK_M1_PRTY(x)         (((x)&0x00000003)<<16)
81
#define MCF_SCM_MPARK_M0_PRTY(x)         (((x)&0x00000003)<<18)
82
#define MCF_SCM_MPARK_M2_PRTY(x)         (((x)&0x00000003)<<20)
83
#define MCF_SCM_MPARK_M3_PRTY(x)         (((x)&0x00000003)<<22)
84
#define MCF_SCM_MPARK_BCR24BIT           (0x01000000)
85
#define MCF_SCM_MPARK_M2_P_EN            (0x02000000)
86
 
87
/* Bit definitions and macros for MCF_SCM_MPR */
88
#define MCF_SCM_MPR_MPR(x)               (((x)&0x0F)<<0)
89
 
90
/* Bit definitions and macros for MCF_SCM_PACR0 */
91
#define MCF_SCM_PACR0_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
92
#define MCF_SCM_PACR0_LOCK0              (0x08)
93
#define MCF_SCM_PACR0_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
94
#define MCF_SCM_PACR0_LOCK1              (0x80)
95
 
96
/* Bit definitions and macros for MCF_SCM_PACR1 */
97
#define MCF_SCM_PACR1_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
98
#define MCF_SCM_PACR1_LOCK0              (0x08)
99
#define MCF_SCM_PACR1_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
100
#define MCF_SCM_PACR1_LOCK1              (0x80)
101
 
102
/* Bit definitions and macros for MCF_SCM_PACR2 */
103
#define MCF_SCM_PACR2_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
104
#define MCF_SCM_PACR2_LOCK0              (0x08)
105
#define MCF_SCM_PACR2_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
106
#define MCF_SCM_PACR2_LOCK1              (0x80)
107
 
108
/* Bit definitions and macros for MCF_SCM_PACR3 */
109
#define MCF_SCM_PACR3_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
110
#define MCF_SCM_PACR3_LOCK0              (0x08)
111
#define MCF_SCM_PACR3_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
112
#define MCF_SCM_PACR3_LOCK1              (0x80)
113
 
114
/* Bit definitions and macros for MCF_SCM_PACR4 */
115
#define MCF_SCM_PACR4_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
116
#define MCF_SCM_PACR4_LOCK0              (0x08)
117
#define MCF_SCM_PACR4_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
118
#define MCF_SCM_PACR4_LOCK1              (0x80)
119
 
120
/* Bit definitions and macros for MCF_SCM_PACR5 */
121
#define MCF_SCM_PACR5_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
122
#define MCF_SCM_PACR5_LOCK0              (0x08)
123
#define MCF_SCM_PACR5_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
124
#define MCF_SCM_PACR5_LOCK1              (0x80)
125
 
126
/* Bit definitions and macros for MCF_SCM_PACR6 */
127
#define MCF_SCM_PACR6_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
128
#define MCF_SCM_PACR6_LOCK0              (0x08)
129
#define MCF_SCM_PACR6_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
130
#define MCF_SCM_PACR6_LOCK1              (0x80)
131
 
132
/* Bit definitions and macros for MCF_SCM_PACR7 */
133
#define MCF_SCM_PACR7_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
134
#define MCF_SCM_PACR7_LOCK0              (0x08)
135
#define MCF_SCM_PACR7_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
136
#define MCF_SCM_PACR7_LOCK1              (0x80)
137
 
138
/* Bit definitions and macros for MCF_SCM_PACR8 */
139
#define MCF_SCM_PACR8_ACCESS_CTRL0(x)    (((x)&0x07)<<0)
140
#define MCF_SCM_PACR8_LOCK0              (0x08)
141
#define MCF_SCM_PACR8_ACCESS_CTRL1(x)    (((x)&0x07)<<4)
142
#define MCF_SCM_PACR8_LOCK1              (0x80)
143
 
144
/* Bit definitions and macros for MCF_SCM_GPACR0 */
145
#define MCF_SCM_GPACR0_ACCESS_CTRL(x)    (((x)&0x0F)<<0)
146
#define MCF_SCM_GPACR0_LOCK              (0x80)
147
 
148
/********************************************************************/
149
 
150
#endif /* __MCF523X_SCM_H__ */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.