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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MCF5235_GCC/] [include/] [arch/] [mcf523x/] [mcf523x_timer.h] - Blame information for rev 584

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Line No. Rev Author Line
1 584 jeremybenn
/*
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 * These files are taken from the MCF523X source code example package
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 * which is available on the Freescale website. Freescale explicitly
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 * grants the redistribution and modification of these source files.
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 * The complete licensing information is available in the file
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 * LICENSE_FREESCALE.TXT.
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 *
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 * File:        mcf523x_timer.h
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 * Purpose:     Register and bit definitions for the MCF523X
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 *
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 * Notes:
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 *
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 */
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#ifndef __MCF523X_TIMER_H__
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#define __MCF523X_TIMER_H__
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/*********************************************************************
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*
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* DMA Timers (TIMER)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_TIMER_DTMR0       (*(vuint16*)(void*)(&__IPSBAR[0x000400]))
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#define MCF_TIMER_DTXMR0      (*(vuint8 *)(void*)(&__IPSBAR[0x000402]))
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#define MCF_TIMER_DTER0       (*(vuint8 *)(void*)(&__IPSBAR[0x000403]))
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#define MCF_TIMER_DTRR0       (*(vuint32*)(void*)(&__IPSBAR[0x000404]))
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#define MCF_TIMER_DTCR0       (*(vuint32*)(void*)(&__IPSBAR[0x000408]))
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#define MCF_TIMER_DTCN0       (*(vuint32*)(void*)(&__IPSBAR[0x00040C]))
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#define MCF_TIMER_DTMR1       (*(vuint16*)(void*)(&__IPSBAR[0x000440]))
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#define MCF_TIMER_DTXMR1      (*(vuint8 *)(void*)(&__IPSBAR[0x000442]))
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#define MCF_TIMER_DTER1       (*(vuint8 *)(void*)(&__IPSBAR[0x000443]))
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#define MCF_TIMER_DTRR1       (*(vuint32*)(void*)(&__IPSBAR[0x000444]))
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#define MCF_TIMER_DTCR1       (*(vuint32*)(void*)(&__IPSBAR[0x000448]))
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#define MCF_TIMER_DTCN1       (*(vuint32*)(void*)(&__IPSBAR[0x00044C]))
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#define MCF_TIMER_DTMR2       (*(vuint16*)(void*)(&__IPSBAR[0x000480]))
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#define MCF_TIMER_DTXMR2      (*(vuint8 *)(void*)(&__IPSBAR[0x000482]))
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#define MCF_TIMER_DTER2       (*(vuint8 *)(void*)(&__IPSBAR[0x000483]))
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#define MCF_TIMER_DTRR2       (*(vuint32*)(void*)(&__IPSBAR[0x000484]))
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#define MCF_TIMER_DTCR2       (*(vuint32*)(void*)(&__IPSBAR[0x000488]))
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#define MCF_TIMER_DTCN2       (*(vuint32*)(void*)(&__IPSBAR[0x00048C]))
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#define MCF_TIMER_DTMR3       (*(vuint16*)(void*)(&__IPSBAR[0x0004C0]))
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#define MCF_TIMER_DTXMR3      (*(vuint8 *)(void*)(&__IPSBAR[0x0004C2]))
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#define MCF_TIMER_DTER3       (*(vuint8 *)(void*)(&__IPSBAR[0x0004C3]))
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#define MCF_TIMER_DTRR3       (*(vuint32*)(void*)(&__IPSBAR[0x0004C4]))
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#define MCF_TIMER_DTCR3       (*(vuint32*)(void*)(&__IPSBAR[0x0004C8]))
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#define MCF_TIMER_DTCN3       (*(vuint32*)(void*)(&__IPSBAR[0x0004CC]))
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#define MCF_TIMER_DTMR(x)     (*(vuint16*)(void*)(&__IPSBAR[0x000400+((x)*0x040)]))
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#define MCF_TIMER_DTXMR(x)    (*(vuint8 *)(void*)(&__IPSBAR[0x000402+((x)*0x040)]))
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#define MCF_TIMER_DTER(x)     (*(vuint8 *)(void*)(&__IPSBAR[0x000403+((x)*0x040)]))
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#define MCF_TIMER_DTRR(x)     (*(vuint32*)(void*)(&__IPSBAR[0x000404+((x)*0x040)]))
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#define MCF_TIMER_DTCR(x)     (*(vuint32*)(void*)(&__IPSBAR[0x000408+((x)*0x040)]))
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#define MCF_TIMER_DTCN(x)     (*(vuint32*)(void*)(&__IPSBAR[0x00040C+((x)*0x040)]))
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/* Bit definitions and macros for MCF_TIMER_DTMR */
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#define MCF_TIMER_DTMR_RST          (0x0001)
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#define MCF_TIMER_DTMR_CLK(x)       (((x)&0x0003)<<1)
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#define MCF_TIMER_DTMR_FRR          (0x0008)
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#define MCF_TIMER_DTMR_ORRI         (0x0010)
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#define MCF_TIMER_DTMR_OM           (0x0020)
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#define MCF_TIMER_DTMR_CE(x)        (((x)&0x0003)<<6)
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#define MCF_TIMER_DTMR_PS(x)        (((x)&0x00FF)<<8)
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#define MCF_TIMER_DTMR_CE_ANY       (0x00C0)
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#define MCF_TIMER_DTMR_CE_FALL      (0x0080)
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#define MCF_TIMER_DTMR_CE_RISE      (0x0040)
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#define MCF_TIMER_DTMR_CE_NONE      (0x0000)
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#define MCF_TIMER_DTMR_CLK_DTIN     (0x0006)
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#define MCF_TIMER_DTMR_CLK_DIV16    (0x0004)
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#define MCF_TIMER_DTMR_CLK_DIV1     (0x0002)
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#define MCF_TIMER_DTMR_CLK_STOP     (0x0000)
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/* Bit definitions and macros for MCF_TIMER_DTXMR */
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#define MCF_TIMER_DTXMR_MODE16      (0x01)
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#define MCF_TIMER_DTXMR_DMAEN       (0x80)
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/* Bit definitions and macros for MCF_TIMER_DTER */
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#define MCF_TIMER_DTER_CAP          (0x01)
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#define MCF_TIMER_DTER_REF          (0x02)
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/********************************************************************/
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#endif /* __MCF523X_TIMER_H__ */

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