OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MCF5235_GCC/] [m5235-rom.ld] - Blame information for rev 867

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 584 jeremybenn
STARTUP(system/crt0.o)
2
INPUT(system/vector.o)
3
OUTPUT_ARCH(m68k)
4
SEARCH_DIR(.)
5
GROUP(-lc -lgcc)
6
 
7
__DYNAMIC  =  0;
8
 
9
MEMORY
10
{
11
  sdram  (rwx) : ORIGIN = 0x00000000, LENGTH = 0x01000000
12
  sram   (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000
13
  ipsbar (rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000
14
  flash  (rwx) : ORIGIN = 0x80000000, LENGTH = 0x00080000
15
}
16
 
17
PROVIDE (__stack = 0x2000FFFC);
18
 
19
SECTIONS
20
{
21
  .sdram      : {} > sdram
22
  .ipsbar     : {} > ipsbar
23
  .sram (NOLOAD) : { *(.vector_ram); *(.nbuf) } > sram
24
  .flash      : {} > flash
25
 
26
  .text :
27
  {
28
    __text_start = . ;
29
    *(.vector_rom)
30
    . = ALIGN (0x100);
31
    *(.text)
32
    . = ALIGN (16);
33
 
34
    *(.eh_frame)
35
    . = ALIGN (16);
36
 
37
    *(.gnu.linkonce.t.*)
38
 
39
    . = ALIGN(0x4);
40
     __CTOR_LIST__ = .;
41
    ___CTOR_LIST__ = .;
42
    LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
43
    *(.ctors)
44
    LONG(0)
45
    __CTOR_END__ = .;
46
    __DTOR_LIST__ = .;
47
    ___DTOR_LIST__ = .;
48
    LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
49
    *(.dtors)
50
     LONG(0)
51
    __DTOR_END__ = .;
52
    *(.rodata)
53
    *(.rodata.*)
54
    *(.gcc_except_table)
55
 
56
    . = ALIGN(0x2);
57
    __INIT_SECTION__ = . ;
58
    LONG (0x4e560000)   /* linkw %fp,#0 */
59
    *(.init)
60
    SHORT (0x4e5e)      /* unlk %fp */
61
    SHORT (0x4e75)      /* rts */
62
 
63
    __FINI_SECTION__ = . ;
64
    LONG (0x4e560000)   /* linkw %fp,#0 */
65
    *(.fini)
66
    SHORT (0x4e5e)      /* unlk %fp */
67
    SHORT (0x4e75)      /* rts */
68
 
69
    *(.lit)
70
    . = ALIGN(16);
71
    _etext = .;
72
    etext = .;
73
  } > sdram
74
 
75
  .data :
76
  {
77
    copy_start = .;
78
    *(.shdata)
79
    *(.data)
80
    *(.gnu.linkonce.d.*)
81
    . = ALIGN (16);
82
    _edata = .;
83
    copy_end = .;
84
  } > sdram
85
  __data_load_start = LOADADDR(.data);
86
  __data_load_end = __data_load_start + SIZEOF(.data);
87
 
88
  .bss :
89
  {
90
    . = ALIGN(0x4);
91
    __bss_start = . ;
92
    *(.shbss)
93
    *(.bss)
94
    *(COMMON)
95
    _end =  ALIGN (0x8);
96
    __end = _end;
97
  } > sdram
98
 
99
  .stab 0 (NOLOAD) :
100
  {
101
    *(.stab)
102
  }
103
 
104
  .stabstr 0 (NOLOAD) :
105
  {
106
    *(.stabstr)
107
  }
108
}
109
 
110
__IPSBAR            = ADDR(.ipsbar);
111
 
112
__SDRAM             = ADDR(.sdram);
113
__SDRAM_SIZE        = SIZEOF(.sdram);
114
 
115
__SRAM              = ADDR(.sram);
116
__SRAM_SIZE         = SIZEOF(.sram);
117
 
118
__FLASH             = ADDR(.flash);
119
__FLASH_SIZE        = SIZEOF(.flash);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.