OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MCF5235_GCC/] [system/] [init.c] - Blame information for rev 584

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 584 jeremybenn
/*
2
    FreeRTOS MCF5235 port - Copyright (C) 2006 Christian Walter.
3
 
4
    This file is part of the FreeRTOS distribution.
5
 
6
    FreeRTOS is free software; you can redistribute it and/or modify
7
    it under the terms of the GNU General Public License** as published by
8
    the Free Software Foundation; either version 2 of the License, or
9
    (at your option) any later version.
10
 
11
    FreeRTOS is distributed in the hope that it will be useful,
12
    but WITHOUT ANY WARRANTY; without even the implied warranty of
13
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
    GNU General Public License for more details.
15
 
16
    You should have received a copy of the GNU General Public License
17
    along with FreeRTOS; if not, write to the Free Software
18
    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
19
 
20
    A special exception to the GPL can be applied should you wish to distribute
21
    a combined work that includes FreeRTOS, without being obliged to provide
22
    the source code for any proprietary components.  See the licensing section
23
    of http://www.FreeRTOS.org for full details of how and when the exception
24
    can be applied.
25
 
26
    ***************************************************************************
27
    ***************************************************************************
28
    *                                                                         *
29
    * Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *
30
        *                                                                         *
31
        * This is a concise, step by step, 'hands on' guide that describes both   *
32
        * general multitasking concepts and FreeRTOS specifics. It presents and   *
33
        * explains numerous examples that are written using the FreeRTOS API.     *
34
        * Full source code for all the examples is provided in an accompanying    *
35
        * .zip file.                                                              *
36
    *                                                                         *
37
    ***************************************************************************
38
    ***************************************************************************
39
 
40
        Please ensure to read the configuration and relevant port sections of the
41
        online documentation.
42
 
43
        http://www.FreeRTOS.org - Documentation, latest information, license and
44
        contact details.
45
 
46
        http://www.SafeRTOS.com - A version that is certified for use in safety
47
        critical systems.
48
 
49
        http://www.OpenRTOS.com - Commercial support, development, porting,
50
        licensing and training services.
51
*/
52
 
53
#include "mcf5xxx.h"
54
#include "mcf523x.h"
55
 
56
/* Function prototypes */
57
void            init_main( void );
58
static void     disable_interrupts( void );
59
static void     disable_watchdog_timer( void );
60
static void     disable_cache( void );
61
static void     init_ipsbar( void );
62
static void     init_basics( void );
63
static void     init_clock_config( void );
64
static void     init_chip_selects( void );
65
static void     init_bus_config( void );
66
static void     init_cache( void );
67
static void     init_eport( void );
68
static void     init_flexcan( void );
69
static void     init_power_management( void );
70
static void     init_dma_timers( void );
71
static void     init_interrupt_timers( void );
72
static void     init_watchdog_timers( void );
73
static void     init_pin_assignments( void );
74
static void     init_sdram_controller( void );
75
static void     init_interrupt_controller( void );
76
 
77
 
78
/*********************************************************************
79
* init_main - Main entry point for initialisation code               *
80
**********************************************************************/
81
void
82
init_main( void )
83
{
84
 
85
    /* Initialise base address of peripherals, VBR, etc */
86
    init_ipsbar(  );
87
    init_basics(  );
88
    init_clock_config(  );
89
 
90
    /* Disable interrupts, watchdog timer, cache */
91
    disable_interrupts(  );
92
    disable_watchdog_timer(  );
93
    disable_cache(  );
94
 
95
    /* Initialise individual modules */
96
    init_chip_selects(  );
97
    init_bus_config(  );
98
    init_cache(  );
99
    init_eport(  );
100
    init_flexcan(  );
101
    init_power_management(  );
102
    init_dma_timers(  );
103
    init_interrupt_timers(  );
104
    init_watchdog_timers(  );
105
    init_pin_assignments(  );
106
    init_sdram_controller(  );
107
 
108
    /* Initialise interrupt controller */
109
    init_interrupt_controller(  );
110
}
111
 
112
/*********************************************************************
113
* disable_interrupts - Disable all interrupt sources                 *
114
**********************************************************************/
115
static void
116
disable_interrupts( void )
117
{
118
    vuint8         *p;
119
    int             i;
120
 
121
 
122
    /* Set ICR008-ICR063 to 0x0 */
123
    p = ( vuint8 * ) & MCF_INTC0_ICR8;
124
    for( i = 8; i <= 63; i++ )
125
        *p++ = 0x0;
126
 
127
    /* Set ICR108-ICR163 to 0x0 */
128
    p = ( vuint8 * ) & MCF_INTC1_ICR8;
129
    for( i = 108; i <= 163; i++ )
130
        *p++ = 0x0;
131
}
132
 
133
 
134
/*********************************************************************
135
* disable_watchdog_timer - Disable system watchdog timer             *
136
**********************************************************************/
137
static void
138
disable_watchdog_timer( void )
139
{
140
 
141
    /* Disable Core Watchdog Timer */
142
    MCF_SCM_CWCR = 0;
143
}
144
 
145
/*********************************************************************
146
* disable_cache - Disable and invalidate cache                       *
147
**********************************************************************/
148
static void
149
disable_cache( void )
150
{
151
    asm ( "move.l   #0x01000000, %d0" );
152
    asm ( "movec    %d0, %CACR" );
153
}
154
 
155
/*********************************************************************
156
* init_basics - Configuration Information & VBR                      *
157
**********************************************************************/
158
static void
159
init_basics( void )
160
{
161
    int             i;
162
    extern uint32   __RAMVEC[];
163
    extern uint32   __ROMVEC[];
164
 
165
    /* Transfer size not driven on SIZ[1:0] pins during external cycles
166
       Processor Status (PST) and Debug Data (DDATA) functions disabled
167
       Bus monitor disabled
168
       Output pads configured for full strength
169
     */
170
    MCF_CCM_CCR = ( 0x1 << 15 ) | MCF_CCM_CCR_BME;
171
 
172
    /* Set up RAM vectors */
173
    for( i = 0; i < 256; i++ )
174
 
175
    {
176
        __RAMVEC[i] = __ROMVEC[i];
177
    }
178
    asm( "move.l   %0,%%d0": :"i"( __RAMVEC ) );
179
    asm( "movec    %d0,%vbr" );
180
}
181
 
182
 
183
/*********************************************************************
184
* init_clock_config - Clock Module                                   *
185
**********************************************************************/
186
static void
187
init_clock_config( void )
188
{
189
    /* Clock module uses normal PLL mode with 25.0000 MHz external reference (Fref)
190
       MFD = 0, RFD = 1
191
       Bus clock frequency = 25.00 MHz
192
       Processor clock frequency = 2 x bus clock = 50.00 MHz
193
       Frequency Modulation disabled
194
       Loss of clock detection disabled
195
       Reset/Interrupt on loss of lock disabled
196
     */
197
    MCF_FMPLL_SYNCR = 0x00100000;       /* Set RFD=RFD+1 to avoid frequency overshoot */
198
    while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 )    /* Wait for PLL to lock */
199
        ;
200
    MCF_FMPLL_SYNCR = 0x00080000;       /* Set desired RFD */
201
    while( ( MCF_FMPLL_SYNSR & 0x08 ) == 0 )    /* Wait for PLL to lock */
202
        ;
203
}
204
 
205
 
206
/*********************************************************************
207
* init_ipsbar - Internal Peripheral System Base Address (IPSBAR)     *
208
**********************************************************************/
209
static void
210
init_ipsbar( void )
211
{
212
    extern int  __SRAM;
213
 
214
    /* Base address of internal peripherals (IPSBAR) = 0x40000000
215
 
216
       Note: Processor powers up with IPS base address = 0x40000000
217
       Write to IPS base + 0x00000000 to set new value
218
     */
219
    *( vuint32 * ) 0x40000000 = ( vuint32 ) __IPSBAR + 1;
220
 
221
    /* Configure RAMBAR in SCM module and allow dual-ported access. */
222
    MCF_SCM_RAMBAR = ( uint32 ) &__SRAM | MCF_SCM_RAMBAR_BDE;
223
}
224
 
225
/*********************************************************************
226
* init_chip_selects - Chip Select Module                             *
227
**********************************************************************/
228
static void
229
init_chip_selects( void )
230
{
231
    extern void __FLASH;
232
    uint32 FLASH_ADDR = (uint32)&__FLASH;
233
 
234
    /* Chip Select 0 - External Flash */
235
    MCF_CS_CSAR0 = MCF_CS_CSAR_BA( FLASH_ADDR );
236
    MCF_CS_CSCR0 = ( 0
237
                     | MCF_CS_CSCR_IWS( 6 )
238
                     | MCF_CS_CSCR_AA | MCF_CS_CSCR_PS_16 );
239
    MCF_CS_CSMR0 = MCF_CS_CSMR_BAM_2M | MCF_CS_CSMR_V;
240
 
241
    /* Chip Select 1 disabled (CSMR1[V] = 0) */
242
    MCF_CS_CSAR1 = 0;
243
    MCF_CS_CSMR1 = 0;
244
    MCF_CS_CSCR1 = 0;
245
 
246
    /* Chip Select 2 disabled (CSMR2[V] = 0) */
247
    MCF_CS_CSAR2 = 0;
248
    MCF_CS_CSMR2 = 0;
249
    MCF_CS_CSCR2 = 0;
250
 
251
    /* Chip Select 3 disabled (CSMR3[V] = 0) */
252
    MCF_CS_CSAR3 = 0;
253
    MCF_CS_CSMR3 = 0;
254
    MCF_CS_CSCR3 = 0;
255
 
256
    /* Chip Select 4 disabled (CSMR4[V] = 0) */
257
    MCF_CS_CSAR4 = 0;
258
    MCF_CS_CSMR4 = 0;
259
    MCF_CS_CSCR4 = 0;
260
 
261
    /* Chip Select 5 disabled (CSMR5[V] = 0) */
262
    MCF_CS_CSAR5 = 0;
263
    MCF_CS_CSMR5 = 0;
264
    MCF_CS_CSCR5 = 0;
265
 
266
    /* Chip Select 6 disabled (CSMR6[V] = 0) */
267
    MCF_CS_CSAR6 = 0;
268
    MCF_CS_CSMR6 = 0;
269
    MCF_CS_CSCR6 = 0;
270
 
271
    /* Chip Select 7 disabled (CSMR7[V] = 0) */
272
    MCF_CS_CSAR7 = 0;
273
    MCF_CS_CSMR7 = 0;
274
    MCF_CS_CSCR7 = 0;
275
}
276
 
277
/*********************************************************************
278
* init_bus_config - Internal Bus Arbitration                         *
279
**********************************************************************/
280
static void
281
init_bus_config( void )
282
{
283
 
284
    /* Use round robin arbitration scheme
285
       Assigned priorities (highest first):
286
       Ethernet
287
       DMA Controller
288
       ColdFire Core
289
       DMA bandwidth control disabled
290
       Park on last active bus master
291
     */
292
    MCF_SCM_MPARK =
293
        MCF_SCM_MPARK_M3_PRTY( 0x3 ) | MCF_SCM_MPARK_M2_PRTY( 0x2 ) |
294
        MCF_SCM_MPARK_M1_PRTY( 0x1 );
295
}
296
 
297
/*********************************************************************
298
* init_cache - Instruction/Data Cache                                *
299
**********************************************************************/
300
static void
301
init_cache( void )
302
{
303
    /* Configured as split cache: 4 KByte instruction cache and 4 Kbyte data cache
304
       ACR0: Don't cache accesses to 16 MB memory region at address $20000000
305
       ACR1: Don't cache accesses to 1 GB memory region at address $40000000
306
       CACR: Cache accesses to the rest of memory
307
    */
308
    asm("move.l   #0x80000000,%d0");
309
    asm("movec    %d0,%CACR");
310
    asm("move.l   #0x2000c040,%d0");
311
    asm("movec    %d0,%ACR0");
312
    asm("move.l   #0x403fc040,%d0");
313
    asm("movec    %d0,%ACR1");
314
 
315
    /* Instruction/Data cache disabled. */
316
    //asm( "move.l   #0x00000000, %d0" );
317
    //asm( "movec    %d0,%cacr" );
318
}
319
 
320
/*********************************************************************
321
* init_eport - Edge Port Module (EPORT)                              *
322
**********************************************************************/
323
static void
324
init_eport( void )
325
{
326
 
327
    /* Pins 1-7 configured as GPIO inputs */
328
    MCF_EPORT_EPPAR = 0;
329
    MCF_EPORT_EPDDR = 0;
330
    MCF_EPORT_EPIER = 0;
331
}
332
 
333
/*********************************************************************
334
* init_flexcan - FlexCAN Module                                      *
335
**********************************************************************/
336
static void
337
init_flexcan( void )
338
{
339
 
340
    /* FlexCAN controller 0 disabled (CANMCR0[MDIS]=1) */
341
    MCF_CAN_IMASK0 = 0;
342
    MCF_CAN_RXGMASK0 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
343
    MCF_CAN_RX14MASK0 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
344
    MCF_CAN_RX15MASK0 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
345
    MCF_CAN_CANCTRL0 = 0;
346
    MCF_CAN_CANMCR0 =
347
        MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
348
        MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
349
 
350
    /* FlexCAN controller 1 disabled (CANMCR1[MDIS]=1) */
351
    MCF_CAN_IMASK1 = 0;
352
    MCF_CAN_RXGMASK1 = MCF_CAN_RXGMASK_MI( 0x1fffffff );
353
    MCF_CAN_RX14MASK1 = MCF_CAN_RX14MASK_MI( 0x1fffffff );
354
    MCF_CAN_RX15MASK1 = MCF_CAN_RX15MASK_MI( 0x1fffffff );
355
    MCF_CAN_CANCTRL1 = 0;
356
    MCF_CAN_CANMCR1 =
357
        MCF_CAN_CANMCR_MDIS | MCF_CAN_CANMCR_FRZ | MCF_CAN_CANMCR_HALT |
358
        MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB( 0xf );
359
}
360
 
361
/*********************************************************************
362
* init_power_management - Power Management                           *
363
**********************************************************************/
364
static void
365
init_power_management( void )
366
{
367
 
368
    /* On executing STOP instruction, processor enters RUN mode
369
       Mode is exited when an interrupt of level 1 or higher is received
370
     */
371
    MCF_SCM_LPICR = MCF_SCM_LPICR_ENBSTOP;
372
    MCF_CCM_LPCR = 0;
373
}
374
 
375
/*********************************************************************
376
* init_sdram_controller - SDRAM Controller                           *
377
**********************************************************************/
378
static void
379
init_sdram_controller( void )
380
{
381
    extern void __SDRAM;
382
    uint32 SDRAM_ADDR = (uint32)&__SDRAM;
383
    int             i;
384
 
385
 
386
    /*
387
     * Check to see if the SDRAM has already been initialized
388
     * by a run control tool
389
     */
390
    if( !( MCF_SDRAMC_DACR0 & MCF_SDRAMC_DACR0_RE ) )
391
    {
392
        /* Initialize DRAM Control Register: DCR */
393
        MCF_SDRAMC_DCR = ( MCF_SDRAMC_DCR_RTIM( 1 ) |
394
                           MCF_SDRAMC_DCR_RC( ( 15 * FSYS_2 ) >> 4 ) );
395
 
396
        /* Initialize DACR0 */
397
        MCF_SDRAMC_DACR0 = ( MCF_SDRAMC_DACR0_BA( SDRAM_ADDR >> 18UL ) |
398
                             MCF_SDRAMC_DACR0_CASL( 1 ) |
399
                             MCF_SDRAMC_DACR0_CBM( 3 ) |
400
                             MCF_SDRAMC_DACR0_PS( 0 ) );
401
 
402
        /* Initialize DMR0 */
403
        MCF_SDRAMC_DMR0 = ( MCF_SDRAMC_DMR_BAM_16M | MCF_SDRAMC_DMR0_V );
404
 
405
        /* Set IP (bit 3) in DACR */
406
        MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_IP;
407
 
408
        /* Wait 30ns to allow banks to precharge */
409
        for( i = 0; i < 5; i++ )
410
        {
411
            asm volatile    ( " nop" );
412
        }
413
        /* Write to this block to initiate precharge */
414
        *( uint32 * ) ( SDRAM_ADDR ) = 0xA5A59696;
415
 
416
        /* Set RE (bit 15) in DACR */
417
        MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_RE;
418
 
419
        /* Wait for at least 8 auto refresh cycles to occur */
420
        for( i = 0; i < 2000; i++ )
421
        {
422
            asm volatile    ( "nop" );
423
        }
424
        /* Finish the configuration by issuing the IMRS. */
425
        MCF_SDRAMC_DACR0 |= MCF_SDRAMC_DACR0_MRS;
426
 
427
        /* Write to the SDRAM Mode Register */
428
        *( uint32 * ) ( SDRAM_ADDR + 0x400 ) = 0xA5A59696;
429
    }
430
}
431
 
432
/*********************************************************************
433
* init_dma_timers - DMA Timer Modules                                *
434
**********************************************************************/
435
static void
436
init_dma_timers( void )
437
{
438
 
439
    /* DMA Timer 0 disabled (DTMR0[RST] = 0) */
440
    MCF_TIMER_DTMR0 = 0;
441
    MCF_TIMER_DTXMR0 = 0;
442
    MCF_TIMER_DTRR0 = 0xffffffff;
443
 
444
    /* DMA Timer 1 disabled (DTMR1[RST] = 0) */
445
    MCF_TIMER_DTMR1 = 0;
446
    MCF_TIMER_DTXMR1 = 0;
447
    MCF_TIMER_DTRR1 = 0xffffffff;
448
 
449
    /* DMA Timer 2 disabled (DTMR2[RST] = 0) */
450
    MCF_TIMER_DTMR2 = 0;
451
    MCF_TIMER_DTXMR2 = 0;
452
    MCF_TIMER_DTRR2 = 0xffffffff;
453
 
454
    /* DMA Timer 3 disabled (DTMR3[RST] = 0) */
455
    MCF_TIMER_DTMR3 = 0;
456
    MCF_TIMER_DTXMR3 = 0;
457
    MCF_TIMER_DTRR3 = 0xffffffff;
458
}
459
 
460
/**********************************************************************
461
* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules  *
462
***********************************************************************/
463
static void
464
init_interrupt_timers( void )
465
{
466
 
467
    /* PIT0 disabled (PCSR0[EN]=0) */
468
    MCF_PIT_PCSR0 = 0;
469
 
470
    /* PIT1 disabled (PCSR1[EN]=0) */
471
    MCF_PIT_PCSR1 = 0;
472
 
473
    /* PIT2 disabled (PCSR2[EN]=0) */
474
    MCF_PIT_PCSR2 = 0;
475
 
476
    /* PIT3 disabled (PCSR3[EN]=0) */
477
    MCF_PIT_PCSR3 = 0;
478
}
479
 
480
/*********************************************************************
481
* init_watchdog_timers - Watchdog Timer Modules                      *
482
**********************************************************************/
483
static void
484
init_watchdog_timers( void )
485
{
486
 
487
    /* Watchdog Timer disabled (WCR[EN]=0)
488
       NOTE: WCR and WMR cannot be written again until after the
489
       processor is reset.
490
     */
491
    MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
492
    MCF_WTM_WMR = 0xffff;
493
 
494
    /* Core Watchdog Timer disabled (CWCR[CWE]=0) */
495
    MCF_SCM_CWCR = 0;
496
}
497
 
498
/*********************************************************************
499
* init_interrupt_controller - Interrupt Controller                   *
500
**********************************************************************/
501
static void
502
init_interrupt_controller( void )
503
{
504
 
505
    /* Configured interrupt sources in order of priority...
506
       Level 7:  External interrupt /IRQ7, (initially masked)
507
       Level 6:  External interrupt /IRQ6, (initially masked)
508
       Level 5:  External interrupt /IRQ5, (initially masked)
509
       Level 4:  External interrupt /IRQ4, (initially masked)
510
       Level 3:  External interrupt /IRQ3, (initially masked)
511
       Level 2:  External interrupt /IRQ2, (initially masked)
512
       Level 1:  External interrupt /IRQ1, (initially masked)
513
     */
514
    MCF_INTC0_ICR1 = 0;
515
    MCF_INTC0_ICR2 = 0;
516
    MCF_INTC0_ICR3 = 0;
517
    MCF_INTC0_ICR4 = 0;
518
    MCF_INTC0_ICR5 = 0;
519
    MCF_INTC0_ICR6 = 0;
520
    MCF_INTC0_ICR7 = 0;
521
    MCF_INTC0_ICR8 = 0;
522
    MCF_INTC0_ICR9 = 0;
523
    MCF_INTC0_ICR10 = 0;
524
    MCF_INTC0_ICR11 = 0;
525
    MCF_INTC0_ICR12 = 0;
526
    MCF_INTC0_ICR13 = 0;
527
    MCF_INTC0_ICR14 = 0;
528
    MCF_INTC0_ICR15 = 0;
529
    MCF_INTC0_ICR17 = 0;
530
    MCF_INTC0_ICR18 = 0;
531
    MCF_INTC0_ICR19 = 0;
532
    MCF_INTC0_ICR20 = 0;
533
    MCF_INTC0_ICR21 = 0;
534
    MCF_INTC0_ICR22 = 0;
535
    MCF_INTC0_ICR23 = 0;
536
    MCF_INTC0_ICR24 = 0;
537
    MCF_INTC0_ICR25 = 0;
538
    MCF_INTC0_ICR26 = 0;
539
    MCF_INTC0_ICR27 = 0;
540
    MCF_INTC0_ICR28 = 0;
541
    MCF_INTC0_ICR29 = 0;
542
    MCF_INTC0_ICR30 = 0;
543
    MCF_INTC0_ICR31 = 0;
544
    MCF_INTC0_ICR32 = 0;
545
    MCF_INTC0_ICR33 = 0;
546
    MCF_INTC0_ICR34 = 0;
547
    MCF_INTC0_ICR35 = 0;
548
    MCF_INTC0_ICR36 = 0;
549
    MCF_INTC0_ICR37 = 0;
550
    MCF_INTC0_ICR38 = 0;
551
    MCF_INTC0_ICR39 = 0;
552
    MCF_INTC0_ICR40 = 0;
553
    MCF_INTC0_ICR41 = 0;
554
    MCF_INTC0_ICR42 = 0;
555
    MCF_INTC0_ICR43 = 0;
556
    MCF_INTC0_ICR44 = 0;
557
    MCF_INTC0_ICR45 = 0;
558
    MCF_INTC0_ICR46 = 0;
559
    MCF_INTC0_ICR47 = 0;
560
    MCF_INTC0_ICR48 = 0;
561
    MCF_INTC0_ICR49 = 0;
562
    MCF_INTC0_ICR50 = 0;
563
    MCF_INTC0_ICR51 = 0;
564
    MCF_INTC0_ICR52 = 0;
565
    MCF_INTC0_ICR53 = 0;
566
    MCF_INTC0_ICR54 = 0;
567
    MCF_INTC0_ICR55 = 0;
568
    MCF_INTC0_ICR56 = 0;
569
    MCF_INTC0_ICR57 = 0;
570
    MCF_INTC0_ICR58 = 0;
571
    MCF_INTC0_ICR59 = 0;
572
    MCF_INTC0_ICR60 = 0;
573
    MCF_INTC1_ICR8 = 0;
574
    MCF_INTC1_ICR9 = 0;
575
    MCF_INTC1_ICR10 = 0;
576
    MCF_INTC1_ICR11 = 0;
577
    MCF_INTC1_ICR12 = 0;
578
    MCF_INTC1_ICR13 = 0;
579
    MCF_INTC1_ICR14 = 0;
580
    MCF_INTC1_ICR15 = 0;
581
    MCF_INTC1_ICR16 = 0;
582
    MCF_INTC1_ICR17 = 0;
583
    MCF_INTC1_ICR18 = 0;
584
    MCF_INTC1_ICR19 = 0;
585
    MCF_INTC1_ICR20 = 0;
586
    MCF_INTC1_ICR21 = 0;
587
    MCF_INTC1_ICR22 = 0;
588
    MCF_INTC1_ICR23 = 0;
589
    MCF_INTC1_ICR24 = 0;
590
    MCF_INTC1_ICR25 = 0;
591
    MCF_INTC1_ICR27 = 0;
592
    MCF_INTC1_ICR28 = 0;
593
    MCF_INTC1_ICR29 = 0;
594
    MCF_INTC1_ICR30 = 0;
595
    MCF_INTC1_ICR31 = 0;
596
    MCF_INTC1_ICR32 = 0;
597
    MCF_INTC1_ICR33 = 0;
598
    MCF_INTC1_ICR34 = 0;
599
    MCF_INTC1_ICR35 = 0;
600
    MCF_INTC1_ICR36 = 0;
601
    MCF_INTC1_ICR37 = 0;
602
    MCF_INTC1_ICR38 = 0;
603
    MCF_INTC1_ICR39 = 0;
604
    MCF_INTC1_ICR40 = 0;
605
    MCF_INTC1_ICR41 = 0;
606
    MCF_INTC1_ICR42 = 0;
607
    MCF_INTC1_ICR59 = 0;
608
    MCF_INTC0_IMRH = 0xffffffff;
609
    MCF_INTC0_IMRL =
610
        MCF_INTC0_IMRL_INT_MASK31 | MCF_INTC0_IMRL_INT_MASK30 |
611
        MCF_INTC0_IMRL_INT_MASK29 | MCF_INTC0_IMRL_INT_MASK28 |
612
        MCF_INTC0_IMRL_INT_MASK27 | MCF_INTC0_IMRL_INT_MASK26 |
613
        MCF_INTC0_IMRL_INT_MASK25 | MCF_INTC0_IMRL_INT_MASK24 |
614
        MCF_INTC0_IMRL_INT_MASK23 | MCF_INTC0_IMRL_INT_MASK22 |
615
        MCF_INTC0_IMRL_INT_MASK21 | MCF_INTC0_IMRL_INT_MASK20 |
616
        MCF_INTC0_IMRL_INT_MASK19 | MCF_INTC0_IMRL_INT_MASK18 |
617
        MCF_INTC0_IMRL_INT_MASK17 | MCF_INTC0_IMRL_INT_MASK16 |
618
        MCF_INTC0_IMRL_INT_MASK15 | MCF_INTC0_IMRL_INT_MASK14 |
619
        MCF_INTC0_IMRL_INT_MASK13 | MCF_INTC0_IMRL_INT_MASK12 |
620
        MCF_INTC0_IMRL_INT_MASK11 | MCF_INTC0_IMRL_INT_MASK10 |
621
        MCF_INTC0_IMRL_INT_MASK9 | MCF_INTC0_IMRL_INT_MASK8 |
622
        MCF_INTC0_IMRL_INT_MASK7 | MCF_INTC0_IMRL_INT_MASK6 |
623
        MCF_INTC0_IMRL_INT_MASK5 | MCF_INTC0_IMRL_INT_MASK4 |
624
        MCF_INTC0_IMRL_INT_MASK3 | MCF_INTC0_IMRL_INT_MASK2 |
625
        MCF_INTC0_IMRL_INT_MASK1;
626
    MCF_INTC1_IMRH = 0xffffffff;
627
    MCF_INTC1_IMRL =
628
        MCF_INTC1_IMRL_INT_MASK31 | MCF_INTC1_IMRL_INT_MASK30 |
629
        MCF_INTC1_IMRL_INT_MASK29 | MCF_INTC1_IMRL_INT_MASK28 |
630
        MCF_INTC1_IMRL_INT_MASK27 | MCF_INTC1_IMRL_INT_MASK26 |
631
        MCF_INTC1_IMRL_INT_MASK25 | MCF_INTC1_IMRL_INT_MASK24 |
632
        MCF_INTC1_IMRL_INT_MASK23 | MCF_INTC1_IMRL_INT_MASK22 |
633
        MCF_INTC1_IMRL_INT_MASK21 | MCF_INTC1_IMRL_INT_MASK20 |
634
        MCF_INTC1_IMRL_INT_MASK19 | MCF_INTC1_IMRL_INT_MASK18 |
635
        MCF_INTC1_IMRL_INT_MASK17 | MCF_INTC1_IMRL_INT_MASK16 |
636
        MCF_INTC1_IMRL_INT_MASK15 | MCF_INTC1_IMRL_INT_MASK14 |
637
        MCF_INTC1_IMRL_INT_MASK13 | MCF_INTC1_IMRL_INT_MASK12 |
638
        MCF_INTC1_IMRL_INT_MASK11 | MCF_INTC1_IMRL_INT_MASK10 |
639
        MCF_INTC1_IMRL_INT_MASK9 | MCF_INTC1_IMRL_INT_MASK8 |
640
        MCF_INTC1_IMRL_INT_MASK7 | MCF_INTC1_IMRL_INT_MASK6 |
641
        MCF_INTC1_IMRL_INT_MASK5 | MCF_INTC1_IMRL_INT_MASK4 |
642
        MCF_INTC1_IMRL_INT_MASK3 | MCF_INTC1_IMRL_INT_MASK2 |
643
        MCF_INTC1_IMRL_INT_MASK1;
644
}
645
 
646
/*********************************************************************
647
* init_pin_assignments - Pin Assignment and General Purpose I/O      *
648
**********************************************************************/
649
static void
650
init_pin_assignments( void )
651
{
652
 
653
    /* Pin assignments for port ADDR
654
       Pins are all GPIO inputs
655
     */
656
    MCF_GPIO_PDDR_APDDR = 0;
657
    MCF_GPIO_PAR_AD = MCF_GPIO_PAR_AD_PAR_ADDR23
658
        | MCF_GPIO_PAR_AD_PAR_ADDR22
659
        | MCF_GPIO_PAR_AD_PAR_ADDR21 | MCF_GPIO_PAR_AD_PAR_DATAL;
660
 
661
    /* Pin assignments for ports DATAH and DATAL
662
       Pins are all GPIO inputs
663
     */
664
    MCF_GPIO_PDDR_DATAH = 0;
665
    MCF_GPIO_PDDR_DATAL = 0;
666
 
667
    /* Pin assignments for port BUSCTL
668
       Pin /OE        : External bus output enable, /OE
669
       Pin /TA        : External bus transfer acknowledge, /TA
670
       Pin /TEA       : External bus transfer error acknowledge, /TEA
671
       Pin R/W        : External bus read/write indication, R/W
672
       Pin TSIZ1      : External bus transfer size TSIZ1 or DMA acknowledge /DACK1
673
       Pin TSIZ0      : External bus transfer size TSIZ0 or DMA acknowledge /DACK0
674
       Pin /TS        : External bus transfer start, /TS
675
       Pin /TIP       : External bus transfer in progess, /TIP
676
     */
677
    MCF_GPIO_PDDR_BUSCTL = 0;
678
    MCF_GPIO_PAR_BUSCTL =
679
        MCF_GPIO_PAR_BUSCTL_PAR_OE | MCF_GPIO_PAR_BUSCTL_PAR_TA |
680
        MCF_GPIO_PAR_BUSCTL_PAR_TEA( 0x3 ) | MCF_GPIO_PAR_BUSCTL_PAR_RWB |
681
        MCF_GPIO_PAR_BUSCTL_PAR_TSIZ1 | MCF_GPIO_PAR_BUSCTL_PAR_TSIZ0 |
682
        MCF_GPIO_PAR_BUSCTL_PAR_TS( 0x3 ) |
683
        MCF_GPIO_PAR_BUSCTL_PAR_TIP( 0x3 );
684
 
685
    /* Pin assignments for port BS
686
       Pin /BS3       : External byte strobe /BS3
687
       Pin /BS2       : External byte strobe /BS2
688
       Pin /BS1       : External byte strobe /BS1
689
       Pin /BS0       : External byte strobe /BS0
690
     */
691
    MCF_GPIO_PDDR_BS = 0;
692
    MCF_GPIO_PAR_BS =
693
        MCF_GPIO_PAR_BS_PAR_BS3 | MCF_GPIO_PAR_BS_PAR_BS2 |
694
        MCF_GPIO_PAR_BS_PAR_BS1 | MCF_GPIO_PAR_BS_PAR_BS0;
695
 
696
    /* Pin assignments for port CS
697
       Pin /CS7       : Chip select /CS7
698
       Pin /CS6       : Chip select /CS6
699
       Pin /CS5       : Chip select /CS5
700
       Pin /CS4       : Chip select /CS4
701
       Pin /CS3       : Chip select /CS3
702
       Pin /CS2       : Chip select /CS2
703
       Pin /CS1       : Chip select /CS1
704
     */
705
    MCF_GPIO_PDDR_CS = 0;
706
    MCF_GPIO_PAR_CS =
707
        MCF_GPIO_PAR_CS_PAR_CS7 | MCF_GPIO_PAR_CS_PAR_CS6 |
708
        MCF_GPIO_PAR_CS_PAR_CS5 | MCF_GPIO_PAR_CS_PAR_CS4 |
709
        MCF_GPIO_PAR_CS_PAR_CS3 | MCF_GPIO_PAR_CS_PAR_CS2 |
710
        MCF_GPIO_PAR_CS_PAR_CS1;
711
 
712
    /* Pin assignments for port SDRAM
713
       Pin /SD_WE     : SDRAM controller /SD_WE
714
       Pin /SD_SCAS   : SDRAM controller /SD_SCAS
715
       Pin /SD_SRAS   : SDRAM controller /SD_SRAS
716
       Pin /SD_SCKE   : SDRAM controller /SD_SCKE
717
       Pin /SD_CS1    : SDRAM controller /SD_CS1
718
       Pin /SD_CS0    : SDRAM controller /SD_CS0
719
     */
720
    MCF_GPIO_PDDR_SDRAM = 0;
721
    MCF_GPIO_PAR_SDRAM =
722
        MCF_GPIO_PAR_SDRAM_PAR_SDWE | MCF_GPIO_PAR_SDRAM_PAR_SCAS |
723
        MCF_GPIO_PAR_SDRAM_PAR_SRAS | MCF_GPIO_PAR_SDRAM_PAR_SCKE |
724
        MCF_GPIO_PAR_SDRAM_PAR_SDCS1 | MCF_GPIO_PAR_SDRAM_PAR_SDCS0;
725
 
726
    /* Pin assignments for port FECI2C
727
       Pins are all GPIO inputs
728
     */
729
    MCF_GPIO_PDDR_FECI2C = 0;
730
    MCF_GPIO_PAR_FECI2C =
731
        MCF_GPIO_PAR_FECI2C_PAR_EMDC_FEC | MCF_GPIO_PAR_FECI2C_PAR_EMDIO_FEC;
732
 
733
    /* Pin assignments for port UARTL
734
       Pins are all GPIO inputs
735
     */
736
    MCF_GPIO_PDDR_UARTL = 0;
737
    MCF_GPIO_PAR_UART = 0;
738
 
739
    /* Pin assignments for port UARTH
740
       Pin U2TXD      : GPIO input
741
       Pin U2RXD      : GPIO input
742
       Pin /IRQ2      : Interrupt request /IRQ2 or GPIO
743
     */
744
    MCF_GPIO_PDDR_UARTH = 0;
745
 
746
    /* Pin assignments for port QSPI
747
       Pins are all GPIO inputs
748
     */
749
    MCF_GPIO_PDDR_QSPI = 0;
750
    MCF_GPIO_PAR_QSPI = 0;
751
 
752
    /* Pin assignments for port TIMER
753
       Pins are all GPIO inputs
754
     */
755
    MCF_GPIO_PDDR_TIMER = 0;
756
    MCF_GPIO_PAR_TIMER = 0;
757
 
758
    /* Pin assignments for port ETPU
759
       Pins are all GPIO inputs
760
     */
761
    MCF_GPIO_PDDR_ETPU = 0;
762
    MCF_GPIO_PAR_ETPU = 0;
763
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.