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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MSP430X_MSP430F5438_IAR/] [F5XX_6XX_Core_Lib/] [hal_UCS.h] - Blame information for rev 584

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Line No. Rev Author Line
1 584 jeremybenn 
//*******************************************************************************
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//  Provides Functions to Initialize the UCS/FLL and clock sources
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//    File: hal_ucs.c
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//
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//    Texas Instruments
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//
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//    Version 1.2
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//    11/24/09
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//
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//    V1.0  Initial Version
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//    V1.1  Added timeout function
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//    V1.1  Added parameter for XTDrive
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//*******************************************************************************
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#ifndef __hal_UCS
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#define __hal_UCS
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#include <stdint.h>
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#include "hal_macros.h"
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/*************************************************************************
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* MACROS
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**************************************************************************/
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/* Select source for FLLREF  e.g. SELECT_FLLREF(SELREF__XT1CLK) */
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#define SELECT_FLLREF(source) st(UCSCTL3 = (UCSCTL3 & ~(SELREF_7)) | (source);)
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/* Select source for ACLK    e.g. SELECT_ACLK(SELA__XT1CLK) */
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#define SELECT_ACLK(source)   st(UCSCTL4 = (UCSCTL4 & ~(SELA_7))   | (source);)
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/* Select source for MCLK    e.g. SELECT_MCLK(SELM__XT2CLK) */
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#define SELECT_MCLK(source)   st(UCSCTL4 = (UCSCTL4 & ~(SELM_7))   | (source);)
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/* Select source for SMCLK   e.g. SELECT_SMCLK(SELS__XT2CLK) */
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#define SELECT_SMCLK(source)  st(UCSCTL4 = (UCSCTL4 & ~(SELS_7))   | (source);)
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/* Select source for MCLK and SMCLK e.g. SELECT_MCLK_SMCLK(SELM__DCOCLK + SELS__DCOCLK) */
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#define SELECT_MCLK_SMCLK(sources) st(UCSCTL4 = (UCSCTL4 & ~(SELM_7 + SELS_7)) | (sources);)
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/* set ACLK/x */
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#define ACLK_DIV(x)         st(UCSCTL5 = (UCSCTL5 & ~(DIVA_7)) | (DIVA__##x);)
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/* set MCLK/x */
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#define MCLK_DIV(x)         st(UCSCTL5 = (UCSCTL5 & ~(DIVM_7)) | (DIVM__##x);)
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/* set SMCLK/x */
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#define SMCLK_DIV(x)        st(UCSCTL5 = (UCSCTL5 & ~(DIVS_7)) | (DIVS__##x);)
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/* Select divider for FLLREF  e.g. SELECT_FLLREFDIV(2) */
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#define SELECT_FLLREFDIV(x) st(UCSCTL3 = (UCSCTL3 & ~(FLLREFDIV_7))|(FLLREFDIV__##x);)
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//************************************************************************
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// Defines
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//************************************************************************
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#define UCS_STATUS_OK     0
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#define UCS_STATUS_ERROR  1
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//====================================================================
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/**
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 * Startup routine for 32kHz Cristal on LFXT1
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 *
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 * \param xtdrive: Bits defining the LFXT drive mode after startup
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 *
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*/
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extern void LFXT_Start(uint16_t xtdrive);
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//====================================================================
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/**
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 * Startup routine for 32kHz Cristal on LFXT1 with timeout counter
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 *
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 * \param xtdrive: Bits defining the LFXT drive mode after startup
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 * \param timeout: value for the timeout counter
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 *
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*/
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extern uint16_t LFXT_Start_Timeout(uint16_t xtdrive, uint16_t timeout);
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//====================================================================
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/**
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 * Startup routine for XT1
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 *
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 * \param xtdrive: Bits defining the XT drive mode
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 *
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*/
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extern void XT1_Start(uint16_t xtdrive);
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//====================================================================
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/**
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 * Startup routine for XT1 with timeout counter
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 *
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 * \param xtdrive: Bits defining the XT drive mode
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 * \param timeout: value for the timeout counter
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 *
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*/
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extern uint16_t XT1_Start_Timeout(uint16_t xtdrive, uint16_t timeout);
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//====================================================================
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/**
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 * Use XT1 in Bypasss mode
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 *
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*/
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extern void XT1_Bypass(void);
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//====================================================================
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/**
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 * Startup routine for XT2
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 *
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 * \param xtdrive: Bits defining the XT drive mode
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 *
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*/
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extern void XT2_Start(uint16_t xtdrive);
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//====================================================================
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/**
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 * Startup routine for XT2 with timeout counter
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 *
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 * \param xtdrive: Bits defining the XT drive mode
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 * \param timeout: value for the timeout counter
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 *
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*/
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extern uint16_t XT2_Start_Timeout(uint16_t xtdrive, uint16_t timeout);
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//====================================================================
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/**
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 * Use XT2 in Bypasss mode for MCLK
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 *
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*/
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extern void XT2_Bypass(void);
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//====================================================================
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/**
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  * Initializes FLL of the UCS and wait till settled
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  *
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  * \param fsystem  required system frequency (MCLK) in kHz
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  * \param ratio    ratio between fsystem and FLLREFCLK
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  */
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extern void Init_FLL_Settle(uint16_t fsystem, uint16_t ratio);
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//====================================================================
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/**
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  * Initializes FLL of the UCS
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  *
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  * \param fsystem  required system frequency (MCLK) in kHz
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  * \param ratio    ratio between fsystem and FLLREFCLK
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  */
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static void Init_FLL(uint16_t fsystem, uint16_t ratio);
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#endif /* __hal_UCS */

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