OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MSP430X_MSP430F5438_IAR/] [settings/] [RTOSDemo.dni] - Blame information for rev 820

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 584 jeremybenn 
[DebugChecksum]
2 
Checksum=1942227584
3 
[DisAssemblyWindow]
4 
NumStates=_ 1
5 
State 1=_ 1
6 
[InstructionProfiling]
7 
Enabled=_ 0
8 
[CodeCoverage]
9 
Enabled=_ 0
10 
[State Storage]
11 
Control Register=0
12 
[Sequencer]
13 
Control Register=0
14 
NextState0=0
15 
NextState1=0
16 
[Action Register]
17 
Break=1
18 
State Storage=0
19 
[Profiling]
20 
Enabled=0
21 
[StackPlugin]
22 
Enabled=0
23 
OverflowWarningsEnabled=1
24 
WarningThreshold=90
25 
SpWarningsEnabled=0
26 
WarnHow=0
27 
UseTrigger=1
28 
TriggerName=main
29 
LimitSize=0
30 
ByteLimit=50
31 
[Log file]
32 
LoggingEnabled=_ 0
33 
LogFile=_ ""
34 
Category=_ 0
35 
[TermIOLog]
36 
LoggingEnabled=_ 0
37 
LogFile=_ ""
38 
[CallStackLog]
39 
Enabled=0
40 
[DriverProfiling]
41 
Enabled=0
42 
Mode=604119078
43 
Graph=0
44 
Symbiont=0
45 
[Breakpoints]
46 
Count=0
47 
[FET]
48 
Clock mode=14
49 
Extended Clock mode=4047
50 
Secure Password=
51 
Extended Clock Control Enable=1
52 
Advanced Extended Clock Control=0
53 
Emulation mode=0
54 
Free running=0
55 
Shutting Down=1
56 
[Memory Dump]
57 
Start address=
58 
Lenghth=
59 
Address info=0
60 
Format=0
61 
Dump registers=0
62 
PC=0
63 
SP=0
64 
SR=0
65 
all registers=0
66 
File name=
67 
[Aliases]
68 
Count=0
69 
SuppressDialog=0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.