OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MicroBlaze/] [crt0.s] - Blame information for rev 590

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 584 jeremybenn
###################################-*-asm*-
2
#
3
# Copyright (c) 2001 Xilinx, Inc.  All rights reserved.
4
#
5
# Xilinx, Inc. CONFIDENTIAL
6
#
7
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
8
# COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
9
# ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
10
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
11
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
12
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
13
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
14
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
15
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
16
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
17
# AND FITNESS FOR A PARTICULAR PURPOSE.
18
#
19
# crt0.s
20
#
21
#       C RunTime:
22
#       Used for initialization of small data
23
#       anchors and stack for programs compiled using
24
#       Xilinx Gnu Tools. This routine also intializes the
25
#       exception and interrupt handlers
26
#
27
# $Id: crt0.s 2 2011-07-17 20:13:17Z filepang@gmail.com $
28
#
29
#######################################
30
 
31
/*      Vector map (Interrupts, Exceptions, Breakpoints)                 */
32
#       # 0x00 #                Jump to Start
33
#       # 0x04 #                nop
34
#       # 0x08 #                Imm instr for soft exception address [Hi halfword]
35
#       # 0x0c #                Jump to sof Exception handler        [Lo halfword]
36
#       # 0x10 #                Imm instr for interrupt address      [Hi halfword]
37
#       # 0x14 #                Jump to interrupt handler            [Lo halfword]
38
#       # 0x18 #                nop - Reserved for breakpoint vector
39
#       # 0x1C #                nop - Reserved for breakpoint vector
40
#       # 0x20 #                Imm instr for hw exception address   [Hi halfword]
41
#       # 0x24 #                Jump instr to hw exception handler   [Lo halfword]
42
 
43
        .globl _start
44
 
45
/*      Set the exception and interrupt address vectors    */
46
/*      to jump to the appropriate handlers                */
47
 
48
        .align 2
49
        .ent _start
50
        _start:
51
        bri     _start1                 # 0x00
52
        nop                             # 0x04
53
        nop                             # 0x08          # Reserve space for software exception vector
54
        nop                             # 0x0c
55
        nop                             # 0x10          # Reserve space for interrupt vector
56
        nop                             # 0x14
57
        nop                             # 0x18          # Reserve space for breakpoint vector
58
        nop                             # 0x1c
59
        nop                             # 0x18          # Reserve space for hw exception vector
60
        nop                             # 0x1c
61
 
62
        _start1:
63
/*      Set the Small Data Anchors and the Stack pointer  */
64
        la      r13, r0, _SDA_BASE_
65
        la      r2, r0, _SDA2_BASE_
66
        la      r1, r0, _stack-16       # 16 bytes (4 words are needed by
67
                                        # crt for args and link reg )
68
 
69
/*      Set the opcodes brai and imm for handlers         */
70
        la      r6,r0,0xb8080000        # [opcode for brai ]
71
        swi     r6,r0,0x4               # [brai opcode for reset]
72
        swi     r6,r0,0xc               # [brai opcode for exception]
73
        swi     r6,r0,0x14              # [brai opcode for interrupt]
74
        swi     r6,r0,0x24              # [brai opcode for hw exceptions]
75
 
76
        la      r6,r0,0xb0000000        # [opcode for imm ]
77
        swi     r6,r0,0x0               # [imm opcode for reset]
78
        swi     r6,r0,0x8               # [imm opcode for exception]
79
        swi     r6,r0,0x10              # [imm opocde for interrupt]
80
        swi     r6,r0,0x20              # [imm opocde for hw exceptions]
81
 
82
/*      Set Reset vector        */
83
        la      r6,r0,_start1
84
        sw      r6,r1,r0
85
        lhu     r7,r1,r0
86
        shi     r7,r0, 0x2              # [imm for reset]
87
        shi     r6,r0, 0x6              # [lower half for reset]
88
 
89
/*      Set Software Exception Handler */
90
        la      r6,r0,_exception_handler
91
        sw      r6,r1,r0
92
        lhu     r7,r1,r0
93
        shi     r7,r0, 0xa              # [imm for exception]
94
        shi     r6,r0, 0xe              # [lower half for exception ]
95
 
96
/*      Set Interrupt Handler */
97
        la      r6,r0,_interrupt_handler
98
        sw      r6,r1,r0
99
        lhu     r7,r1,r0
100
        shi     r7,r0, 0x12             # [imm for exception]
101
        shi     r6,r0, 0x16             # [lower half for intterupt ]
102
 
103
/*      Set HW Exception Handler */
104
        la      r6,r0,_hw_exception_handler
105
        sw      r6,r1,r0
106
        lhu     r7,r1,r0
107
        shi     r7,r0, 0x22             # [imm for exception]
108
        shi     r6,r0, 0x26             # [lower half for hw exception]
109
 
110
/*      initialize bss sections                           */
111
        brlid   r15,_crtinit
112
        nop
113
 
114
/*      Adjust the stack pointer                          */
115
        addi    r1,r1,16
116
 
117
/*      Fall through to exit                              */
118
        .end _start
119
 
120
/*      Use this exit function                            */
121
        .globl exit                  # exit library call
122
        .ent exit
123
exit:
124
        bri     exit
125
        .end exit
126
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.