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584 |
jeremybenn |
############################################################################
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## This system.ucf file is generated by Base System Builder based on the
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## settings in the selected Xilinx Board Definition file. Please add other
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## user constraints to this file based on customer design specifications.
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############################################################################
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Net sys_clk_pin LOC=AE14;
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Net sys_clk_pin IOSTANDARD = LVCMOS33;
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Net sys_rst_pin LOC=D6;
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Net sys_rst_pin PULLUP;
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## System level constraints
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Net sys_clk_pin TNM_NET = sys_clk_pin;
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TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
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Net sys_rst_pin TIG;
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## FPGA pin constraints
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Net fpga_0_RS232_Uart_RX_pin LOC=W2;
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Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33;
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Net fpga_0_RS232_Uart_TX_pin LOC=W1;
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Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG;
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