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jeremybenn |
/*
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FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
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***************************************************************************
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* *
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* If you are: *
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* *
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* + New to FreeRTOS, *
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* + Wanting to learn FreeRTOS or multitasking in general quickly *
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* + Looking for basic training, *
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* + Wanting to improve your FreeRTOS skills and productivity *
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* *
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* then take a look at the FreeRTOS books - available as PDF or paperback *
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* *
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* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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* http://www.FreeRTOS.org/Documentation *
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* *
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* A pdf reference manual is also available. Both are usually delivered *
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* to your inbox within 20 minutes to two hours when purchased between 8am *
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* and 8pm GMT (although please allow up to 24 hours in case of *
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* exceptional circumstances). Thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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***NOTE*** The exception to the GPL is included to allow you to distribute
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a combined work that includes FreeRTOS without being obliged to provide the
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source code for proprietary components outside of the FreeRTOS kernel.
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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/*
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BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "queue.h"
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#include "task.h"
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/* Demo application includes. */
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#include "serial.h"
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/* Microblaze driver includes. */
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#include "xuartlite_l.h"
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#include "xintc_l.h"
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/*-----------------------------------------------------------*/
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/* Queues used to hold received characters, and characters waiting to be
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transmitted. */
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static xQueueHandle xRxedChars;
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static xQueueHandle xCharsForTx;
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/*-----------------------------------------------------------*/
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xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
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{
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unsigned long ulControlReg, ulMask;
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/* NOTE: The baud rate used by this driver is determined by the hardware
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parameterization of the UART Lite peripheral, and the baud value passed to
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this function has no effect. */
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/* Create the queues used to hold Rx and Tx characters. */
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xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
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xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
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if( ( xRxedChars ) && ( xCharsForTx ) )
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{
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/* Disable the interrupt. */
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XUartLite_mDisableIntr( XPAR_RS232_UART_BASEADDR );
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/* Flush the fifos. */
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ulControlReg = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
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XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_CONTROL_REG_OFFSET, ulControlReg | XUL_CR_FIFO_TX_RESET | XUL_CR_FIFO_RX_RESET );
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/* Enable the interrupt again. The interrupt controller has not yet been
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initialised so there is no chance of receiving an interrupt until the
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scheduler has been started. */
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XUartLite_mEnableIntr( XPAR_RS232_UART_BASEADDR );
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/* Enable the interrupt in the interrupt controller while maintaining
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all the other bit settings. */
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ulMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
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ulMask |= XPAR_RS232_UART_INTERRUPT_MASK;
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XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( ulMask ) );
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XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 2 );
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}
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return ( xComPortHandle ) 0;
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}
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/*-----------------------------------------------------------*/
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signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )
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{
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/* The port handle is not required as this driver only supports one UART. */
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( void ) pxPort;
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/* Get the next character from the buffer. Return false if no characters
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are available, or arrive before xBlockTime expires. */
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if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
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{
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return pdTRUE;
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}
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else
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{
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return pdFALSE;
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}
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}
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/*-----------------------------------------------------------*/
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signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )
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{
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portBASE_TYPE xReturn = pdTRUE;
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portENTER_CRITICAL();
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{
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/* If the UART FIFO is full we can block posting the new data on the
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Tx queue. */
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if( XUartLite_mIsTransmitFull( XPAR_RS232_UART_BASEADDR ) )
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{
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if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
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{
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xReturn = pdFAIL;
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}
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}
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/* Otherwise, if there is data already in the queue we should add the
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new data to the back of the queue to ensure the sequencing is
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maintained. */
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else if( uxQueueMessagesWaiting( xCharsForTx ) )
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{
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if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
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{
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xReturn = pdFAIL;
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}
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}
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/* If the UART FIFO is not full and there is no data already in the
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queue we can write directly to the FIFO without disrupting the
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sequence. */
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else
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{
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XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cOutChar );
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}
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}
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portEXIT_CRITICAL();
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return xReturn;
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}
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/*-----------------------------------------------------------*/
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void vSerialClose( xComPortHandle xPort )
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{
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/* Not supported as not required by the demo application. */
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( void ) xPort;
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}
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/*-----------------------------------------------------------*/
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void vSerialISR( void *pvBaseAddress )
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{
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unsigned long ulISRStatus;
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portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
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char cChar;
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/* Determine the cause of the interrupt. */
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ulISRStatus = XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_STATUS_REG_OFFSET );
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if( ( ulISRStatus & ( XUL_SR_RX_FIFO_FULL | XUL_SR_RX_FIFO_VALID_DATA ) ) != 0 )
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{
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/* A character is available - place it in the queue of received
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characters. This might wake a task that was blocked waiting for
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data. */
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cChar = ( char )XIo_In32( XPAR_RS232_UART_BASEADDR + XUL_RX_FIFO_OFFSET );
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xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
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}
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if( ( ulISRStatus & XUL_SR_TX_FIFO_EMPTY ) != 0 )
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{
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/* There is space in the FIFO - if there are any characters queue for
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transmission they can be send to the UART now. This might unblock a
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task that was waiting for space to become available on the Tx queue. */
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if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
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{
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XIo_Out32( XPAR_RS232_UART_BASEADDR + XUL_TX_FIFO_OFFSET, cChar );
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}
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}
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/* If we woke any tasks we may require a context switch. */
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if( xHigherPriorityTaskWoken )
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{
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portYIELD_FROM_ISR();
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}
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}
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