OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [MicroBlaze/] [system.mhs] - Blame information for rev 615

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 584 jeremybenn
# ##############################################################################
2
# Created by Base System Builder Wizard for Xilinx EDK 7.1.2 Build EDK_H.12.5.1
3
# Sun Nov 13 16:46:19 2005
4
# Target Board:  Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
5
# Family:        virtex4
6
# Device:        xc4vfx12
7
# Package:       ff668
8
# Speed Grade:   -10
9
# Processor: Microblaze
10
# System clock frequency: 100.000000 MHz
11
# Debug interface: On-Chip HW Debug Module
12
# On Chip Memory :  64 KB
13
# ##############################################################################
14
 
15
 
16
 PARAMETER VERSION = 2.1.0
17
 
18
 
19
 PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = INPUT
20
 PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = OUTPUT
21
 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = INOUT, VEC = [0:3]
22
 PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = INOUT, VEC = [0:4]
23
 PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = DCMCLK
24
 PORT sys_rst_pin = sys_rst_s, DIR = INPUT
25
 
26
 
27
BEGIN microblaze
28
 PARAMETER INSTANCE = microblaze_0
29
 PARAMETER HW_VER = 4.00.a
30
 PARAMETER C_DEBUG_ENABLED = 1
31
 PARAMETER C_NUMBER_OF_PC_BRK = 2
32
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 1
33
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 1
34
 BUS_INTERFACE DLMB = dlmb
35
 BUS_INTERFACE ILMB = ilmb
36
 BUS_INTERFACE DOPB = mb_opb
37
 BUS_INTERFACE IOPB = mb_opb
38
 PORT CLK = sys_clk_s
39
 PORT DBG_CAPTURE = DBG_CAPTURE_s
40
 PORT DBG_CLK = DBG_CLK_s
41
 PORT DBG_REG_EN = DBG_REG_EN_s
42
 PORT DBG_TDI = DBG_TDI_s
43
 PORT DBG_TDO = DBG_TDO_s
44
 PORT DBG_UPDATE = DBG_UPDATE_s
45
 PORT Interrupt = Interrupt
46
END
47
 
48
BEGIN opb_v20
49
 PARAMETER INSTANCE = mb_opb
50
 PARAMETER HW_VER = 1.10.c
51
 PARAMETER C_EXT_RESET_HIGH = 0
52
 PORT SYS_Rst = sys_rst_s
53
 PORT OPB_Clk = sys_clk_s
54
END
55
 
56
BEGIN opb_mdm
57
 PARAMETER INSTANCE = debug_module
58
 PARAMETER HW_VER = 2.00.a
59
 PARAMETER C_MB_DBG_PORTS = 1
60
 PARAMETER C_USE_UART = 1
61
 PARAMETER C_UART_WIDTH = 8
62
 PARAMETER C_BASEADDR = 0x41400000
63
 PARAMETER C_HIGHADDR = 0x4140ffff
64
 BUS_INTERFACE SOPB = mb_opb
65
 PORT OPB_Clk = sys_clk_s
66
 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
67
 PORT DBG_CLK_0 = DBG_CLK_s
68
 PORT DBG_REG_EN_0 = DBG_REG_EN_s
69
 PORT DBG_TDI_0 = DBG_TDI_s
70
 PORT DBG_TDO_0 = DBG_TDO_s
71
 PORT DBG_UPDATE_0 = DBG_UPDATE_s
72
END
73
 
74
BEGIN lmb_v10
75
 PARAMETER INSTANCE = ilmb
76
 PARAMETER HW_VER = 1.00.a
77
 PARAMETER C_EXT_RESET_HIGH = 0
78
 PORT SYS_Rst = sys_rst_s
79
 PORT LMB_Clk = sys_clk_s
80
END
81
 
82
BEGIN lmb_v10
83
 PARAMETER INSTANCE = dlmb
84
 PARAMETER HW_VER = 1.00.a
85
 PARAMETER C_EXT_RESET_HIGH = 0
86
 PORT SYS_Rst = sys_rst_s
87
 PORT LMB_Clk = sys_clk_s
88
END
89
 
90
BEGIN lmb_bram_if_cntlr
91
 PARAMETER INSTANCE = dlmb_cntlr
92
 PARAMETER HW_VER = 1.00.b
93
 PARAMETER C_BASEADDR = 0x00000000
94
 PARAMETER C_HIGHADDR = 0x0000ffff
95
 BUS_INTERFACE SLMB = dlmb
96
 BUS_INTERFACE BRAM_PORT = dlmb_port
97
END
98
 
99
BEGIN lmb_bram_if_cntlr
100
 PARAMETER INSTANCE = ilmb_cntlr
101
 PARAMETER HW_VER = 1.00.b
102
 PARAMETER C_BASEADDR = 0x00000000
103
 PARAMETER C_HIGHADDR = 0x0000ffff
104
 BUS_INTERFACE SLMB = ilmb
105
 BUS_INTERFACE BRAM_PORT = ilmb_port
106
END
107
 
108
BEGIN bram_block
109
 PARAMETER INSTANCE = lmb_bram
110
 PARAMETER HW_VER = 1.00.a
111
 BUS_INTERFACE PORTA = ilmb_port
112
 BUS_INTERFACE PORTB = dlmb_port
113
END
114
 
115
BEGIN opb_uartlite
116
 PARAMETER INSTANCE = RS232_Uart
117
 PARAMETER HW_VER = 1.00.b
118
 PARAMETER C_BAUDRATE = 9600
119
 PARAMETER C_DATA_BITS = 8
120
 PARAMETER C_ODD_PARITY = 0
121
 PARAMETER C_USE_PARITY = 0
122
 PARAMETER C_CLK_FREQ = 100000000
123
 PARAMETER C_BASEADDR = 0x40600000
124
 PARAMETER C_HIGHADDR = 0x4060ffff
125
 BUS_INTERFACE SOPB = mb_opb
126
 PORT OPB_Clk = sys_clk_s
127
 PORT Interrupt = RS232_Uart_Interrupt
128
 PORT RX = fpga_0_RS232_Uart_RX
129
 PORT TX = fpga_0_RS232_Uart_TX
130
END
131
 
132
BEGIN opb_gpio
133
 PARAMETER INSTANCE = LEDs_4Bit
134
 PARAMETER HW_VER = 3.01.b
135
 PARAMETER C_GPIO_WIDTH = 4
136
 PARAMETER C_IS_DUAL = 0
137
 PARAMETER C_IS_BIDIR = 1
138
 PARAMETER C_ALL_INPUTS = 0
139
 PARAMETER C_BASEADDR = 0x40020000
140
 PARAMETER C_HIGHADDR = 0x4002ffff
141
 BUS_INTERFACE SOPB = mb_opb
142
 PORT OPB_Clk = sys_clk_s
143
 PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
144
END
145
 
146
BEGIN opb_gpio
147
 PARAMETER INSTANCE = LEDs_Positions
148
 PARAMETER HW_VER = 3.01.b
149
 PARAMETER C_GPIO_WIDTH = 5
150
 PARAMETER C_IS_DUAL = 0
151
 PARAMETER C_IS_BIDIR = 1
152
 PARAMETER C_ALL_INPUTS = 0
153
 PARAMETER C_BASEADDR = 0x40000000
154
 PARAMETER C_HIGHADDR = 0x4000ffff
155
 BUS_INTERFACE SOPB = mb_opb
156
 PORT OPB_Clk = sys_clk_s
157
 PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO
158
END
159
 
160
BEGIN opb_timer
161
 PARAMETER INSTANCE = opb_timer_1
162
 PARAMETER HW_VER = 1.00.b
163
 PARAMETER C_COUNT_WIDTH = 32
164
 PARAMETER C_ONE_TIMER_ONLY = 1
165
 PARAMETER C_BASEADDR = 0x41c00000
166
 PARAMETER C_HIGHADDR = 0x41c0ffff
167
 BUS_INTERFACE SOPB = mb_opb
168
 PORT OPB_Clk = sys_clk_s
169
 PORT Interrupt = opb_timer_1_Interrupt
170
END
171
 
172
BEGIN opb_intc
173
 PARAMETER INSTANCE = opb_intc_0
174
 PARAMETER HW_VER = 1.00.c
175
 PARAMETER C_BASEADDR = 0x41200000
176
 PARAMETER C_HIGHADDR = 0x4120ffff
177
 PARAMETER C_HAS_IPR = 0
178
 BUS_INTERFACE SOPB = mb_opb
179
 PORT Irq = Interrupt
180
 PORT Intr = RS232_Uart_Interrupt & opb_timer_1_Interrupt
181
END
182
 
183
BEGIN dcm_module
184
 PARAMETER INSTANCE = dcm_0
185
 PARAMETER HW_VER = 1.00.a
186
 PARAMETER C_CLK0_BUF = TRUE
187
 PARAMETER C_CLKIN_PERIOD = 10.000000
188
 PARAMETER C_CLK_FEEDBACK = 1X
189
 PARAMETER C_EXT_RESET_HIGH = 1
190
 PORT CLKIN = dcm_clk_s
191
 PORT CLK0 = sys_clk_s
192
 PORT CLKFB = sys_clk_s
193
 PORT RST = net_gnd
194
 PORT LOCKED = dcm_0_lock
195
END
196
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.