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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [NiosII_CycloneIII_DBC3C40_GCC/] [cpu.ptf] - Blame information for rev 825

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Line No. Rev Author Line
1 584 jeremybenn
SYSTEM cpu
2
{
3
   System_Wizard_Version = "8.00";
4
   System_Wizard_Build = "215";
5
   Builder_Application = "sopc_builder_ca";
6
   WIZARD_SCRIPT_ARGUMENTS
7
   {
8
      hdl_language = "vhdl";
9
      device_family = "CYCLONEIII";
10
      device_family_id = "CYCLONEIII";
11
      generate_sdk = "0";
12
      do_build_sim = "0";
13
      hardcopy_compatible = "0";
14
      CLOCKS
15
      {
16
         CLOCK clk
17
         {
18
            frequency = "75000000";
19
            source = "External";
20
            Is_Clock_Source = "0";
21
            display_name = "clk";
22
            pipeline = "0";
23
            clock_module_connection_point_for_c2h = "clk.clk";
24
         }
25
      }
26
      clock_freq = "75000000";
27
      clock_freq = "75000000";
28
      board_class = "";
29
      view_master_columns = "1";
30
      view_master_priorities = "0";
31
      generate_hdl = "";
32
      bustype_column_width = "0";
33
      clock_column_width = "80";
34
      name_column_width = "75";
35
      desc_column_width = "75";
36
      base_column_width = "75";
37
      end_column_width = "75";
38
      BOARD_INFO
39
      {
40
         altera_avalon_epcs_flash_controller
41
         {
42
            reference_designators = "";
43
         }
44
         altera_avalon_cfi_flash
45
         {
46
            reference_designators = "";
47
         }
48
      }
49
      do_log_history = "0";
50
   }
51
   MODULE cpu_0
52
   {
53
      MASTER instruction_master
54
      {
55
         PORT_WIRING
56
         {
57
            PORT clk
58
            {
59
               type = "clk";
60
               width = "1";
61
               direction = "input";
62
               Is_Enabled = "1";
63
            }
64
            PORT reset_n
65
            {
66
               type = "reset_n";
67
               width = "1";
68
               direction = "input";
69
               Is_Enabled = "0";
70
            }
71
            PORT i_address
72
            {
73
               type = "address";
74
               width = "25";
75
               direction = "output";
76
               Is_Enabled = "1";
77
            }
78
            PORT i_read
79
            {
80
               type = "read";
81
               width = "1";
82
               direction = "output";
83
               Is_Enabled = "1";
84
            }
85
            PORT i_readdata
86
            {
87
               type = "readdata";
88
               width = "32";
89
               direction = "input";
90
               Is_Enabled = "1";
91
            }
92
            PORT i_readdatavalid
93
            {
94
               type = "readdatavalid";
95
               width = "1";
96
               direction = "input";
97
               Is_Enabled = "1";
98
            }
99
            PORT i_waitrequest
100
            {
101
               type = "waitrequest";
102
               width = "1";
103
               direction = "input";
104
               Is_Enabled = "1";
105
            }
106
         }
107
         SYSTEM_BUILDER_INFO
108
         {
109
            Bus_Type = "avalon";
110
            Is_Asynchronous = "0";
111
            DBS_Big_Endian = "0";
112
            Adapts_To = "";
113
            Do_Stream_Reads = "0";
114
            Do_Stream_Writes = "0";
115
            Max_Address_Width = "32";
116
            Data_Width = "32";
117
            Address_Width = "25";
118
            Maximum_Burst_Size = "1";
119
            Register_Incoming_Signals = "0";
120
            Register_Outgoing_Signals = "0";
121
            Interleave_Bursts = "";
122
            Linewrap_Bursts = "";
123
            Burst_On_Burst_Boundaries_Only = "";
124
            Always_Burst_Max_Burst = "";
125
            Is_Big_Endian = "0";
126
            Is_Enabled = "1";
127
            Is_Instruction_Master = "1";
128
            Is_Readable = "1";
129
            Is_Writeable = "0";
130
            Address_Group = "0";
131
            Has_IRQ = "0";
132
            Irq_Scheme = "individual_requests";
133
            Interrupt_Range = "0-0";
134
         }
135
         MEMORY_MAP
136
         {
137
            Entry cpu_0/jtag_debug_module
138
            {
139
               address = "0x00901800";
140
               span = "0x00000800";
141
               is_bridge = "0";
142
            }
143
            Entry onchip_memory/s1
144
            {
145
               address = "0x00904000";
146
               span = "0x00002000";
147
               is_bridge = "0";
148
            }
149
            Entry sdram/s1
150
            {
151
               address = "0x01000000";
152
               span = "0x01000000";
153
               is_bridge = "0";
154
            }
155
            Entry epcs_controller/epcs_control_port
156
            {
157
               address = "0x00906000";
158
               span = "0x00000800";
159
               is_bridge = "0";
160
            }
161
            Entry cfi_flash/s1
162
            {
163
               address = "0x00000000";
164
               span = "0x00800000";
165
               is_bridge = "0";
166
            }
167
            Entry DBC3C40_SRAM_inst/avalon_tristate_slave
168
            {
169
               address = "0x00800000";
170
               span = "0x00100000";
171
               is_bridge = "0";
172
            }
173
         }
174
      }
175
      MASTER custom_instruction_master
176
      {
177
         SYSTEM_BUILDER_INFO
178
         {
179
            Bus_Type = "nios_custom_instruction";
180
            Data_Width = "32";
181
            Address_Width = "8";
182
            Is_Custom_Instruction = "1";
183
            Is_Enabled = "0";
184
            Max_Address_Width = "8";
185
            Base_Address = "N/A";
186
            Is_Visible = "0";
187
         }
188
         PORT_WIRING
189
         {
190
            PORT dataa
191
            {
192
               type = "dataa";
193
               width = "32";
194
               direction = "output";
195
            }
196
            PORT datab
197
            {
198
               type = "datab";
199
               width = "32";
200
               direction = "output";
201
            }
202
            PORT result
203
            {
204
               type = "result";
205
               width = "32";
206
               direction = "input";
207
            }
208
            PORT clk_en
209
            {
210
               type = "clk_en";
211
               width = "1";
212
               direction = "output";
213
            }
214
            PORT reset
215
            {
216
               type = "reset";
217
               width = "1";
218
               direction = "output";
219
            }
220
            PORT start
221
            {
222
               type = "start";
223
               width = "1";
224
               direction = "output";
225
            }
226
            PORT done
227
            {
228
               type = "done";
229
               width = "1";
230
               direction = "input";
231
            }
232
            PORT n
233
            {
234
               type = "n";
235
               width = "8";
236
               direction = "output";
237
            }
238
            PORT a
239
            {
240
               type = "a";
241
               width = "5";
242
               direction = "output";
243
            }
244
            PORT b
245
            {
246
               type = "b";
247
               width = "5";
248
               direction = "output";
249
            }
250
            PORT c
251
            {
252
               type = "c";
253
               width = "5";
254
               direction = "output";
255
            }
256
            PORT readra
257
            {
258
               type = "readra";
259
               width = "1";
260
               direction = "output";
261
            }
262
            PORT readrb
263
            {
264
               type = "readrb";
265
               width = "1";
266
               direction = "output";
267
            }
268
            PORT writerc
269
            {
270
               type = "writerc";
271
               width = "1";
272
               direction = "output";
273
            }
274
         }
275
      }
276
      SLAVE jtag_debug_module
277
      {
278
         SYSTEM_BUILDER_INFO
279
         {
280
            Bus_Type = "avalon";
281
            Write_Wait_States = "0cycles";
282
            Read_Wait_States = "1cycles";
283
            Hold_Time = "0cycles";
284
            Setup_Time = "0cycles";
285
            Is_Printable_Device = "0";
286
            Address_Alignment = "dynamic";
287
            Well_Behaved_Waitrequest = "0";
288
            Is_Nonvolatile_Storage = "0";
289
            Address_Span = "2048";
290
            Read_Latency = "0";
291
            Is_Memory_Device = "1";
292
            Maximum_Pending_Read_Transactions = "0";
293
            Minimum_Uninterrupted_Run_Length = "1";
294
            Accepts_Internal_Connections = "1";
295
            Write_Latency = "0";
296
            Is_Flash = "0";
297
            Data_Width = "32";
298
            Address_Width = "9";
299
            Maximum_Burst_Size = "1";
300
            Register_Incoming_Signals = "0";
301
            Register_Outgoing_Signals = "0";
302
            Interleave_Bursts = "0";
303
            Linewrap_Bursts = "0";
304
            Burst_On_Burst_Boundaries_Only = "0";
305
            Always_Burst_Max_Burst = "0";
306
            Is_Big_Endian = "0";
307
            Is_Enabled = "1";
308
            Accepts_External_Connections = "1";
309
            Requires_Internal_Connections = "";
310
            MASTERED_BY cpu_0/instruction_master
311
            {
312
               priority = "1";
313
               Offset_Address = "0x00901800";
314
            }
315
            MASTERED_BY cpu_0/data_master
316
            {
317
               priority = "1";
318
               Offset_Address = "0x00901800";
319
            }
320
            Base_Address = "0x00901800";
321
            Is_Readable = "1";
322
            Is_Writeable = "1";
323
            Uses_Tri_State_Data_Bus = "0";
324
            Has_IRQ = "0";
325
            JTAG_Hub_Base_Id = "1118278";
326
            JTAG_Hub_Instance_Id = "0";
327
            Address_Group = "0";
328
            IRQ_MASTER cpu_0/data_master
329
            {
330
               IRQ_Number = "NC";
331
            }
332
         }
333
         PORT_WIRING
334
         {
335
            PORT jtag_debug_module_address
336
            {
337
               type = "address";
338
               width = "9";
339
               direction = "input";
340
               Is_Enabled = "1";
341
            }
342
            PORT jtag_debug_module_begintransfer
343
            {
344
               type = "begintransfer";
345
               width = "1";
346
               direction = "input";
347
               Is_Enabled = "1";
348
            }
349
            PORT jtag_debug_module_byteenable
350
            {
351
               type = "byteenable";
352
               width = "4";
353
               direction = "input";
354
               Is_Enabled = "1";
355
            }
356
            PORT jtag_debug_module_clk
357
            {
358
               type = "clk";
359
               width = "1";
360
               direction = "input";
361
               Is_Enabled = "1";
362
            }
363
            PORT jtag_debug_module_debugaccess
364
            {
365
               type = "debugaccess";
366
               width = "1";
367
               direction = "input";
368
               Is_Enabled = "1";
369
            }
370
            PORT jtag_debug_module_readdata
371
            {
372
               type = "readdata";
373
               width = "32";
374
               direction = "output";
375
               Is_Enabled = "1";
376
            }
377
            PORT jtag_debug_module_reset
378
            {
379
               type = "reset";
380
               width = "1";
381
               direction = "input";
382
               Is_Enabled = "1";
383
            }
384
            PORT jtag_debug_module_resetrequest
385
            {
386
               type = "resetrequest";
387
               width = "1";
388
               direction = "output";
389
               Is_Enabled = "1";
390
            }
391
            PORT jtag_debug_module_select
392
            {
393
               type = "chipselect";
394
               width = "1";
395
               direction = "input";
396
               Is_Enabled = "1";
397
            }
398
            PORT jtag_debug_module_write
399
            {
400
               type = "write";
401
               width = "1";
402
               direction = "input";
403
               Is_Enabled = "1";
404
            }
405
            PORT jtag_debug_module_writedata
406
            {
407
               type = "writedata";
408
               width = "32";
409
               direction = "input";
410
               Is_Enabled = "1";
411
            }
412
            PORT reset_n
413
            {
414
               Is_Enabled = "1";
415
               direction = "input";
416
               type = "reset_n";
417
               width = "1";
418
            }
419
         }
420
      }
421
      MASTER data_master
422
      {
423
         SYSTEM_BUILDER_INFO
424
         {
425
            Has_IRQ = "1";
426
            Irq_Scheme = "individual_requests";
427
            Bus_Type = "avalon";
428
            Is_Asynchronous = "0";
429
            DBS_Big_Endian = "0";
430
            Adapts_To = "";
431
            Do_Stream_Reads = "0";
432
            Do_Stream_Writes = "0";
433
            Max_Address_Width = "32";
434
            Data_Width = "32";
435
            Address_Width = "25";
436
            Maximum_Burst_Size = "1";
437
            Register_Incoming_Signals = "1";
438
            Register_Outgoing_Signals = "0";
439
            Interleave_Bursts = "0";
440
            Linewrap_Bursts = "0";
441
            Burst_On_Burst_Boundaries_Only = "";
442
            Always_Burst_Max_Burst = "0";
443
            Is_Big_Endian = "0";
444
            Is_Enabled = "1";
445
            Is_Data_Master = "1";
446
            Address_Group = "0";
447
            Is_Readable = "1";
448
            Is_Writeable = "1";
449
            Interrupt_Range = "0-31";
450
         }
451
         PORT_WIRING
452
         {
453
            PORT d_irq
454
            {
455
               type = "irq";
456
               width = "32";
457
               direction = "input";
458
               Is_Enabled = "1";
459
            }
460
            PORT d_address
461
            {
462
               type = "address";
463
               width = "25";
464
               direction = "output";
465
               Is_Enabled = "1";
466
            }
467
            PORT d_byteenable
468
            {
469
               type = "byteenable";
470
               width = "4";
471
               direction = "output";
472
               Is_Enabled = "1";
473
            }
474
            PORT d_read
475
            {
476
               type = "read";
477
               width = "1";
478
               direction = "output";
479
               Is_Enabled = "1";
480
            }
481
            PORT d_readdata
482
            {
483
               type = "readdata";
484
               width = "32";
485
               direction = "input";
486
               Is_Enabled = "1";
487
            }
488
            PORT d_readdatavalid
489
            {
490
               type = "readdatavalid";
491
               width = "1";
492
               direction = "input";
493
               Is_Enabled = "0";
494
            }
495
            PORT d_waitrequest
496
            {
497
               type = "waitrequest";
498
               width = "1";
499
               direction = "input";
500
               Is_Enabled = "1";
501
            }
502
            PORT d_write
503
            {
504
               type = "write";
505
               width = "1";
506
               direction = "output";
507
               Is_Enabled = "1";
508
            }
509
            PORT d_writedata
510
            {
511
               type = "writedata";
512
               width = "32";
513
               direction = "output";
514
               Is_Enabled = "1";
515
            }
516
            PORT jtag_debug_module_debugaccess_to_roms
517
            {
518
               type = "debugaccess";
519
               width = "1";
520
               direction = "output";
521
               Is_Enabled = "1";
522
            }
523
         }
524
         MEMORY_MAP
525
         {
526
            Entry cpu_0/jtag_debug_module
527
            {
528
               address = "0x00901800";
529
               span = "0x00000800";
530
               is_bridge = "0";
531
            }
532
            Entry onchip_memory/s1
533
            {
534
               address = "0x00904000";
535
               span = "0x00002000";
536
               is_bridge = "0";
537
            }
538
            Entry jtag_uart_0/avalon_jtag_slave
539
            {
540
               address = "0x009000d0";
541
               span = "0x00000008";
542
               is_bridge = "0";
543
            }
544
            Entry sdram/s1
545
            {
546
               address = "0x01000000";
547
               span = "0x01000000";
548
               is_bridge = "0";
549
            }
550
            Entry sysid/control_slave
551
            {
552
               address = "0x009000d8";
553
               span = "0x00000008";
554
               is_bridge = "0";
555
            }
556
            Entry LED_Pio/s1
557
            {
558
               address = "0x00900080";
559
               span = "0x00000010";
560
               is_bridge = "0";
561
            }
562
            Entry SG_Pio/s1
563
            {
564
               address = "0x00900090";
565
               span = "0x00000010";
566
               is_bridge = "0";
567
            }
568
            Entry IO_Pio/s1
569
            {
570
               address = "0x009000a0";
571
               span = "0x00000010";
572
               is_bridge = "0";
573
            }
574
            Entry Button_Pio/s1
575
            {
576
               address = "0x009000b0";
577
               span = "0x00000010";
578
               is_bridge = "0";
579
            }
580
            Entry uart/s1
581
            {
582
               address = "0x00900040";
583
               span = "0x00000020";
584
               is_bridge = "0";
585
            }
586
            Entry LM74_Pio/s1
587
            {
588
               address = "0x009000c0";
589
               span = "0x00000010";
590
               is_bridge = "0";
591
            }
592
            Entry epcs_controller/epcs_control_port
593
            {
594
               address = "0x00906000";
595
               span = "0x00000800";
596
               is_bridge = "0";
597
            }
598
            Entry cfi_flash/s1
599
            {
600
               address = "0x00000000";
601
               span = "0x00800000";
602
               is_bridge = "0";
603
            }
604
            Entry DBC3C40_SRAM_inst/avalon_tristate_slave
605
            {
606
               address = "0x00800000";
607
               span = "0x00100000";
608
               is_bridge = "0";
609
            }
610
            Entry sys_clk/s1
611
            {
612
               address = "0x00900060";
613
               span = "0x00000020";
614
               is_bridge = "0";
615
            }
616
            Entry nios_vga_inst/vga_regs
617
            {
618
               address = "0x00900000";
619
               span = "0x00000040";
620
               is_bridge = "0";
621
            }
622
         }
623
      }
624
      WIZARD_SCRIPT_ARGUMENTS
625
      {
626
         cache_has_dcache = "0";
627
         cache_dcache_size = "0";
628
         cache_dcache_line_size = "0";
629
         cache_dcache_bursts = "0";
630
         cache_dcache_ram_block_type = "AUTO";
631
         num_tightly_coupled_data_masters = "0";
632
         gui_num_tightly_coupled_data_masters = "0";
633
         gui_include_tightly_coupled_data_masters = "0";
634
         gui_omit_avalon_data_master = "0";
635
         cache_has_icache = "1";
636
         cache_icache_size = "16384";
637
         cache_icache_line_size = "32";
638
         cache_icache_ram_block_type = "AUTO";
639
         cache_icache_bursts = "0";
640
         num_tightly_coupled_instruction_masters = "0";
641
         gui_num_tightly_coupled_instruction_masters = "0";
642
         gui_include_tightly_coupled_instruction_masters = "0";
643
         debug_level = "3";
644
         include_oci = "1";
645
         oci_sbi_enabled = "1";
646
         oci_num_xbrk = "2";
647
         oci_num_dbrk = "2";
648
         oci_dbrk_trace = "0";
649
         oci_dbrk_pairs = "1";
650
         oci_onchip_trace = "0";
651
         oci_offchip_trace = "0";
652
         oci_data_trace = "0";
653
         include_third_party_debug_port = "0";
654
         oci_trace_addr_width = "7";
655
         oci_trigger_arming = "1";
656
         oci_debugreq_signals = "0";
657
         oci_embedded_pll = "0";
658
         oci_num_pm = "0";
659
         oci_pm_width = "32";
660
         performance_counters_present = "0";
661
         performance_counters_width = "32";
662
         always_encrypt = "1";
663
         debug_simgen = "0";
664
         activate_model_checker = "0";
665
         activate_test_end_checker = "0";
666
         activate_trace = "1";
667
         activate_monitors = "1";
668
         clear_x_bits_ld_non_bypass = "1";
669
         bit_31_bypass_dcache = "1";
670
         hdl_sim_caches_cleared = "1";
671
         hbreak_test = "0";
672
         allow_full_address_range = "0";
673
         extra_exc_info = "0";
674
         branch_prediction_type = "Static";
675
         bht_ptr_sz = "8";
676
         bht_index_pc_only = "0";
677
         gui_branch_prediction_type = "Static";
678
         full_waveform_signals = "0";
679
         export_pcb = "0";
680
         avalon_debug_port_present = "0";
681
         illegal_instructions_trap = "0";
682
         illegal_memory_access_detection = "0";
683
         illegal_mem_exc = "0";
684
         slave_access_error_exc = "0";
685
         division_error_exc = "0";
686
         advanced_exc = "0";
687
         gui_mmu_present = "0";
688
         mmu_present = "0";
689
         process_id_num_bits = "8";
690
         tlb_ptr_sz = "7";
691
         tlb_num_ways = "16";
692
         udtlb_num_entries = "6";
693
         uitlb_num_entries = "4";
694
         fast_tlb_miss_exc_slave = "";
695
         fast_tlb_miss_exc_offset = "0x00000000";
696
         mpu_present = "0";
697
         mpu_num_data_regions = "8";
698
         mpu_num_inst_regions = "8";
699
         mpu_min_data_region_size_log2 = "12";
700
         mpu_min_inst_region_size_log2 = "12";
701
         mpu_use_limit = "0";
702
         hardware_divide_present = "0";
703
         gui_hardware_divide_setting = "0";
704
         hardware_multiply_present = "1";
705
         hardware_multiply_impl = "embedded_mul";
706
         shift_rot_impl = "fast_le_shift";
707
         gui_hardware_multiply_setting = "embedded_mul_fast_le_shift";
708
         reset_slave = "cfi_flash/s1";
709
         break_slave = "cpu_0/jtag_debug_module";
710
         exc_slave = "sdram/s1";
711
         reset_offset = "0x00000000";
712
         break_offset = "0x00000020";
713
         exc_offset = "0x00000020";
714
         cpu_reset = "0";
715
         CPU_Implementation = "small";
716
         cpu_selection = "s";
717
         device_family_id = "CYCLONEIII";
718
         address_stall_present = "1";
719
         dsp_block_supports_shift = "0";
720
         mrams_present = "0";
721
         do_generate = "1";
722
         cpuid_value = "0";
723
         cpuid_sz = "1";
724
         dont_overwrite_cpuid = "1";
725
         allow_legacy_sdk = "1";
726
         legacy_sdk_support = "1";
727
         inst_addr_width = "25";
728
         data_addr_width = "25";
729
         asp_debug = "0";
730
         asp_core_debug = "0";
731
         CPU_Architecture = "nios2";
732
         cache_icache_burst_type = "none";
733
         include_debug = "0";
734
         include_trace = "0";
735
         hardware_multiply_uses_les = "0";
736
         hardware_multiply_omits_msw = "1";
737
         big_endian = "0";
738
         break_slave_override = "";
739
         break_offset_override = "0x20";
740
         altera_show_unreleased_features = "0";
741
         altera_show_unpublished_features = "0";
742
         altera_internal_test = "0";
743
         alt_log_port_base = "";
744
         alt_log_port_type = "";
745
         gui_illegal_instructions_trap = "0";
746
         atomic_mem_present = "0";
747
         nmi_present = "0";
748
         fast_intr_present = "0";
749
         num_shadow_regs = "0";
750
         gui_illegal_memory_access_detection = "0";
751
         cache_omit_dcache = "0";
752
         cache_omit_icache = "0";
753
         omit_instruction_master = "0";
754
         omit_data_master = "0";
755
         ras_ptr_sz = "4";
756
         jtb_ptr_sz = "5";
757
         ibuf_ptr_sz = "4";
758
         always_bypass_dcache = "0";
759
         iss_trace_on = "0";
760
         iss_trace_warning = "1";
761
         iss_trace_info = "1";
762
         iss_trace_disassembly = "0";
763
         iss_trace_registers = "0";
764
         iss_trace_instr_count = "0";
765
         iss_software_debug = "0";
766
         iss_software_debug_port = "9996";
767
         iss_memory_dump_start = "";
768
         iss_memory_dump_end = "";
769
         Boot_Copier = "boot_loader_cfi.srec";
770
         Boot_Copier_EPCS = "boot_loader_epcs.srec";
771
         Boot_Copier_EPCS_SII_SIII_CIII = "boot_loader_epcs_sii_siii_ciii.srec";
772
         Boot_Copier_BE = "boot_loader_cfi_be.srec";
773
         Boot_Copier_EPCS_BE = "boot_loader_epcs_be.srec";
774
         Boot_Copier_EPCS_SII_SIII_CIII_BE = "boot_loader_epcs_sii_siii_ciii_be.srec";
775
         CONSTANTS
776
         {
777
            CONSTANT __nios_catch_irqs__
778
            {
779
               value = "1";
780
               comment = "Include panic handler for all irqs (needs uart)";
781
            }
782
            CONSTANT __nios_use_constructors__
783
            {
784
               value = "1";
785
               comment = "Call c++ static constructors";
786
            }
787
            CONSTANT __nios_use_small_printf__
788
            {
789
               value = "1";
790
               comment = "Smaller non-ANSI printf, with no floating point";
791
            }
792
            CONSTANT nasys_has_icache
793
            {
794
               value = "1";
795
               comment = "True if instruction cache present";
796
            }
797
            CONSTANT nasys_icache_size
798
            {
799
               value = "16384";
800
               comment = "Size in bytes of instruction cache";
801
            }
802
            CONSTANT nasys_icache_line_size
803
            {
804
               value = "32";
805
               comment = "Size in bytes of each icache line";
806
            }
807
            CONSTANT nasys_icache_line_size_log2
808
            {
809
               value = "5";
810
               comment = "Log2 size in bytes of each icache line";
811
            }
812
            CONSTANT nasys_has_dcache
813
            {
814
               value = "0";
815
               comment = "True if instruction cache present";
816
            }
817
            CONSTANT nasys_dcache_size
818
            {
819
               value = "0";
820
               comment = "Size in bytes of data cache";
821
            }
822
            CONSTANT nasys_dcache_line_size
823
            {
824
               value = "0";
825
               comment = "Size in bytes of each dcache line";
826
            }
827
            CONSTANT nasys_dcache_line_size_log2
828
            {
829
               value = "-Infinity";
830
               comment = "Log2 size in bytes of each dcache line";
831
            }
832
         }
833
         license_status = "encrypted";
834
         mainmem_slave = "DBC3C40_SRAM_inst/avalon_tristate_slave";
835
         datamem_slave = "DBC3C40_SRAM_inst/avalon_tristate_slave";
836
         maincomm_slave = "uart/s1";
837
         germs_monitor_id = "";
838
      }
839
      class = "altera_nios2";
840
      class_version = "7.08";
841
      SYSTEM_BUILDER_INFO
842
      {
843
         Is_Enabled = "1";
844
         Clock_Source = "clk";
845
         Has_Clock = "1";
846
         Parameters_Signature = "";
847
         Is_CPU = "1";
848
         Instantiate_In_System_Module = "1";
849
         Required_Device_Family = "STRATIX,STRATIXGX,STRATIXII,STRATIXIIGX,STRATIXIIGXLITE,STRATIXIII,STRATIXIV,CYCLONE,CYCLONEII,CYCLONEIII";
850
         Default_Module_Name = "cpu";
851
         Top_Level_Ports_Are_Enumerated = "1";
852
         View
853
         {
854
            Settings_Summary = "Nios II/s
855
            
  16-Kbyte Instruction Cache
856
 
857
            
  JTAG Debug Module
858
            ";
859
            MESSAGES
860
            {
861
            }
862
         }
863
      }
864
      iss_model_name = "altera_nios2";
865
      HDL_INFO
866
      {
867
         PLI_Files = "";
868
         Precompiled_Simulation_Library_Files = "";
869
         Simulation_HDL_Files = "";
870
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_0_test_bench.vhd, __PROJECT_DIRECTORY__/cpu_0_mult_cell.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_tck.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_sysclk.vhd, __PROJECT_DIRECTORY__/cpu_0_jtag_debug_module_wrapper.vhd, __PROJECT_DIRECTORY__/cpu_0.vhd";
871
         Synthesis_Only_Files = "";
872
      }
873
      MASTER tightly_coupled_instruction_master_0
874
      {
875
         PORT_WIRING
876
         {
877
         }
878
         SYSTEM_BUILDER_INFO
879
         {
880
            Register_Incoming_Signals = "0";
881
            Bus_Type = "avalon";
882
            Data_Width = "32";
883
            Max_Address_Width = "31";
884
            Address_Width = "8";
885
            Is_Instruction_Master = "1";
886
            Has_IRQ = "0";
887
            Is_Enabled = "0";
888
            Is_Big_Endian = "0";
889
            Connection_Limit = "1";
890
            Is_Channel = "1";
891
         }
892
      }
893
      MASTER tightly_coupled_instruction_master_1
894
      {
895
         PORT_WIRING
896
         {
897
         }
898
         SYSTEM_BUILDER_INFO
899
         {
900
            Register_Incoming_Signals = "0";
901
            Bus_Type = "avalon";
902
            Data_Width = "32";
903
            Max_Address_Width = "31";
904
            Address_Width = "8";
905
            Address_Group = "0";
906
            Is_Instruction_Master = "1";
907
            Is_Readable = "1";
908
            Is_Writeable = "0";
909
            Has_IRQ = "0";
910
            Is_Enabled = "0";
911
            Is_Big_Endian = "0";
912
            Connection_Limit = "1";
913
            Is_Channel = "1";
914
         }
915
      }
916
      MASTER tightly_coupled_instruction_master_2
917
      {
918
         PORT_WIRING
919
         {
920
         }
921
         SYSTEM_BUILDER_INFO
922
         {
923
            Register_Incoming_Signals = "0";
924
            Bus_Type = "avalon";
925
            Data_Width = "32";
926
            Max_Address_Width = "31";
927
            Address_Width = "8";
928
            Address_Group = "0";
929
            Is_Instruction_Master = "1";
930
            Is_Readable = "1";
931
            Is_Writeable = "0";
932
            Has_IRQ = "0";
933
            Is_Enabled = "0";
934
            Is_Big_Endian = "0";
935
            Connection_Limit = "1";
936
            Is_Channel = "1";
937
         }
938
      }
939
      MASTER tightly_coupled_instruction_master_3
940
      {
941
         PORT_WIRING
942
         {
943
         }
944
         SYSTEM_BUILDER_INFO
945
         {
946
            Register_Incoming_Signals = "0";
947
            Bus_Type = "avalon";
948
            Data_Width = "32";
949
            Max_Address_Width = "31";
950
            Address_Width = "8";
951
            Address_Group = "0";
952
            Is_Instruction_Master = "1";
953
            Is_Readable = "1";
954
            Is_Writeable = "0";
955
            Has_IRQ = "0";
956
            Is_Enabled = "0";
957
            Is_Big_Endian = "0";
958
            Connection_Limit = "1";
959
            Is_Channel = "1";
960
         }
961
      }
962
      MASTER data_master2
963
      {
964
         PORT_WIRING
965
         {
966
         }
967
         SYSTEM_BUILDER_INFO
968
         {
969
            Register_Incoming_Signals = "1";
970
            Bus_Type = "avalon";
971
            Data_Width = "32";
972
            Max_Address_Width = "31";
973
            Address_Width = "8";
974
            Address_Group = "0";
975
            Is_Data_Master = "1";
976
            Is_Readable = "1";
977
            Is_Writeable = "1";
978
            Has_IRQ = "0";
979
            Is_Enabled = "0";
980
            Is_Big_Endian = "0";
981
         }
982
      }
983
      MASTER tightly_coupled_data_master_0
984
      {
985
         PORT_WIRING
986
         {
987
         }
988
         SYSTEM_BUILDER_INFO
989
         {
990
            Register_Incoming_Signals = "0";
991
            Bus_Type = "avalon";
992
            Data_Width = "32";
993
            Max_Address_Width = "31";
994
            Address_Width = "8";
995
            Address_Group = "0";
996
            Is_Data_Master = "1";
997
            Is_Readable = "1";
998
            Is_Writeable = "1";
999
            Has_IRQ = "0";
1000
            Is_Enabled = "0";
1001
            Is_Big_Endian = "0";
1002
            Connection_Limit = "1";
1003
            Is_Channel = "1";
1004
         }
1005
      }
1006
      MASTER tightly_coupled_data_master_1
1007
      {
1008
         PORT_WIRING
1009
         {
1010
         }
1011
         SYSTEM_BUILDER_INFO
1012
         {
1013
            Register_Incoming_Signals = "0";
1014
            Bus_Type = "avalon";
1015
            Data_Width = "32";
1016
            Max_Address_Width = "31";
1017
            Address_Width = "8";
1018
            Address_Group = "0";
1019
            Is_Data_Master = "1";
1020
            Is_Readable = "1";
1021
            Is_Writeable = "1";
1022
            Has_IRQ = "0";
1023
            Is_Enabled = "0";
1024
            Is_Big_Endian = "0";
1025
            Connection_Limit = "1";
1026
            Is_Channel = "1";
1027
         }
1028
      }
1029
      MASTER tightly_coupled_data_master_2
1030
      {
1031
         PORT_WIRING
1032
         {
1033
         }
1034
         SYSTEM_BUILDER_INFO
1035
         {
1036
            Register_Incoming_Signals = "0";
1037
            Bus_Type = "avalon";
1038
            Data_Width = "32";
1039
            Max_Address_Width = "31";
1040
            Address_Width = "8";
1041
            Address_Group = "0";
1042
            Is_Data_Master = "1";
1043
            Is_Readable = "1";
1044
            Is_Writeable = "1";
1045
            Has_IRQ = "0";
1046
            Is_Enabled = "0";
1047
            Is_Big_Endian = "0";
1048
            Connection_Limit = "1";
1049
            Is_Channel = "1";
1050
         }
1051
      }
1052
      MASTER tightly_coupled_data_master_3
1053
      {
1054
         PORT_WIRING
1055
         {
1056
         }
1057
         SYSTEM_BUILDER_INFO
1058
         {
1059
            Register_Incoming_Signals = "0";
1060
            Bus_Type = "avalon";
1061
            Data_Width = "32";
1062
            Max_Address_Width = "31";
1063
            Address_Width = "8";
1064
            Address_Group = "0";
1065
            Is_Data_Master = "1";
1066
            Is_Readable = "1";
1067
            Is_Writeable = "1";
1068
            Has_IRQ = "0";
1069
            Is_Enabled = "0";
1070
            Is_Big_Endian = "0";
1071
            Connection_Limit = "1";
1072
            Is_Channel = "1";
1073
         }
1074
      }
1075
      PORT_WIRING
1076
      {
1077
         PORT jtag_debug_trigout
1078
         {
1079
            width = "1";
1080
            direction = "output";
1081
            Is_Enabled = "0";
1082
         }
1083
         PORT jtag_debug_offchip_trace_clk
1084
         {
1085
            width = "1";
1086
            direction = "output";
1087
            Is_Enabled = "0";
1088
         }
1089
         PORT jtag_debug_offchip_trace_data
1090
         {
1091
            width = "18";
1092
            direction = "output";
1093
            Is_Enabled = "0";
1094
         }
1095
         PORT clkx2
1096
         {
1097
            width = "1";
1098
            direction = "input";
1099
            Is_Enabled = "0";
1100
            visible = "0";
1101
         }
1102
      }
1103
      SIMULATION
1104
      {
1105
         DISPLAY
1106
         {
1107
            SIGNAL aaa
1108
            {
1109
               format = "Logic";
1110
               name = "i_readdata";
1111
               radix = "hexadecimal";
1112
            }
1113
            SIGNAL aab
1114
            {
1115
               format = "Logic";
1116
               name = "i_readdatavalid";
1117
               radix = "hexadecimal";
1118
            }
1119
            SIGNAL aac
1120
            {
1121
               format = "Logic";
1122
               name = "i_waitrequest";
1123
               radix = "hexadecimal";
1124
            }
1125
            SIGNAL aad
1126
            {
1127
               format = "Logic";
1128
               name = "i_address";
1129
               radix = "hexadecimal";
1130
            }
1131
            SIGNAL aae
1132
            {
1133
               format = "Logic";
1134
               name = "i_read";
1135
               radix = "hexadecimal";
1136
            }
1137
            SIGNAL aaf
1138
            {
1139
               format = "Logic";
1140
               name = "clk";
1141
               radix = "hexadecimal";
1142
            }
1143
            SIGNAL aag
1144
            {
1145
               format = "Logic";
1146
               name = "reset_n";
1147
               radix = "hexadecimal";
1148
            }
1149
            SIGNAL aah
1150
            {
1151
               format = "Logic";
1152
               name = "d_readdata";
1153
               radix = "hexadecimal";
1154
            }
1155
            SIGNAL aai
1156
            {
1157
               format = "Logic";
1158
               name = "d_waitrequest";
1159
               radix = "hexadecimal";
1160
            }
1161
            SIGNAL aaj
1162
            {
1163
               format = "Logic";
1164
               name = "d_irq";
1165
               radix = "hexadecimal";
1166
            }
1167
            SIGNAL aak
1168
            {
1169
               format = "Logic";
1170
               name = "d_address";
1171
               radix = "hexadecimal";
1172
            }
1173
            SIGNAL aal
1174
            {
1175
               format = "Logic";
1176
               name = "d_byteenable";
1177
               radix = "hexadecimal";
1178
            }
1179
            SIGNAL aam
1180
            {
1181
               format = "Logic";
1182
               name = "d_read";
1183
               radix = "hexadecimal";
1184
            }
1185
            SIGNAL aan
1186
            {
1187
               format = "Logic";
1188
               name = "d_write";
1189
               radix = "hexadecimal";
1190
            }
1191
            SIGNAL aao
1192
            {
1193
               format = "Logic";
1194
               name = "d_writedata";
1195
               radix = "hexadecimal";
1196
            }
1197
            SIGNAL aap
1198
            {
1199
               format = "Divider";
1200
               name = "base pipeline";
1201
               radix = "";
1202
            }
1203
            SIGNAL aaq
1204
            {
1205
               format = "Logic";
1206
               name = "clk";
1207
               radix = "hexadecimal";
1208
            }
1209
            SIGNAL aar
1210
            {
1211
               format = "Logic";
1212
               name = "reset_n";
1213
               radix = "hexadecimal";
1214
            }
1215
            SIGNAL aas
1216
            {
1217
               format = "Logic";
1218
               name = "M_stall";
1219
               radix = "hexadecimal";
1220
            }
1221
            SIGNAL aat
1222
            {
1223
               format = "Logic";
1224
               name = "F_pcb_nxt";
1225
               radix = "hexadecimal";
1226
            }
1227
            SIGNAL aau
1228
            {
1229
               format = "Logic";
1230
               name = "F_pcb";
1231
               radix = "hexadecimal";
1232
            }
1233
            SIGNAL aav
1234
            {
1235
               format = "Logic";
1236
               name = "D_pcb";
1237
               radix = "hexadecimal";
1238
            }
1239
            SIGNAL aaw
1240
            {
1241
               format = "Logic";
1242
               name = "E_pcb";
1243
               radix = "hexadecimal";
1244
            }
1245
            SIGNAL aax
1246
            {
1247
               format = "Logic";
1248
               name = "M_pcb";
1249
               radix = "hexadecimal";
1250
            }
1251
            SIGNAL aay
1252
            {
1253
               format = "Logic";
1254
               name = "W_pcb";
1255
               radix = "hexadecimal";
1256
            }
1257
            SIGNAL aaz
1258
            {
1259
               format = "Logic";
1260
               name = "F_vinst";
1261
               radix = "ascii";
1262
            }
1263
            SIGNAL aba
1264
            {
1265
               format = "Logic";
1266
               name = "D_vinst";
1267
               radix = "ascii";
1268
            }
1269
            SIGNAL abb
1270
            {
1271
               format = "Logic";
1272
               name = "E_vinst";
1273
               radix = "ascii";
1274
            }
1275
            SIGNAL abc
1276
            {
1277
               format = "Logic";
1278
               name = "M_vinst";
1279
               radix = "ascii";
1280
            }
1281
            SIGNAL abd
1282
            {
1283
               format = "Logic";
1284
               name = "W_vinst";
1285
               radix = "ascii";
1286
            }
1287
            SIGNAL abe
1288
            {
1289
               format = "Logic";
1290
               name = "F_inst_ram_hit";
1291
               radix = "hexadecimal";
1292
            }
1293
            SIGNAL abf
1294
            {
1295
               format = "Logic";
1296
               name = "F_issue";
1297
               radix = "hexadecimal";
1298
            }
1299
            SIGNAL abg
1300
            {
1301
               format = "Logic";
1302
               name = "F_kill";
1303
               radix = "hexadecimal";
1304
            }
1305
            SIGNAL abh
1306
            {
1307
               format = "Logic";
1308
               name = "D_kill";
1309
               radix = "hexadecimal";
1310
            }
1311
            SIGNAL abi
1312
            {
1313
               format = "Logic";
1314
               name = "D_refetch";
1315
               radix = "hexadecimal";
1316
            }
1317
            SIGNAL abj
1318
            {
1319
               format = "Logic";
1320
               name = "D_issue";
1321
               radix = "hexadecimal";
1322
            }
1323
            SIGNAL abk
1324
            {
1325
               format = "Logic";
1326
               name = "D_valid";
1327
               radix = "hexadecimal";
1328
            }
1329
            SIGNAL abl
1330
            {
1331
               format = "Logic";
1332
               name = "E_valid";
1333
               radix = "hexadecimal";
1334
            }
1335
            SIGNAL abm
1336
            {
1337
               format = "Logic";
1338
               name = "M_valid";
1339
               radix = "hexadecimal";
1340
            }
1341
            SIGNAL abn
1342
            {
1343
               format = "Logic";
1344
               name = "W_valid";
1345
               radix = "hexadecimal";
1346
            }
1347
            SIGNAL abo
1348
            {
1349
               format = "Logic";
1350
               name = "W_wr_dst_reg";
1351
               radix = "hexadecimal";
1352
            }
1353
            SIGNAL abp
1354
            {
1355
               format = "Logic";
1356
               name = "W_dst_regnum";
1357
               radix = "hexadecimal";
1358
            }
1359
            SIGNAL abq
1360
            {
1361
               format = "Logic";
1362
               name = "W_wr_data";
1363
               radix = "hexadecimal";
1364
            }
1365
            SIGNAL abr
1366
            {
1367
               format = "Logic";
1368
               name = "F_en";
1369
               radix = "hexadecimal";
1370
            }
1371
            SIGNAL abs
1372
            {
1373
               format = "Logic";
1374
               name = "D_en";
1375
               radix = "hexadecimal";
1376
            }
1377
            SIGNAL abt
1378
            {
1379
               format = "Logic";
1380
               name = "E_en";
1381
               radix = "hexadecimal";
1382
            }
1383
            SIGNAL abu
1384
            {
1385
               format = "Logic";
1386
               name = "M_en";
1387
               radix = "hexadecimal";
1388
            }
1389
            SIGNAL abv
1390
            {
1391
               format = "Logic";
1392
               name = "F_iw";
1393
               radix = "hexadecimal";
1394
            }
1395
            SIGNAL abw
1396
            {
1397
               format = "Logic";
1398
               name = "D_iw";
1399
               radix = "hexadecimal";
1400
            }
1401
            SIGNAL abx
1402
            {
1403
               format = "Logic";
1404
               name = "E_iw";
1405
               radix = "hexadecimal";
1406
            }
1407
            SIGNAL aby
1408
            {
1409
               format = "Logic";
1410
               name = "E_valid_prior_to_hbreak";
1411
               radix = "hexadecimal";
1412
            }
1413
            SIGNAL abz
1414
            {
1415
               format = "Logic";
1416
               name = "M_pipe_flush_nxt";
1417
               radix = "hexadecimal";
1418
            }
1419
            SIGNAL aca
1420
            {
1421
               format = "Logic";
1422
               name = "M_pipe_flush_baddr_nxt";
1423
               radix = "hexadecimal";
1424
            }
1425
            SIGNAL acb
1426
            {
1427
               format = "Logic";
1428
               name = "M_status_reg_pie";
1429
               radix = "hexadecimal";
1430
            }
1431
            SIGNAL acc
1432
            {
1433
               format = "Logic";
1434
               name = "M_ienable_reg";
1435
               radix = "hexadecimal";
1436
            }
1437
            SIGNAL acd
1438
            {
1439
               format = "Logic";
1440
               name = "intr_req";
1441
               radix = "hexadecimal";
1442
            }
1443
         }
1444
      }
1445
   }
1446
   MODULE onchip_memory
1447
   {
1448
      SLAVE s1
1449
      {
1450
         PORT_WIRING
1451
         {
1452
            PORT clk
1453
            {
1454
               type = "clk";
1455
               width = "1";
1456
               direction = "input";
1457
               Is_Enabled = "1";
1458
            }
1459
            PORT reset_n
1460
            {
1461
               type = "reset_n";
1462
               width = "1";
1463
               direction = "input";
1464
               Is_Enabled = "0";
1465
            }
1466
            PORT address
1467
            {
1468
               type = "address";
1469
               width = "11";
1470
               direction = "input";
1471
               Is_Enabled = "1";
1472
            }
1473
            PORT chipselect
1474
            {
1475
               type = "chipselect";
1476
               width = "1";
1477
               direction = "input";
1478
               Is_Enabled = "1";
1479
            }
1480
            PORT clken
1481
            {
1482
               type = "clken";
1483
               width = "1";
1484
               direction = "input";
1485
               Is_Enabled = "1";
1486
               default_value = "1'b1";
1487
            }
1488
            PORT read
1489
            {
1490
               type = "read";
1491
               width = "1";
1492
               direction = "input";
1493
               Is_Enabled = "0";
1494
            }
1495
            PORT readdata
1496
            {
1497
               type = "readdata";
1498
               width = "32";
1499
               direction = "output";
1500
               Is_Enabled = "1";
1501
            }
1502
            PORT write
1503
            {
1504
               type = "write";
1505
               width = "1";
1506
               direction = "input";
1507
               Is_Enabled = "1";
1508
            }
1509
            PORT writedata
1510
            {
1511
               type = "writedata";
1512
               width = "32";
1513
               direction = "input";
1514
               Is_Enabled = "1";
1515
            }
1516
            PORT debugaccess
1517
            {
1518
               type = "debugaccess";
1519
               width = "1";
1520
               direction = "input";
1521
               Is_Enabled = "0";
1522
            }
1523
            PORT byteenable
1524
            {
1525
               type = "byteenable";
1526
               width = "4";
1527
               direction = "input";
1528
               Is_Enabled = "1";
1529
            }
1530
         }
1531
         SYSTEM_BUILDER_INFO
1532
         {
1533
            Bus_Type = "avalon";
1534
            Write_Wait_States = "0cycles";
1535
            Read_Wait_States = "0cycles";
1536
            Hold_Time = "0cycles";
1537
            Setup_Time = "0cycles";
1538
            Is_Printable_Device = "0";
1539
            Address_Alignment = "dynamic";
1540
            Well_Behaved_Waitrequest = "0";
1541
            Is_Nonvolatile_Storage = "0";
1542
            Address_Span = "8192";
1543
            Read_Latency = "1";
1544
            Is_Memory_Device = "1";
1545
            Maximum_Pending_Read_Transactions = "0";
1546
            Minimum_Uninterrupted_Run_Length = "1";
1547
            Accepts_Internal_Connections = "1";
1548
            Write_Latency = "0";
1549
            Is_Flash = "0";
1550
            Data_Width = "32";
1551
            Address_Width = "11";
1552
            Maximum_Burst_Size = "1";
1553
            Register_Incoming_Signals = "0";
1554
            Register_Outgoing_Signals = "0";
1555
            Interleave_Bursts = "0";
1556
            Linewrap_Bursts = "0";
1557
            Burst_On_Burst_Boundaries_Only = "0";
1558
            Always_Burst_Max_Burst = "0";
1559
            Is_Big_Endian = "0";
1560
            Is_Enabled = "1";
1561
            MASTERED_BY cpu_0/instruction_master
1562
            {
1563
               priority = "1";
1564
               Offset_Address = "0x00904000";
1565
            }
1566
            MASTERED_BY cpu_0/data_master
1567
            {
1568
               priority = "1";
1569
               Offset_Address = "0x00904000";
1570
            }
1571
            Base_Address = "0x00904000";
1572
            Address_Group = "0";
1573
            Has_IRQ = "0";
1574
            Is_Channel = "1";
1575
            Is_Writable = "1";
1576
            IRQ_MASTER cpu_0/data_master
1577
            {
1578
               IRQ_Number = "NC";
1579
            }
1580
         }
1581
      }
1582
      iss_model_name = "altera_memory";
1583
      WIZARD_SCRIPT_ARGUMENTS
1584
      {
1585
         allow_mram_sim_contents_only_file = "0";
1586
         ram_block_type = "AUTO";
1587
         init_contents_file = "onchip_memory";
1588
         non_default_init_file_enabled = "0";
1589
         gui_ram_block_type = "Automatic";
1590
         Writeable = "1";
1591
         dual_port = "0";
1592
         Size_Value = "8192";
1593
         Size_Multiple = "1";
1594
         use_shallow_mem_blocks = "0";
1595
         init_mem_content = "1";
1596
         allow_in_system_memory_content_editor = "0";
1597
         instance_id = "NONE";
1598
         read_during_write_mode = "DONT_CARE";
1599
         ignore_auto_block_type_assignment = "1";
1600
         MAKE
1601
         {
1602
            TARGET delete_placeholder_warning
1603
            {
1604
               onchip_memory
1605
               {
1606
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
1607
                  Is_Phony = "1";
1608
                  Target_File = "do_delete_placeholder_warning";
1609
               }
1610
            }
1611
            TARGET hex
1612
            {
1613
               onchip_memory
1614
               {
1615
                  Command1 = "@echo Post-processing to create $(notdir $@)";
1616
                  Command2 = "elf2hex $(ELF) 0x00904000 0x905FFF --width=32 $(QUARTUS_PROJECT_DIR)/onchip_memory.hex --create-lanes=0 ";
1617
                  Dependency = "$(ELF)";
1618
                  Target_File = "$(QUARTUS_PROJECT_DIR)/onchip_memory.hex";
1619
               }
1620
            }
1621
            TARGET sim
1622
            {
1623
               onchip_memory
1624
               {
1625
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
1626
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
1627
                  Command3 = "touch $(SIMDIR)/dummy_file";
1628
                  Dependency = "$(ELF)";
1629
                  Target_File = "$(SIMDIR)/dummy_file";
1630
               }
1631
            }
1632
         }
1633
         contents_info = "";
1634
      }
1635
      SIMULATION
1636
      {
1637
         DISPLAY
1638
         {
1639
            SIGNAL a
1640
            {
1641
               name = "chipselect";
1642
               conditional = "1";
1643
            }
1644
            SIGNAL c
1645
            {
1646
               name = "address";
1647
               radix = "hexadecimal";
1648
            }
1649
            SIGNAL d
1650
            {
1651
               name = "byteenable";
1652
               radix = "binary";
1653
               conditional = "1";
1654
            }
1655
            SIGNAL e
1656
            {
1657
               name = "readdata";
1658
               radix = "hexadecimal";
1659
            }
1660
            SIGNAL b
1661
            {
1662
               name = "write";
1663
               conditional = "1";
1664
            }
1665
            SIGNAL f
1666
            {
1667
               name = "writedata";
1668
               radix = "hexadecimal";
1669
               conditional = "1";
1670
            }
1671
         }
1672
      }
1673
      SYSTEM_BUILDER_INFO
1674
      {
1675
         Prohibited_Device_Family = "MERCURY, APEX20K, APEX20KE, APEX20KC, APEXII, ACEX1K, FLEX10KE, EXCALIBUR_ARM, MAXII";
1676
         Instantiate_In_System_Module = "1";
1677
         Is_Enabled = "1";
1678
         Default_Module_Name = "onchip_memory";
1679
         Top_Level_Ports_Are_Enumerated = "1";
1680
         Clock_Source = "clk";
1681
         Has_Clock = "1";
1682
         View
1683
         {
1684
            MESSAGES
1685
            {
1686
            }
1687
         }
1688
      }
1689
      class = "altera_avalon_onchip_memory2";
1690
      class_version = "7.08";
1691
      HDL_INFO
1692
      {
1693
         Precompiled_Simulation_Library_Files = "";
1694
         Simulation_HDL_Files = "";
1695
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/onchip_memory.vhd";
1696
         Synthesis_Only_Files = "";
1697
      }
1698
      SLAVE s2
1699
      {
1700
         PORT_WIRING
1701
         {
1702
         }
1703
         SYSTEM_BUILDER_INFO
1704
         {
1705
            Bus_Type = "avalon";
1706
            Is_Memory_Device = "1";
1707
            Address_Group = "0";
1708
            Address_Alignment = "dynamic";
1709
            Address_Width = "11";
1710
            Data_Width = "32";
1711
            Has_IRQ = "0";
1712
            Read_Wait_States = "0";
1713
            Write_Wait_States = "0";
1714
            Address_Span = "8192";
1715
            Read_Latency = "1";
1716
            Is_Channel = "1";
1717
            Is_Enabled = "0";
1718
            Is_Writable = "1";
1719
         }
1720
      }
1721
      PORT_WIRING
1722
      {
1723
      }
1724
   }
1725
   MODULE jtag_uart_0
1726
   {
1727
      SLAVE avalon_jtag_slave
1728
      {
1729
         PORT_WIRING
1730
         {
1731
            PORT clk
1732
            {
1733
               type = "clk";
1734
               width = "1";
1735
               direction = "input";
1736
               Is_Enabled = "1";
1737
            }
1738
            PORT reset_n
1739
            {
1740
               type = "reset_n";
1741
               width = "1";
1742
               direction = "input";
1743
               Is_Enabled = "0";
1744
            }
1745
            PORT av_irq
1746
            {
1747
               type = "irq";
1748
               width = "1";
1749
               direction = "output";
1750
               Is_Enabled = "1";
1751
            }
1752
            PORT av_chipselect
1753
            {
1754
               type = "chipselect";
1755
               width = "1";
1756
               direction = "input";
1757
               Is_Enabled = "1";
1758
            }
1759
            PORT av_address
1760
            {
1761
               type = "address";
1762
               width = "1";
1763
               direction = "input";
1764
               Is_Enabled = "1";
1765
            }
1766
            PORT av_read_n
1767
            {
1768
               type = "read_n";
1769
               width = "1";
1770
               direction = "input";
1771
               Is_Enabled = "1";
1772
            }
1773
            PORT av_readdata
1774
            {
1775
               type = "readdata";
1776
               width = "32";
1777
               direction = "output";
1778
               Is_Enabled = "1";
1779
            }
1780
            PORT av_write_n
1781
            {
1782
               type = "write_n";
1783
               width = "1";
1784
               direction = "input";
1785
               Is_Enabled = "1";
1786
            }
1787
            PORT av_writedata
1788
            {
1789
               type = "writedata";
1790
               width = "32";
1791
               direction = "input";
1792
               Is_Enabled = "1";
1793
            }
1794
            PORT av_waitrequest
1795
            {
1796
               type = "waitrequest";
1797
               width = "1";
1798
               direction = "output";
1799
               Is_Enabled = "1";
1800
            }
1801
            PORT dataavailable
1802
            {
1803
               type = "dataavailable";
1804
               width = "1";
1805
               direction = "output";
1806
               Is_Enabled = "1";
1807
            }
1808
            PORT readyfordata
1809
            {
1810
               type = "readyfordata";
1811
               width = "1";
1812
               direction = "output";
1813
               Is_Enabled = "1";
1814
            }
1815
            PORT rst_n
1816
            {
1817
               type = "reset_n";
1818
               direction = "input";
1819
               width = "1";
1820
               Is_Enabled = "1";
1821
            }
1822
         }
1823
         SYSTEM_BUILDER_INFO
1824
         {
1825
            Has_IRQ = "1";
1826
            Bus_Type = "avalon";
1827
            Read_Wait_States = "peripheral_controlled";
1828
            Write_Wait_States = "peripheral_controlled";
1829
            Hold_Time = "0cycles";
1830
            Setup_Time = "0cycles";
1831
            Is_Printable_Device = "1";
1832
            Address_Alignment = "native";
1833
            Well_Behaved_Waitrequest = "0";
1834
            Is_Nonvolatile_Storage = "0";
1835
            Read_Latency = "0";
1836
            Is_Memory_Device = "0";
1837
            Maximum_Pending_Read_Transactions = "0";
1838
            Minimum_Uninterrupted_Run_Length = "1";
1839
            Accepts_Internal_Connections = "1";
1840
            Write_Latency = "0";
1841
            Is_Flash = "0";
1842
            Data_Width = "32";
1843
            Address_Width = "1";
1844
            Maximum_Burst_Size = "1";
1845
            Register_Incoming_Signals = "0";
1846
            Register_Outgoing_Signals = "0";
1847
            Interleave_Bursts = "0";
1848
            Linewrap_Bursts = "0";
1849
            Burst_On_Burst_Boundaries_Only = "0";
1850
            Always_Burst_Max_Burst = "0";
1851
            Is_Big_Endian = "0";
1852
            Is_Enabled = "1";
1853
            JTAG_Hub_Base_Id = "262254";
1854
            JTAG_Hub_Instance_Id = "0";
1855
            Connection_Limit = "1";
1856
            MASTERED_BY cpu_0/data_master
1857
            {
1858
               priority = "1";
1859
               Offset_Address = "0x009000d0";
1860
            }
1861
            IRQ_MASTER cpu_0/data_master
1862
            {
1863
               IRQ_Number = "1";
1864
            }
1865
            Base_Address = "0x009000d0";
1866
            Address_Group = "0";
1867
         }
1868
      }
1869
      class = "altera_avalon_jtag_uart";
1870
      class_version = "7.08";
1871
      iss_model_name = "altera_avalon_jtag_uart";
1872
      WIZARD_SCRIPT_ARGUMENTS
1873
      {
1874
         write_depth = "64";
1875
         read_depth = "64";
1876
         write_threshold = "8";
1877
         read_threshold = "8";
1878
         read_char_stream = "";
1879
         showascii = "1";
1880
         read_le = "0";
1881
         write_le = "0";
1882
         altera_show_unreleased_jtag_uart_features = "0";
1883
      }
1884
      SIMULATION
1885
      {
1886
         DISPLAY
1887
         {
1888
            SIGNAL av_chipselect
1889
            {
1890
               name = "av_chipselect";
1891
            }
1892
            SIGNAL av_address
1893
            {
1894
               name = "av_address";
1895
               radix = "hexadecimal";
1896
            }
1897
            SIGNAL av_read_n
1898
            {
1899
               name = "av_read_n";
1900
            }
1901
            SIGNAL av_readdata
1902
            {
1903
               name = "av_readdata";
1904
               radix = "hexadecimal";
1905
            }
1906
            SIGNAL av_write_n
1907
            {
1908
               name = "av_write_n";
1909
            }
1910
            SIGNAL av_writedata
1911
            {
1912
               name = "av_writedata";
1913
               radix = "hexadecimal";
1914
            }
1915
            SIGNAL av_waitrequest
1916
            {
1917
               name = "av_waitrequest";
1918
            }
1919
            SIGNAL dataavailable
1920
            {
1921
               name = "dataavailable";
1922
            }
1923
            SIGNAL readyfordata
1924
            {
1925
               name = "readyfordata";
1926
            }
1927
            SIGNAL av_irq
1928
            {
1929
               name = "av_irq";
1930
            }
1931
         }
1932
         INTERACTIVE_IN drive
1933
         {
1934
            enable = "0";
1935
            file = "_input_data_stream.dat";
1936
            mutex = "_input_data_mutex.dat";
1937
            log = "_in.log";
1938
            rate = "100";
1939
            signals = "temp,list";
1940
            exe = "nios2-terminal";
1941
         }
1942
         INTERACTIVE_OUT log
1943
         {
1944
            enable = "1";
1945
            exe = "perl -- atail-f.pl";
1946
            file = "_output_stream.dat";
1947
            radix = "ascii";
1948
            signals = "temp,list";
1949
         }
1950
         Fix_Me_Up = "";
1951
      }
1952
      SYSTEM_BUILDER_INFO
1953
      {
1954
         Is_Enabled = "1";
1955
         Clock_Source = "clk";
1956
         Has_Clock = "1";
1957
         Instantiate_In_System_Module = "1";
1958
         Iss_Launch_Telnet = "0";
1959
         Top_Level_Ports_Are_Enumerated = "1";
1960
         View
1961
         {
1962
            MESSAGES
1963
            {
1964
            }
1965
            Settings_Summary = "
Write Depth: 64; Write IRQ Threshold: 8
1966
                
Read Depth: 64; Read IRQ Threshold: 8";
1967
         }
1968
      }
1969
      HDL_INFO
1970
      {
1971
         Precompiled_Simulation_Library_Files = "";
1972
         Simulation_HDL_Files = "";
1973
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/jtag_uart_0.vhd";
1974
         Synthesis_Only_Files = "";
1975
      }
1976
      PORT_WIRING
1977
      {
1978
      }
1979
   }
1980
   MODULE sdram
1981
   {
1982
      SLAVE s1
1983
      {
1984
         PORT_WIRING
1985
         {
1986
            PORT clk
1987
            {
1988
               type = "clk";
1989
               width = "1";
1990
               direction = "input";
1991
               Is_Enabled = "1";
1992
            }
1993
            PORT reset_n
1994
            {
1995
               type = "reset_n";
1996
               width = "1";
1997
               direction = "input";
1998
               Is_Enabled = "1";
1999
            }
2000
            PORT az_addr
2001
            {
2002
               type = "address";
2003
               width = "22";
2004
               direction = "input";
2005
               Is_Enabled = "1";
2006
            }
2007
            PORT az_be_n
2008
            {
2009
               type = "byteenable_n";
2010
               width = "4";
2011
               direction = "input";
2012
               Is_Enabled = "1";
2013
            }
2014
            PORT az_cs
2015
            {
2016
               type = "chipselect";
2017
               width = "1";
2018
               direction = "input";
2019
               Is_Enabled = "1";
2020
            }
2021
            PORT az_data
2022
            {
2023
               type = "writedata";
2024
               width = "32";
2025
               direction = "input";
2026
               Is_Enabled = "1";
2027
            }
2028
            PORT az_rd_n
2029
            {
2030
               type = "read_n";
2031
               width = "1";
2032
               direction = "input";
2033
               Is_Enabled = "1";
2034
            }
2035
            PORT az_wr_n
2036
            {
2037
               type = "write_n";
2038
               width = "1";
2039
               direction = "input";
2040
               Is_Enabled = "1";
2041
            }
2042
            PORT za_data
2043
            {
2044
               type = "readdata";
2045
               width = "32";
2046
               direction = "output";
2047
               Is_Enabled = "1";
2048
            }
2049
            PORT za_valid
2050
            {
2051
               type = "readdatavalid";
2052
               width = "1";
2053
               direction = "output";
2054
               Is_Enabled = "1";
2055
            }
2056
            PORT za_waitrequest
2057
            {
2058
               type = "waitrequest";
2059
               width = "1";
2060
               direction = "output";
2061
               Is_Enabled = "1";
2062
            }
2063
            PORT zs_addr
2064
            {
2065
               direction = "output";
2066
               width = "12";
2067
               Is_Enabled = "1";
2068
            }
2069
            PORT zs_ba
2070
            {
2071
               direction = "output";
2072
               width = "2";
2073
               Is_Enabled = "1";
2074
            }
2075
            PORT zs_cas_n
2076
            {
2077
               direction = "output";
2078
               width = "1";
2079
               Is_Enabled = "1";
2080
            }
2081
            PORT zs_cke
2082
            {
2083
               direction = "output";
2084
               width = "1";
2085
               Is_Enabled = "1";
2086
            }
2087
            PORT zs_cs_n
2088
            {
2089
               direction = "output";
2090
               width = "1";
2091
               Is_Enabled = "1";
2092
            }
2093
            PORT zs_dq
2094
            {
2095
               direction = "inout";
2096
               width = "32";
2097
               Is_Enabled = "1";
2098
            }
2099
            PORT zs_dqm
2100
            {
2101
               direction = "output";
2102
               width = "4";
2103
               Is_Enabled = "1";
2104
            }
2105
            PORT zs_ras_n
2106
            {
2107
               direction = "output";
2108
               width = "1";
2109
               Is_Enabled = "1";
2110
            }
2111
            PORT zs_we_n
2112
            {
2113
               direction = "output";
2114
               width = "1";
2115
               Is_Enabled = "1";
2116
            }
2117
         }
2118
         SYSTEM_BUILDER_INFO
2119
         {
2120
            Bus_Type = "avalon";
2121
            Read_Wait_States = "peripheral_controlled";
2122
            Write_Wait_States = "peripheral_controlled";
2123
            Hold_Time = "0cycles";
2124
            Setup_Time = "0cycles";
2125
            Is_Printable_Device = "0";
2126
            Address_Alignment = "dynamic";
2127
            Well_Behaved_Waitrequest = "0";
2128
            Is_Nonvolatile_Storage = "0";
2129
            Address_Span = "16777216";
2130
            Read_Latency = "0";
2131
            Is_Memory_Device = "1";
2132
            Maximum_Pending_Read_Transactions = "6";
2133
            Minimum_Uninterrupted_Run_Length = "1";
2134
            Accepts_Internal_Connections = "1";
2135
            Write_Latency = "0";
2136
            Is_Flash = "0";
2137
            Data_Width = "32";
2138
            Address_Width = "22";
2139
            Maximum_Burst_Size = "1";
2140
            Register_Incoming_Signals = "0";
2141
            Register_Outgoing_Signals = "0";
2142
            Interleave_Bursts = "0";
2143
            Linewrap_Bursts = "0";
2144
            Burst_On_Burst_Boundaries_Only = "0";
2145
            Always_Burst_Max_Burst = "0";
2146
            Is_Big_Endian = "0";
2147
            Is_Enabled = "1";
2148
            MASTERED_BY cpu_0/instruction_master
2149
            {
2150
               priority = "1";
2151
               Offset_Address = "0x01000000";
2152
            }
2153
            MASTERED_BY cpu_0/data_master
2154
            {
2155
               priority = "1";
2156
               Offset_Address = "0x01000000";
2157
            }
2158
            Base_Address = "0x01000000";
2159
            Has_IRQ = "0";
2160
            Simulation_Num_Lanes = "1";
2161
            Address_Group = "0";
2162
            IRQ_MASTER cpu_0/data_master
2163
            {
2164
               IRQ_Number = "NC";
2165
            }
2166
         }
2167
      }
2168
      PORT_WIRING
2169
      {
2170
         PORT zs_addr
2171
         {
2172
            type = "export";
2173
            width = "12";
2174
            direction = "output";
2175
            Is_Enabled = "0";
2176
         }
2177
         PORT zs_ba
2178
         {
2179
            type = "export";
2180
            width = "2";
2181
            direction = "output";
2182
            Is_Enabled = "0";
2183
         }
2184
         PORT zs_cas_n
2185
         {
2186
            type = "export";
2187
            width = "1";
2188
            direction = "output";
2189
            Is_Enabled = "0";
2190
         }
2191
         PORT zs_cke
2192
         {
2193
            type = "export";
2194
            width = "1";
2195
            direction = "output";
2196
            Is_Enabled = "0";
2197
         }
2198
         PORT zs_cs_n
2199
         {
2200
            type = "export";
2201
            width = "1";
2202
            direction = "output";
2203
            Is_Enabled = "0";
2204
         }
2205
         PORT zs_dq
2206
         {
2207
            type = "export";
2208
            width = "32";
2209
            direction = "output";
2210
            Is_Enabled = "0";
2211
         }
2212
         PORT zs_dqm
2213
         {
2214
            type = "export";
2215
            width = "4";
2216
            direction = "output";
2217
            Is_Enabled = "0";
2218
         }
2219
         PORT zs_ras_n
2220
         {
2221
            type = "export";
2222
            width = "1";
2223
            direction = "output";
2224
            Is_Enabled = "0";
2225
         }
2226
         PORT zs_we_n
2227
         {
2228
            type = "export";
2229
            width = "1";
2230
            direction = "output";
2231
            Is_Enabled = "0";
2232
         }
2233
      }
2234
      iss_model_name = "altera_memory";
2235
      WIZARD_SCRIPT_ARGUMENTS
2236
      {
2237
         register_data_in = "1";
2238
         sim_model_base = "0";
2239
         sdram_data_width = "32";
2240
         sdram_addr_width = "12";
2241
         sdram_row_width = "12";
2242
         sdram_col_width = "8";
2243
         sdram_num_chipselects = "1";
2244
         sdram_num_banks = "4";
2245
         refresh_period = "15.625";
2246
         powerup_delay = "100.0";
2247
         cas_latency = "2";
2248
         t_rfc = "70.0";
2249
         t_rp = "15.0";
2250
         t_mrd = "3";
2251
         t_rcd = "15.0";
2252
         t_ac = "6.0";
2253
         t_wr = "14.0";
2254
         init_refresh_commands = "2";
2255
         init_nop_delay = "0.0";
2256
         shared_data = "0";
2257
         sdram_bank_width = "2";
2258
         tristate_bridge_slave = "";
2259
         starvation_indicator = "0";
2260
         is_initialized = "1";
2261
      }
2262
      SIMULATION
2263
      {
2264
         DISPLAY
2265
         {
2266
            SIGNAL a
2267
            {
2268
               name = "az_addr";
2269
               radix = "hexadecimal";
2270
            }
2271
            SIGNAL b
2272
            {
2273
               name = "az_be_n";
2274
               radix = "hexadecimal";
2275
            }
2276
            SIGNAL c
2277
            {
2278
               name = "az_cs";
2279
            }
2280
            SIGNAL d
2281
            {
2282
               name = "az_data";
2283
               radix = "hexadecimal";
2284
            }
2285
            SIGNAL e
2286
            {
2287
               name = "az_rd_n";
2288
            }
2289
            SIGNAL f
2290
            {
2291
               name = "az_wr_n";
2292
            }
2293
            SIGNAL h
2294
            {
2295
               name = "za_data";
2296
               radix = "hexadecimal";
2297
            }
2298
            SIGNAL i
2299
            {
2300
               name = "za_valid";
2301
            }
2302
            SIGNAL j
2303
            {
2304
               name = "za_waitrequest";
2305
            }
2306
            SIGNAL l
2307
            {
2308
               name = "CODE";
2309
               radix = "ascii";
2310
            }
2311
            SIGNAL g
2312
            {
2313
               name = "clk";
2314
            }
2315
            SIGNAL k
2316
            {
2317
               name = "za_cannotrefresh";
2318
               suppress = "1";
2319
            }
2320
            SIGNAL m
2321
            {
2322
               name = "zs_addr";
2323
               radix = "hexadecimal";
2324
               suppress = "0";
2325
            }
2326
            SIGNAL n
2327
            {
2328
               name = "zs_ba";
2329
               radix = "hexadecimal";
2330
               suppress = "0";
2331
            }
2332
            SIGNAL o
2333
            {
2334
               name = "zs_cs_n";
2335
               radix = "hexadecimal";
2336
               suppress = "0";
2337
            }
2338
            SIGNAL p
2339
            {
2340
               name = "zs_ras_n";
2341
               suppress = "0";
2342
            }
2343
            SIGNAL q
2344
            {
2345
               name = "zs_cas_n";
2346
               suppress = "0";
2347
            }
2348
            SIGNAL r
2349
            {
2350
               name = "zs_we_n";
2351
               suppress = "0";
2352
            }
2353
            SIGNAL s
2354
            {
2355
               name = "zs_dq";
2356
               radix = "hexadecimal";
2357
               suppress = "0";
2358
            }
2359
            SIGNAL t
2360
            {
2361
               name = "zs_dqm";
2362
               radix = "hexadecimal";
2363
               suppress = "0";
2364
            }
2365
            SIGNAL u
2366
            {
2367
               name = "zt_addr";
2368
               radix = "hexadecimal";
2369
               suppress = "1";
2370
            }
2371
            SIGNAL v
2372
            {
2373
               name = "zt_ba";
2374
               radix = "hexadecimal";
2375
               suppress = "1";
2376
            }
2377
            SIGNAL w
2378
            {
2379
               name = "zt_oe";
2380
               suppress = "1";
2381
            }
2382
            SIGNAL x
2383
            {
2384
               name = "zt_cke";
2385
               suppress = "1";
2386
            }
2387
            SIGNAL y
2388
            {
2389
               name = "zt_chipselect";
2390
               suppress = "1";
2391
            }
2392
            SIGNAL z0
2393
            {
2394
               name = "zt_lock_n";
2395
               suppress = "1";
2396
            }
2397
            SIGNAL z1
2398
            {
2399
               name = "zt_ras_n";
2400
               suppress = "1";
2401
            }
2402
            SIGNAL z2
2403
            {
2404
               name = "zt_cas_n";
2405
               suppress = "1";
2406
            }
2407
            SIGNAL z3
2408
            {
2409
               name = "zt_we_n";
2410
               suppress = "1";
2411
            }
2412
            SIGNAL z4
2413
            {
2414
               name = "zt_cs_n";
2415
               radix = "hexadecimal";
2416
               suppress = "1";
2417
            }
2418
            SIGNAL z5
2419
            {
2420
               name = "zt_dqm";
2421
               radix = "hexadecimal";
2422
               suppress = "1";
2423
            }
2424
            SIGNAL z6
2425
            {
2426
               name = "zt_data";
2427
               radix = "hexadecimal";
2428
               suppress = "1";
2429
            }
2430
            SIGNAL z7
2431
            {
2432
               name = "tz_data";
2433
               radix = "hexadecimal";
2434
               suppress = "1";
2435
            }
2436
            SIGNAL z8
2437
            {
2438
               name = "tz_waitrequest";
2439
               suppress = "1";
2440
            }
2441
         }
2442
         Fix_Me_Up = "";
2443
      }
2444
      SYSTEM_BUILDER_INFO
2445
      {
2446
         Instantiate_In_System_Module = "1";
2447
         Is_Enabled = "1";
2448
         Default_Module_Name = "sdram";
2449
         Top_Level_Ports_Are_Enumerated = "1";
2450
         Clock_Source = "clk";
2451
         Has_Clock = "1";
2452
         Disable_Simulation_Port_Wiring = "0";
2453
         View
2454
         {
2455
            MESSAGES
2456
            {
2457
            }
2458
            Settings_Summary = "4194304 x 32
2459
                Memory size: 16 MBytes
2460
                128 MBits
2461
                ";
2462
         }
2463
      }
2464
      class = "altera_avalon_new_sdram_controller";
2465
      class_version = "7.08";
2466
      HDL_INFO
2467
      {
2468
         Precompiled_Simulation_Library_Files = "";
2469
         Simulation_HDL_Files = "";
2470
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sdram.vhd";
2471
         Synthesis_Only_Files = "";
2472
      }
2473
   }
2474
   MODULE sysid
2475
   {
2476
      SLAVE control_slave
2477
      {
2478
         PORT_WIRING
2479
         {
2480
            PORT clock
2481
            {
2482
               type = "clk";
2483
               width = "1";
2484
               direction = "input";
2485
               Is_Enabled = "0";
2486
            }
2487
            PORT reset_n
2488
            {
2489
               type = "reset_n";
2490
               width = "1";
2491
               direction = "input";
2492
               Is_Enabled = "0";
2493
            }
2494
            PORT address
2495
            {
2496
               type = "address";
2497
               width = "1";
2498
               direction = "input";
2499
               Is_Enabled = "1";
2500
            }
2501
            PORT readdata
2502
            {
2503
               type = "readdata";
2504
               width = "32";
2505
               direction = "output";
2506
               Is_Enabled = "1";
2507
            }
2508
         }
2509
         SYSTEM_BUILDER_INFO
2510
         {
2511
            Bus_Type = "avalon";
2512
            Write_Wait_States = "0cycles";
2513
            Read_Wait_States = "1cycles";
2514
            Hold_Time = "0cycles";
2515
            Setup_Time = "0cycles";
2516
            Is_Printable_Device = "0";
2517
            Address_Alignment = "native";
2518
            Well_Behaved_Waitrequest = "0";
2519
            Is_Nonvolatile_Storage = "0";
2520
            Read_Latency = "0";
2521
            Is_Memory_Device = "0";
2522
            Maximum_Pending_Read_Transactions = "0";
2523
            Minimum_Uninterrupted_Run_Length = "1";
2524
            Accepts_Internal_Connections = "1";
2525
            Write_Latency = "0";
2526
            Is_Flash = "0";
2527
            Data_Width = "32";
2528
            Address_Width = "1";
2529
            Maximum_Burst_Size = "1";
2530
            Register_Incoming_Signals = "0";
2531
            Register_Outgoing_Signals = "0";
2532
            Interleave_Bursts = "0";
2533
            Linewrap_Bursts = "0";
2534
            Burst_On_Burst_Boundaries_Only = "0";
2535
            Always_Burst_Max_Burst = "0";
2536
            Is_Big_Endian = "0";
2537
            Is_Enabled = "1";
2538
            MASTERED_BY cpu_0/data_master
2539
            {
2540
               priority = "1";
2541
               Offset_Address = "0x009000d8";
2542
            }
2543
            Base_Address = "0x009000d8";
2544
            Has_IRQ = "0";
2545
            Address_Group = "0";
2546
            IRQ_MASTER cpu_0/data_master
2547
            {
2548
               IRQ_Number = "NC";
2549
            }
2550
         }
2551
      }
2552
      class = "altera_avalon_sysid";
2553
      class_version = "7.08";
2554
      SYSTEM_BUILDER_INFO
2555
      {
2556
         Date_Modified = "";
2557
         Is_Enabled = "1";
2558
         Instantiate_In_System_Module = "1";
2559
         Fixed_Module_Name = "sysid";
2560
         Top_Level_Ports_Are_Enumerated = "1";
2561
         Clock_Source = "clk";
2562
         Has_Clock = "1";
2563
         View
2564
         {
2565
            Settings_Summary = "System ID (at last Generate):
2A1C5786 (unique ID tag)
485BC1C0 (timestamp: Fri Jun 20, 2008 @4:42 PM)";
2566
            MESSAGES
2567
            {
2568
            }
2569
         }
2570
      }
2571
      WIZARD_SCRIPT_ARGUMENTS
2572
      {
2573
         id = "706500486u";
2574
         timestamp = "1213972928u";
2575
         regenerate_values = "0";
2576
         MAKE
2577
         {
2578
            TARGET verifysysid
2579
            {
2580
               verifysysid
2581
               {
2582
                  All_Depends_On = "0";
2583
                  Command = "nios2-download $(JTAG_CABLE)                                --sidp=0x009000d8 --id=706500486 --timestamp=1213972928";
2584
                  Is_Phony = "1";
2585
                  Target_File = "dummy_verifysysid_file";
2586
               }
2587
            }
2588
         }
2589
      }
2590
      HDL_INFO
2591
      {
2592
         Precompiled_Simulation_Library_Files = "";
2593
         Simulation_HDL_Files = "";
2594
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sysid.vhd";
2595
         Synthesis_Only_Files = "";
2596
      }
2597
      PORT_WIRING
2598
      {
2599
      }
2600
   }
2601
   MODULE LED_Pio
2602
   {
2603
      SLAVE s1
2604
      {
2605
         PORT_WIRING
2606
         {
2607
            PORT clk
2608
            {
2609
               type = "clk";
2610
               width = "1";
2611
               direction = "input";
2612
               Is_Enabled = "1";
2613
            }
2614
            PORT reset_n
2615
            {
2616
               type = "reset_n";
2617
               width = "1";
2618
               direction = "input";
2619
               Is_Enabled = "1";
2620
            }
2621
            PORT address
2622
            {
2623
               type = "address";
2624
               width = "2";
2625
               direction = "input";
2626
               Is_Enabled = "1";
2627
            }
2628
            PORT write_n
2629
            {
2630
               type = "write_n";
2631
               width = "1";
2632
               direction = "input";
2633
               Is_Enabled = "1";
2634
            }
2635
            PORT writedata
2636
            {
2637
               type = "writedata";
2638
               width = "8";
2639
               direction = "input";
2640
               Is_Enabled = "1";
2641
            }
2642
            PORT chipselect
2643
            {
2644
               type = "chipselect";
2645
               width = "1";
2646
               direction = "input";
2647
               Is_Enabled = "1";
2648
            }
2649
         }
2650
         SYSTEM_BUILDER_INFO
2651
         {
2652
            Bus_Type = "avalon";
2653
            Write_Wait_States = "0cycles";
2654
            Read_Wait_States = "1cycles";
2655
            Hold_Time = "0cycles";
2656
            Setup_Time = "0cycles";
2657
            Is_Printable_Device = "0";
2658
            Address_Alignment = "native";
2659
            Well_Behaved_Waitrequest = "0";
2660
            Is_Nonvolatile_Storage = "0";
2661
            Read_Latency = "0";
2662
            Is_Memory_Device = "0";
2663
            Maximum_Pending_Read_Transactions = "0";
2664
            Minimum_Uninterrupted_Run_Length = "1";
2665
            Accepts_Internal_Connections = "1";
2666
            Write_Latency = "0";
2667
            Is_Flash = "0";
2668
            Data_Width = "8";
2669
            Address_Width = "2";
2670
            Maximum_Burst_Size = "1";
2671
            Register_Incoming_Signals = "0";
2672
            Register_Outgoing_Signals = "0";
2673
            Interleave_Bursts = "0";
2674
            Linewrap_Bursts = "0";
2675
            Burst_On_Burst_Boundaries_Only = "0";
2676
            Always_Burst_Max_Burst = "0";
2677
            Is_Big_Endian = "0";
2678
            Is_Enabled = "1";
2679
            MASTERED_BY cpu_0/data_master
2680
            {
2681
               priority = "1";
2682
               Offset_Address = "0x00900080";
2683
            }
2684
            Base_Address = "0x00900080";
2685
            Has_IRQ = "0";
2686
            Address_Group = "0";
2687
            IRQ_MASTER cpu_0/data_master
2688
            {
2689
               IRQ_Number = "NC";
2690
            }
2691
            Is_Readable = "0";
2692
            Is_Writable = "1";
2693
         }
2694
      }
2695
      PORT_WIRING
2696
      {
2697
         PORT out_port
2698
         {
2699
            type = "export";
2700
            width = "8";
2701
            direction = "output";
2702
            Is_Enabled = "1";
2703
         }
2704
         PORT in_port
2705
         {
2706
            direction = "input";
2707
            Is_Enabled = "0";
2708
            width = "8";
2709
         }
2710
         PORT bidir_port
2711
         {
2712
            direction = "inout";
2713
            Is_Enabled = "0";
2714
            width = "8";
2715
         }
2716
      }
2717
      class = "altera_avalon_pio";
2718
      class_version = "7.08";
2719
      SYSTEM_BUILDER_INFO
2720
      {
2721
         Is_Enabled = "1";
2722
         Instantiate_In_System_Module = "1";
2723
         Wire_Test_Bench_Values = "1";
2724
         Top_Level_Ports_Are_Enumerated = "1";
2725
         Clock_Source = "clk";
2726
         Has_Clock = "1";
2727
         Date_Modified = "";
2728
         View
2729
         {
2730
            MESSAGES
2731
            {
2732
            }
2733
            Settings_Summary = " 8-bit PIO using 
2734
 
2735
 
2736
                                         output pins";
2737
         }
2738
      }
2739
      WIZARD_SCRIPT_ARGUMENTS
2740
      {
2741
         Do_Test_Bench_Wiring = "0";
2742
         Driven_Sim_Value = "0";
2743
         has_tri = "0";
2744
         has_out = "1";
2745
         has_in = "0";
2746
         capture = "0";
2747
         Data_Width = "8";
2748
         reset_value = "0";
2749
         edge_type = "NONE";
2750
         irq_type = "NONE";
2751
         bit_clearing_edge_register = "0";
2752
      }
2753
      HDL_INFO
2754
      {
2755
         Precompiled_Simulation_Library_Files = "";
2756
         Simulation_HDL_Files = "";
2757
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/LED_Pio.vhd";
2758
         Synthesis_Only_Files = "";
2759
      }
2760
   }
2761
   MODULE SG_Pio
2762
   {
2763
      SLAVE s1
2764
      {
2765
         PORT_WIRING
2766
         {
2767
            PORT clk
2768
            {
2769
               type = "clk";
2770
               width = "1";
2771
               direction = "input";
2772
               Is_Enabled = "1";
2773
            }
2774
            PORT reset_n
2775
            {
2776
               type = "reset_n";
2777
               width = "1";
2778
               direction = "input";
2779
               Is_Enabled = "1";
2780
            }
2781
            PORT address
2782
            {
2783
               type = "address";
2784
               width = "2";
2785
               direction = "input";
2786
               Is_Enabled = "1";
2787
            }
2788
            PORT write_n
2789
            {
2790
               type = "write_n";
2791
               width = "1";
2792
               direction = "input";
2793
               Is_Enabled = "1";
2794
            }
2795
            PORT writedata
2796
            {
2797
               type = "writedata";
2798
               width = "14";
2799
               direction = "input";
2800
               Is_Enabled = "1";
2801
            }
2802
            PORT chipselect
2803
            {
2804
               type = "chipselect";
2805
               width = "1";
2806
               direction = "input";
2807
               Is_Enabled = "1";
2808
            }
2809
         }
2810
         SYSTEM_BUILDER_INFO
2811
         {
2812
            Bus_Type = "avalon";
2813
            Write_Wait_States = "0cycles";
2814
            Read_Wait_States = "1cycles";
2815
            Hold_Time = "0cycles";
2816
            Setup_Time = "0cycles";
2817
            Is_Printable_Device = "0";
2818
            Address_Alignment = "native";
2819
            Well_Behaved_Waitrequest = "0";
2820
            Is_Nonvolatile_Storage = "0";
2821
            Read_Latency = "0";
2822
            Is_Memory_Device = "0";
2823
            Maximum_Pending_Read_Transactions = "0";
2824
            Minimum_Uninterrupted_Run_Length = "1";
2825
            Accepts_Internal_Connections = "1";
2826
            Write_Latency = "0";
2827
            Is_Flash = "0";
2828
            Data_Width = "14";
2829
            Address_Width = "2";
2830
            Maximum_Burst_Size = "1";
2831
            Register_Incoming_Signals = "0";
2832
            Register_Outgoing_Signals = "0";
2833
            Interleave_Bursts = "0";
2834
            Linewrap_Bursts = "0";
2835
            Burst_On_Burst_Boundaries_Only = "0";
2836
            Always_Burst_Max_Burst = "0";
2837
            Is_Big_Endian = "0";
2838
            Is_Enabled = "1";
2839
            MASTERED_BY cpu_0/data_master
2840
            {
2841
               priority = "1";
2842
               Offset_Address = "0x00900090";
2843
            }
2844
            Base_Address = "0x00900090";
2845
            Has_IRQ = "0";
2846
            Address_Group = "0";
2847
            IRQ_MASTER cpu_0/data_master
2848
            {
2849
               IRQ_Number = "NC";
2850
            }
2851
            Is_Readable = "0";
2852
            Is_Writable = "1";
2853
         }
2854
      }
2855
      PORT_WIRING
2856
      {
2857
         PORT out_port
2858
         {
2859
            type = "export";
2860
            width = "14";
2861
            direction = "output";
2862
            Is_Enabled = "1";
2863
         }
2864
         PORT in_port
2865
         {
2866
            direction = "input";
2867
            Is_Enabled = "0";
2868
            width = "14";
2869
         }
2870
         PORT bidir_port
2871
         {
2872
            direction = "inout";
2873
            Is_Enabled = "0";
2874
            width = "14";
2875
         }
2876
      }
2877
      class = "altera_avalon_pio";
2878
      class_version = "7.08";
2879
      SYSTEM_BUILDER_INFO
2880
      {
2881
         Is_Enabled = "1";
2882
         Instantiate_In_System_Module = "1";
2883
         Wire_Test_Bench_Values = "1";
2884
         Top_Level_Ports_Are_Enumerated = "1";
2885
         Clock_Source = "clk";
2886
         Has_Clock = "1";
2887
         Date_Modified = "";
2888
         View
2889
         {
2890
            MESSAGES
2891
            {
2892
            }
2893
            Settings_Summary = " 14-bit PIO using 
2894
 
2895
 
2896
                                         output pins";
2897
         }
2898
      }
2899
      WIZARD_SCRIPT_ARGUMENTS
2900
      {
2901
         Do_Test_Bench_Wiring = "0";
2902
         Driven_Sim_Value = "0";
2903
         has_tri = "0";
2904
         has_out = "1";
2905
         has_in = "0";
2906
         capture = "0";
2907
         Data_Width = "14";
2908
         reset_value = "0";
2909
         edge_type = "NONE";
2910
         irq_type = "NONE";
2911
         bit_clearing_edge_register = "0";
2912
      }
2913
      HDL_INFO
2914
      {
2915
         Precompiled_Simulation_Library_Files = "";
2916
         Simulation_HDL_Files = "";
2917
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/SG_Pio.vhd";
2918
         Synthesis_Only_Files = "";
2919
      }
2920
   }
2921
   MODULE IO_Pio
2922
   {
2923
      SLAVE s1
2924
      {
2925
         PORT_WIRING
2926
         {
2927
            PORT clk
2928
            {
2929
               type = "clk";
2930
               width = "1";
2931
               direction = "input";
2932
               Is_Enabled = "1";
2933
            }
2934
            PORT reset_n
2935
            {
2936
               type = "reset_n";
2937
               width = "1";
2938
               direction = "input";
2939
               Is_Enabled = "1";
2940
            }
2941
            PORT address
2942
            {
2943
               type = "address";
2944
               width = "2";
2945
               direction = "input";
2946
               Is_Enabled = "1";
2947
            }
2948
            PORT write_n
2949
            {
2950
               type = "write_n";
2951
               width = "1";
2952
               direction = "input";
2953
               Is_Enabled = "1";
2954
            }
2955
            PORT writedata
2956
            {
2957
               type = "writedata";
2958
               width = "32";
2959
               direction = "input";
2960
               Is_Enabled = "1";
2961
            }
2962
            PORT chipselect
2963
            {
2964
               type = "chipselect";
2965
               width = "1";
2966
               direction = "input";
2967
               Is_Enabled = "1";
2968
            }
2969
            PORT readdata
2970
            {
2971
               type = "readdata";
2972
               width = "32";
2973
               direction = "output";
2974
               Is_Enabled = "1";
2975
            }
2976
         }
2977
         SYSTEM_BUILDER_INFO
2978
         {
2979
            Bus_Type = "avalon";
2980
            Write_Wait_States = "0cycles";
2981
            Read_Wait_States = "1cycles";
2982
            Hold_Time = "0cycles";
2983
            Setup_Time = "0cycles";
2984
            Is_Printable_Device = "0";
2985
            Address_Alignment = "native";
2986
            Well_Behaved_Waitrequest = "0";
2987
            Is_Nonvolatile_Storage = "0";
2988
            Read_Latency = "0";
2989
            Is_Memory_Device = "0";
2990
            Maximum_Pending_Read_Transactions = "0";
2991
            Minimum_Uninterrupted_Run_Length = "1";
2992
            Accepts_Internal_Connections = "1";
2993
            Write_Latency = "0";
2994
            Is_Flash = "0";
2995
            Data_Width = "32";
2996
            Address_Width = "2";
2997
            Maximum_Burst_Size = "1";
2998
            Register_Incoming_Signals = "0";
2999
            Register_Outgoing_Signals = "0";
3000
            Interleave_Bursts = "0";
3001
            Linewrap_Bursts = "0";
3002
            Burst_On_Burst_Boundaries_Only = "0";
3003
            Always_Burst_Max_Burst = "0";
3004
            Is_Big_Endian = "0";
3005
            Is_Enabled = "1";
3006
            MASTERED_BY cpu_0/data_master
3007
            {
3008
               priority = "1";
3009
               Offset_Address = "0x009000a0";
3010
            }
3011
            Base_Address = "0x009000a0";
3012
            Has_IRQ = "0";
3013
            Address_Group = "0";
3014
            IRQ_MASTER cpu_0/data_master
3015
            {
3016
               IRQ_Number = "NC";
3017
            }
3018
            Is_Readable = "1";
3019
            Is_Writable = "1";
3020
         }
3021
      }
3022
      PORT_WIRING
3023
      {
3024
         PORT bidir_port
3025
         {
3026
            type = "export";
3027
            width = "32";
3028
            direction = "inout";
3029
            Is_Enabled = "1";
3030
         }
3031
         PORT in_port
3032
         {
3033
            direction = "input";
3034
            Is_Enabled = "0";
3035
            width = "32";
3036
         }
3037
         PORT out_port
3038
         {
3039
            direction = "output";
3040
            Is_Enabled = "0";
3041
            width = "32";
3042
         }
3043
      }
3044
      class = "altera_avalon_pio";
3045
      class_version = "7.08";
3046
      SYSTEM_BUILDER_INFO
3047
      {
3048
         Is_Enabled = "1";
3049
         Instantiate_In_System_Module = "1";
3050
         Wire_Test_Bench_Values = "1";
3051
         Top_Level_Ports_Are_Enumerated = "1";
3052
         Clock_Source = "clk";
3053
         Has_Clock = "1";
3054
         Date_Modified = "";
3055
         View
3056
         {
3057
            MESSAGES
3058
            {
3059
            }
3060
            Settings_Summary = " 32-bit PIO using 
3061
                                         tri-state pins with edge type NONE and interrupt source NONE
3062
 
3063
                                        ";
3064
         }
3065
      }
3066
      WIZARD_SCRIPT_ARGUMENTS
3067
      {
3068
         Do_Test_Bench_Wiring = "0";
3069
         Driven_Sim_Value = "0";
3070
         has_tri = "1";
3071
         has_out = "0";
3072
         has_in = "0";
3073
         capture = "0";
3074
         Data_Width = "32";
3075
         reset_value = "0";
3076
         edge_type = "NONE";
3077
         irq_type = "NONE";
3078
         bit_clearing_edge_register = "0";
3079
      }
3080
      HDL_INFO
3081
      {
3082
         Precompiled_Simulation_Library_Files = "";
3083
         Simulation_HDL_Files = "";
3084
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/IO_Pio.vhd";
3085
         Synthesis_Only_Files = "";
3086
      }
3087
   }
3088
   MODULE Button_Pio
3089
   {
3090
      SLAVE s1
3091
      {
3092
         PORT_WIRING
3093
         {
3094
            PORT clk
3095
            {
3096
               type = "clk";
3097
               width = "1";
3098
               direction = "input";
3099
               Is_Enabled = "1";
3100
            }
3101
            PORT reset_n
3102
            {
3103
               type = "reset_n";
3104
               width = "1";
3105
               direction = "input";
3106
               Is_Enabled = "1";
3107
            }
3108
            PORT address
3109
            {
3110
               type = "address";
3111
               width = "2";
3112
               direction = "input";
3113
               Is_Enabled = "1";
3114
            }
3115
            PORT readdata
3116
            {
3117
               type = "readdata";
3118
               width = "9";
3119
               direction = "output";
3120
               Is_Enabled = "1";
3121
            }
3122
         }
3123
         SYSTEM_BUILDER_INFO
3124
         {
3125
            Bus_Type = "avalon";
3126
            Write_Wait_States = "0cycles";
3127
            Read_Wait_States = "1cycles";
3128
            Hold_Time = "0cycles";
3129
            Setup_Time = "0cycles";
3130
            Is_Printable_Device = "0";
3131
            Address_Alignment = "native";
3132
            Well_Behaved_Waitrequest = "0";
3133
            Is_Nonvolatile_Storage = "0";
3134
            Read_Latency = "0";
3135
            Is_Memory_Device = "0";
3136
            Maximum_Pending_Read_Transactions = "0";
3137
            Minimum_Uninterrupted_Run_Length = "1";
3138
            Accepts_Internal_Connections = "1";
3139
            Write_Latency = "0";
3140
            Is_Flash = "0";
3141
            Data_Width = "9";
3142
            Address_Width = "2";
3143
            Maximum_Burst_Size = "1";
3144
            Register_Incoming_Signals = "0";
3145
            Register_Outgoing_Signals = "0";
3146
            Interleave_Bursts = "0";
3147
            Linewrap_Bursts = "0";
3148
            Burst_On_Burst_Boundaries_Only = "0";
3149
            Always_Burst_Max_Burst = "0";
3150
            Is_Big_Endian = "0";
3151
            Is_Enabled = "1";
3152
            MASTERED_BY cpu_0/data_master
3153
            {
3154
               priority = "1";
3155
               Offset_Address = "0x009000b0";
3156
            }
3157
            Base_Address = "0x009000b0";
3158
            Has_IRQ = "0";
3159
            Address_Group = "0";
3160
            IRQ_MASTER cpu_0/data_master
3161
            {
3162
               IRQ_Number = "NC";
3163
            }
3164
            Is_Readable = "1";
3165
            Is_Writable = "0";
3166
         }
3167
      }
3168
      PORT_WIRING
3169
      {
3170
         PORT in_port
3171
         {
3172
            type = "export";
3173
            width = "9";
3174
            direction = "input";
3175
            Is_Enabled = "1";
3176
         }
3177
         PORT out_port
3178
         {
3179
            direction = "output";
3180
            Is_Enabled = "0";
3181
            width = "9";
3182
         }
3183
         PORT bidir_port
3184
         {
3185
            direction = "inout";
3186
            Is_Enabled = "0";
3187
            width = "9";
3188
         }
3189
      }
3190
      class = "altera_avalon_pio";
3191
      class_version = "7.08";
3192
      SYSTEM_BUILDER_INFO
3193
      {
3194
         Is_Enabled = "1";
3195
         Instantiate_In_System_Module = "1";
3196
         Wire_Test_Bench_Values = "1";
3197
         Top_Level_Ports_Are_Enumerated = "1";
3198
         Clock_Source = "clk";
3199
         Has_Clock = "1";
3200
         Date_Modified = "";
3201
         View
3202
         {
3203
            MESSAGES
3204
            {
3205
            }
3206
            Settings_Summary = " 9-bit PIO using 
3207
 
3208
                                         input pins with edge type NONE and interrupt source NONE
3209
                                        ";
3210
         }
3211
      }
3212
      WIZARD_SCRIPT_ARGUMENTS
3213
      {
3214
         Do_Test_Bench_Wiring = "0";
3215
         Driven_Sim_Value = "0";
3216
         has_tri = "0";
3217
         has_out = "0";
3218
         has_in = "1";
3219
         capture = "0";
3220
         Data_Width = "9";
3221
         reset_value = "0";
3222
         edge_type = "NONE";
3223
         irq_type = "NONE";
3224
         bit_clearing_edge_register = "0";
3225
      }
3226
      HDL_INFO
3227
      {
3228
         Precompiled_Simulation_Library_Files = "";
3229
         Simulation_HDL_Files = "";
3230
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/Button_Pio.vhd";
3231
         Synthesis_Only_Files = "";
3232
      }
3233
   }
3234
   MODULE uart
3235
   {
3236
      SLAVE s1
3237
      {
3238
         PORT_WIRING
3239
         {
3240
            PORT clk
3241
            {
3242
               type = "clk";
3243
               width = "1";
3244
               direction = "input";
3245
               Is_Enabled = "1";
3246
            }
3247
            PORT reset_n
3248
            {
3249
               type = "reset_n";
3250
               width = "1";
3251
               direction = "input";
3252
               Is_Enabled = "1";
3253
            }
3254
            PORT irq
3255
            {
3256
               type = "irq";
3257
               width = "1";
3258
               direction = "output";
3259
               Is_Enabled = "1";
3260
            }
3261
            PORT address
3262
            {
3263
               type = "address";
3264
               width = "3";
3265
               direction = "input";
3266
               Is_Enabled = "1";
3267
            }
3268
            PORT begintransfer
3269
            {
3270
               type = "begintransfer";
3271
               width = "1";
3272
               direction = "input";
3273
               Is_Enabled = "1";
3274
            }
3275
            PORT chipselect
3276
            {
3277
               type = "chipselect";
3278
               width = "1";
3279
               direction = "input";
3280
               Is_Enabled = "1";
3281
            }
3282
            PORT read_n
3283
            {
3284
               type = "read_n";
3285
               width = "1";
3286
               direction = "input";
3287
               Is_Enabled = "1";
3288
            }
3289
            PORT write_n
3290
            {
3291
               type = "write_n";
3292
               width = "1";
3293
               direction = "input";
3294
               Is_Enabled = "1";
3295
            }
3296
            PORT writedata
3297
            {
3298
               type = "writedata";
3299
               width = "16";
3300
               direction = "input";
3301
               Is_Enabled = "1";
3302
            }
3303
            PORT readdata
3304
            {
3305
               type = "readdata";
3306
               width = "16";
3307
               direction = "output";
3308
               Is_Enabled = "1";
3309
            }
3310
            PORT dataavailable
3311
            {
3312
               type = "dataavailable";
3313
               width = "1";
3314
               direction = "output";
3315
               Is_Enabled = "1";
3316
            }
3317
            PORT readyfordata
3318
            {
3319
               type = "readyfordata";
3320
               width = "1";
3321
               direction = "output";
3322
               Is_Enabled = "1";
3323
            }
3324
         }
3325
         SYSTEM_BUILDER_INFO
3326
         {
3327
            Has_IRQ = "1";
3328
            Bus_Type = "avalon";
3329
            Write_Wait_States = "1cycles";
3330
            Read_Wait_States = "1cycles";
3331
            Hold_Time = "0cycles";
3332
            Setup_Time = "0cycles";
3333
            Is_Printable_Device = "1";
3334
            Address_Alignment = "native";
3335
            Well_Behaved_Waitrequest = "0";
3336
            Is_Nonvolatile_Storage = "0";
3337
            Read_Latency = "0";
3338
            Is_Memory_Device = "0";
3339
            Maximum_Pending_Read_Transactions = "0";
3340
            Minimum_Uninterrupted_Run_Length = "1";
3341
            Accepts_Internal_Connections = "1";
3342
            Write_Latency = "0";
3343
            Is_Flash = "0";
3344
            Data_Width = "16";
3345
            Address_Width = "3";
3346
            Maximum_Burst_Size = "1";
3347
            Register_Incoming_Signals = "0";
3348
            Register_Outgoing_Signals = "0";
3349
            Interleave_Bursts = "0";
3350
            Linewrap_Bursts = "0";
3351
            Burst_On_Burst_Boundaries_Only = "0";
3352
            Always_Burst_Max_Burst = "0";
3353
            Is_Big_Endian = "0";
3354
            Is_Enabled = "1";
3355
            MASTERED_BY cpu_0/data_master
3356
            {
3357
               priority = "1";
3358
               Offset_Address = "0x00900040";
3359
            }
3360
            IRQ_MASTER cpu_0/data_master
3361
            {
3362
               IRQ_Number = "0";
3363
            }
3364
            Base_Address = "0x00900040";
3365
            Address_Group = "0";
3366
         }
3367
      }
3368
      PORT_WIRING
3369
      {
3370
         PORT rxd
3371
         {
3372
            type = "export";
3373
            width = "1";
3374
            direction = "input";
3375
            Is_Enabled = "1";
3376
         }
3377
         PORT txd
3378
         {
3379
            type = "export";
3380
            width = "1";
3381
            direction = "output";
3382
            Is_Enabled = "1";
3383
         }
3384
         PORT cts_n
3385
         {
3386
            direction = "input";
3387
            width = "1";
3388
            Is_Enabled = "0";
3389
         }
3390
         PORT rts_n
3391
         {
3392
            direction = "output";
3393
            width = "1";
3394
            Is_Enabled = "0";
3395
         }
3396
      }
3397
      class = "altera_avalon_uart";
3398
      class_version = "7.08";
3399
      iss_model_name = "altera_avalon_uart";
3400
      SYSTEM_BUILDER_INFO
3401
      {
3402
         Instantiate_In_System_Module = "1";
3403
         Is_Enabled = "1";
3404
         Iss_Launch_Telnet = "0";
3405
         Top_Level_Ports_Are_Enumerated = "1";
3406
         View
3407
         {
3408
            Settings_Summary = "8-bit UART with 115200 baud, 
3409
                    1 stop bits and N parity";
3410
            Is_Collapsed = "1";
3411
            MESSAGES
3412
            {
3413
            }
3414
         }
3415
         Clock_Source = "clk";
3416
         Has_Clock = "1";
3417
      }
3418
      SIMULATION
3419
      {
3420
         DISPLAY
3421
         {
3422
            SIGNAL a
3423
            {
3424
               name = "  Bus Interface";
3425
               format = "Divider";
3426
            }
3427
            SIGNAL b
3428
            {
3429
               name = "chipselect";
3430
            }
3431
            SIGNAL c
3432
            {
3433
               name = "address";
3434
               radix = "hexadecimal";
3435
            }
3436
            SIGNAL d
3437
            {
3438
               name = "writedata";
3439
               radix = "hexadecimal";
3440
            }
3441
            SIGNAL e
3442
            {
3443
               name = "readdata";
3444
               radix = "hexadecimal";
3445
            }
3446
            SIGNAL f
3447
            {
3448
               name = "  Internals";
3449
               format = "Divider";
3450
            }
3451
            SIGNAL g
3452
            {
3453
               name = "tx_ready";
3454
            }
3455
            SIGNAL h
3456
            {
3457
               name = "tx_data";
3458
               radix = "ascii";
3459
            }
3460
            SIGNAL i
3461
            {
3462
               name = "rx_char_ready";
3463
            }
3464
            SIGNAL j
3465
            {
3466
               name = "rx_data";
3467
               radix = "ascii";
3468
            }
3469
         }
3470
         INTERACTIVE_OUT log
3471
         {
3472
            enable = "0";
3473
            file = "_log_module.txt";
3474
            radix = "ascii";
3475
            signals = "temp,list";
3476
            exe = "perl -- tail-f.pl";
3477
         }
3478
         INTERACTIVE_IN drive
3479
         {
3480
            enable = "0";
3481
            file = "_input_data_stream.dat";
3482
            mutex = "_input_data_mutex.dat";
3483
            log = "_in.log";
3484
            rate = "100";
3485
            signals = "temp,list";
3486
            exe = "perl -- uart.pl";
3487
         }
3488
      }
3489
      WIZARD_SCRIPT_ARGUMENTS
3490
      {
3491
         baud = "115200";
3492
         data_bits = "8";
3493
         fixed_baud = "1";
3494
         parity = "N";
3495
         stop_bits = "1";
3496
         use_cts_rts = "0";
3497
         use_eop_register = "0";
3498
         sim_true_baud = "0";
3499
         sim_char_stream = "";
3500
      }
3501
      HDL_INFO
3502
      {
3503
         Precompiled_Simulation_Library_Files = "";
3504
         Simulation_HDL_Files = "";
3505
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/uart.vhd";
3506
         Synthesis_Only_Files = "";
3507
      }
3508
   }
3509
   MODULE LM74_Pio
3510
   {
3511
      SLAVE s1
3512
      {
3513
         PORT_WIRING
3514
         {
3515
            PORT clk
3516
            {
3517
               type = "clk";
3518
               width = "1";
3519
               direction = "input";
3520
               Is_Enabled = "1";
3521
            }
3522
            PORT reset_n
3523
            {
3524
               type = "reset_n";
3525
               width = "1";
3526
               direction = "input";
3527
               Is_Enabled = "1";
3528
            }
3529
            PORT address
3530
            {
3531
               type = "address";
3532
               width = "2";
3533
               direction = "input";
3534
               Is_Enabled = "1";
3535
            }
3536
            PORT write_n
3537
            {
3538
               type = "write_n";
3539
               width = "1";
3540
               direction = "input";
3541
               Is_Enabled = "1";
3542
            }
3543
            PORT writedata
3544
            {
3545
               type = "writedata";
3546
               width = "3";
3547
               direction = "input";
3548
               Is_Enabled = "1";
3549
            }
3550
            PORT chipselect
3551
            {
3552
               type = "chipselect";
3553
               width = "1";
3554
               direction = "input";
3555
               Is_Enabled = "1";
3556
            }
3557
            PORT readdata
3558
            {
3559
               type = "readdata";
3560
               width = "3";
3561
               direction = "output";
3562
               Is_Enabled = "1";
3563
            }
3564
         }
3565
         SYSTEM_BUILDER_INFO
3566
         {
3567
            Bus_Type = "avalon";
3568
            Write_Wait_States = "0cycles";
3569
            Read_Wait_States = "1cycles";
3570
            Hold_Time = "0cycles";
3571
            Setup_Time = "0cycles";
3572
            Is_Printable_Device = "0";
3573
            Address_Alignment = "native";
3574
            Well_Behaved_Waitrequest = "0";
3575
            Is_Nonvolatile_Storage = "0";
3576
            Read_Latency = "0";
3577
            Is_Memory_Device = "0";
3578
            Maximum_Pending_Read_Transactions = "0";
3579
            Minimum_Uninterrupted_Run_Length = "1";
3580
            Accepts_Internal_Connections = "1";
3581
            Write_Latency = "0";
3582
            Is_Flash = "0";
3583
            Data_Width = "3";
3584
            Address_Width = "2";
3585
            Maximum_Burst_Size = "1";
3586
            Register_Incoming_Signals = "0";
3587
            Register_Outgoing_Signals = "0";
3588
            Interleave_Bursts = "0";
3589
            Linewrap_Bursts = "0";
3590
            Burst_On_Burst_Boundaries_Only = "0";
3591
            Always_Burst_Max_Burst = "0";
3592
            Is_Big_Endian = "0";
3593
            Is_Enabled = "1";
3594
            MASTERED_BY cpu_0/data_master
3595
            {
3596
               priority = "1";
3597
               Offset_Address = "0x009000c0";
3598
            }
3599
            Base_Address = "0x009000c0";
3600
            Has_IRQ = "0";
3601
            Address_Group = "0";
3602
            IRQ_MASTER cpu_0/data_master
3603
            {
3604
               IRQ_Number = "NC";
3605
            }
3606
            Is_Readable = "1";
3607
            Is_Writable = "1";
3608
         }
3609
      }
3610
      PORT_WIRING
3611
      {
3612
         PORT bidir_port
3613
         {
3614
            type = "export";
3615
            width = "3";
3616
            direction = "inout";
3617
            Is_Enabled = "1";
3618
         }
3619
         PORT in_port
3620
         {
3621
            direction = "input";
3622
            Is_Enabled = "0";
3623
            width = "3";
3624
         }
3625
         PORT out_port
3626
         {
3627
            direction = "output";
3628
            Is_Enabled = "0";
3629
            width = "3";
3630
         }
3631
      }
3632
      class = "altera_avalon_pio";
3633
      class_version = "7.08";
3634
      SYSTEM_BUILDER_INFO
3635
      {
3636
         Is_Enabled = "1";
3637
         Instantiate_In_System_Module = "1";
3638
         Wire_Test_Bench_Values = "1";
3639
         Top_Level_Ports_Are_Enumerated = "1";
3640
         Clock_Source = "clk";
3641
         Has_Clock = "1";
3642
         Date_Modified = "";
3643
         View
3644
         {
3645
            MESSAGES
3646
            {
3647
            }
3648
            Settings_Summary = " 3-bit PIO using 
3649
                                         tri-state pins with edge type NONE and interrupt source NONE
3650
 
3651
                                        ";
3652
         }
3653
      }
3654
      WIZARD_SCRIPT_ARGUMENTS
3655
      {
3656
         Do_Test_Bench_Wiring = "0";
3657
         Driven_Sim_Value = "0";
3658
         has_tri = "1";
3659
         has_out = "0";
3660
         has_in = "0";
3661
         capture = "0";
3662
         Data_Width = "3";
3663
         reset_value = "0";
3664
         edge_type = "NONE";
3665
         irq_type = "NONE";
3666
         bit_clearing_edge_register = "0";
3667
      }
3668
      HDL_INFO
3669
      {
3670
         Precompiled_Simulation_Library_Files = "";
3671
         Simulation_HDL_Files = "";
3672
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/LM74_Pio.vhd";
3673
         Synthesis_Only_Files = "";
3674
      }
3675
   }
3676
   MODULE epcs_controller
3677
   {
3678
      SLAVE epcs_control_port
3679
      {
3680
         PORT_WIRING
3681
         {
3682
            PORT clk
3683
            {
3684
               type = "clk";
3685
               width = "1";
3686
               direction = "input";
3687
               Is_Enabled = "1";
3688
            }
3689
            PORT reset_n
3690
            {
3691
               type = "reset_n";
3692
               width = "1";
3693
               direction = "input";
3694
               Is_Enabled = "1";
3695
            }
3696
            PORT irq
3697
            {
3698
               type = "irq";
3699
               width = "1";
3700
               direction = "output";
3701
               Is_Enabled = "1";
3702
            }
3703
            PORT address
3704
            {
3705
               type = "address";
3706
               width = "9";
3707
               direction = "input";
3708
               Is_Enabled = "1";
3709
            }
3710
            PORT chipselect
3711
            {
3712
               type = "chipselect";
3713
               width = "1";
3714
               direction = "input";
3715
               Is_Enabled = "1";
3716
            }
3717
            PORT dataavailable
3718
            {
3719
               type = "dataavailable";
3720
               width = "1";
3721
               direction = "output";
3722
               Is_Enabled = "1";
3723
            }
3724
            PORT endofpacket
3725
            {
3726
               type = "endofpacket";
3727
               width = "1";
3728
               direction = "output";
3729
               Is_Enabled = "1";
3730
            }
3731
            PORT read_n
3732
            {
3733
               type = "read_n";
3734
               width = "1";
3735
               direction = "input";
3736
               Is_Enabled = "1";
3737
            }
3738
            PORT readdata
3739
            {
3740
               type = "readdata";
3741
               width = "32";
3742
               direction = "output";
3743
               Is_Enabled = "1";
3744
            }
3745
            PORT readyfordata
3746
            {
3747
               type = "readyfordata";
3748
               width = "1";
3749
               direction = "output";
3750
               Is_Enabled = "1";
3751
            }
3752
            PORT write_n
3753
            {
3754
               type = "write_n";
3755
               width = "1";
3756
               direction = "input";
3757
               Is_Enabled = "1";
3758
            }
3759
            PORT writedata
3760
            {
3761
               type = "writedata";
3762
               width = "32";
3763
               direction = "input";
3764
               Is_Enabled = "1";
3765
            }
3766
            PORT data_from_cpu
3767
            {
3768
               Is_Enabled = "0";
3769
               direction = "input";
3770
               type = "writedata";
3771
               width = "16";
3772
            }
3773
            PORT data_to_cpu
3774
            {
3775
               Is_Enabled = "0";
3776
               direction = "output";
3777
               type = "readdata";
3778
               width = "16";
3779
            }
3780
            PORT epcs_select
3781
            {
3782
               Is_Enabled = "0";
3783
               direction = "input";
3784
               type = "chipselect";
3785
               width = "1";
3786
            }
3787
            PORT mem_addr
3788
            {
3789
               Is_Enabled = "0";
3790
               direction = "input";
3791
               type = "address";
3792
               width = "3";
3793
            }
3794
         }
3795
         SYSTEM_BUILDER_INFO
3796
         {
3797
            Has_IRQ = "1";
3798
            Bus_Type = "avalon";
3799
            Write_Wait_States = "1cycles";
3800
            Read_Wait_States = "1cycles";
3801
            Hold_Time = "0cycles";
3802
            Setup_Time = "0cycles";
3803
            Is_Printable_Device = "0";
3804
            Address_Alignment = "dynamic";
3805
            Well_Behaved_Waitrequest = "0";
3806
            Is_Nonvolatile_Storage = "1";
3807
            Address_Span = "2048";
3808
            Read_Latency = "0";
3809
            Is_Memory_Device = "1";
3810
            Maximum_Pending_Read_Transactions = "0";
3811
            Minimum_Uninterrupted_Run_Length = "1";
3812
            Accepts_Internal_Connections = "1";
3813
            Write_Latency = "0";
3814
            Is_Flash = "1";
3815
            Data_Width = "32";
3816
            Address_Width = "9";
3817
            Maximum_Burst_Size = "1";
3818
            Register_Incoming_Signals = "0";
3819
            Register_Outgoing_Signals = "0";
3820
            Interleave_Bursts = "0";
3821
            Linewrap_Bursts = "0";
3822
            Burst_On_Burst_Boundaries_Only = "0";
3823
            Always_Burst_Max_Burst = "0";
3824
            Is_Big_Endian = "0";
3825
            Is_Enabled = "1";
3826
            MASTERED_BY cpu_0/instruction_master
3827
            {
3828
               priority = "1";
3829
               Offset_Address = "0x00906000";
3830
            }
3831
            MASTERED_BY cpu_0/data_master
3832
            {
3833
               priority = "1";
3834
               Offset_Address = "0x00906000";
3835
            }
3836
            IRQ_MASTER cpu_0/data_master
3837
            {
3838
               IRQ_Number = "2";
3839
            }
3840
            Base_Address = "0x00906000";
3841
            Address_Group = "0";
3842
         }
3843
         WIZARD_SCRIPT_ARGUMENTS
3844
         {
3845
            class = "altera_avalon_epcs_flash_controller";
3846
            flash_reference_designator = "";
3847
         }
3848
      }
3849
      PORT_WIRING
3850
      {
3851
         PORT dclk
3852
         {
3853
            type = "export";
3854
            width = "1";
3855
            direction = "output";
3856
            Is_Enabled = "1";
3857
         }
3858
         PORT sce
3859
         {
3860
            type = "export";
3861
            width = "1";
3862
            direction = "output";
3863
            Is_Enabled = "1";
3864
         }
3865
         PORT sdo
3866
         {
3867
            type = "export";
3868
            width = "1";
3869
            direction = "output";
3870
            Is_Enabled = "1";
3871
         }
3872
         PORT data0
3873
         {
3874
            type = "export";
3875
            width = "1";
3876
            direction = "input";
3877
            Is_Enabled = "1";
3878
         }
3879
      }
3880
      WIZARD_SCRIPT_ARGUMENTS
3881
      {
3882
         databits = "8";
3883
         targetclock = "20";
3884
         clockunits = "MHz";
3885
         clockmult = "1000000";
3886
         numslaves = "1";
3887
         ismaster = "1";
3888
         clockpolarity = "0";
3889
         clockphase = "0";
3890
         lsbfirst = "0";
3891
         extradelay = "0";
3892
         targetssdelay = "100";
3893
         delayunits = "us";
3894
         delaymult = "1e-006";
3895
         prefix = "epcs_";
3896
         register_offset = "0x400";
3897
         use_asmi_atom = "0";
3898
         MAKE
3899
         {
3900
            MACRO
3901
            {
3902
               EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1:0=)";
3903
               EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
3904
            }
3905
            MASTER cpu_0
3906
            {
3907
               MACRO
3908
               {
3909
                  BOOTS_FROM_EPCS = "0";
3910
                  BOOT_COPIER_EPCS = "boot_loader_epcs.srec";
3911
                  CPU_CLASS = "altera_nios2";
3912
                  CPU_RESET_ADDRESS = "0x0";
3913
               }
3914
            }
3915
            TARGET delete_placeholder_warning
3916
            {
3917
               epcs_controller
3918
               {
3919
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
3920
                  Is_Phony = "1";
3921
                  Target_File = "do_delete_placeholder_warning";
3922
               }
3923
            }
3924
            TARGET flashfiles
3925
            {
3926
               epcs_controller
3927
               {
3928
                  Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then echo Post-processing to create $(notdir $@) ; elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER_EPCS)$(DBL_QUOTE) --outfile=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --epcs --base=0x0 --end=0x7FFFFFFF  ; fi";
3929
                  Dependency = "$(ELF)";
3930
                  Target_File = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash";
3931
               }
3932
            }
3933
            TARGET sim
3934
            {
3935
               epcs_controller
3936
               {
3937
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
3938
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
3939
                  Command3 = "touch $(SIMDIR)/dummy_file";
3940
                  Dependency = "$(ELF)";
3941
                  Target_File = "$(SIMDIR)/dummy_file";
3942
               }
3943
            }
3944
         }
3945
         clockunit = "kHz";
3946
         delayunit = "us";
3947
      }
3948
      class = "altera_avalon_epcs_flash_controller";
3949
      class_version = "7.08";
3950
      SYSTEM_BUILDER_INFO
3951
      {
3952
         Is_Enabled = "1";
3953
         Clock_Source = "clk";
3954
         Has_Clock = "1";
3955
         Instantiate_In_System_Module = "1";
3956
         Required_Device_Family = "STRATIX,CYCLONE,CYCLONEII,CYCLONEIII,STRATIXIII,STRATIXII,STRATIXIIGX,ARRIAGX,STRATIXIIGXLITE";
3957
         Fixed_Module_Name = "epcs_controller";
3958
         Top_Level_Ports_Are_Enumerated = "1";
3959
         View
3960
         {
3961
            MESSAGES
3962
            {
3963
            }
3964
         }
3965
      }
3966
      HDL_INFO
3967
      {
3968
         Precompiled_Simulation_Library_Files = "";
3969
         Simulation_HDL_Files = "";
3970
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/epcs_controller.vhd";
3971
         Synthesis_Only_Files = "";
3972
      }
3973
   }
3974
   MODULE tri_state_bridge_0
3975
   {
3976
      SLAVE avalon_slave
3977
      {
3978
         PORT_WIRING
3979
         {
3980
         }
3981
         SYSTEM_BUILDER_INFO
3982
         {
3983
            Bus_Type = "avalon";
3984
            Write_Wait_States = "0cycles";
3985
            Read_Wait_States = "1cycles";
3986
            Hold_Time = "0cycles";
3987
            Setup_Time = "0cycles";
3988
            Is_Printable_Device = "0";
3989
            Address_Alignment = "dynamic";
3990
            Well_Behaved_Waitrequest = "0";
3991
            Is_Nonvolatile_Storage = "0";
3992
            Address_Span = "1";
3993
            Read_Latency = "0";
3994
            Is_Memory_Device = "0";
3995
            Maximum_Pending_Read_Transactions = "0";
3996
            Minimum_Uninterrupted_Run_Length = "1";
3997
            Accepts_Internal_Connections = "1";
3998
            Write_Latency = "0";
3999
            Is_Flash = "0";
4000
            Maximum_Burst_Size = "1";
4001
            Register_Incoming_Signals = "1";
4002
            Register_Outgoing_Signals = "1";
4003
            Interleave_Bursts = "0";
4004
            Linewrap_Bursts = "0";
4005
            Burst_On_Burst_Boundaries_Only = "0";
4006
            Always_Burst_Max_Burst = "0";
4007
            Is_Big_Endian = "0";
4008
            Is_Enabled = "1";
4009
            MASTERED_BY cpu_0/data_master
4010
            {
4011
               priority = "1";
4012
               Offset_Address = "0x00000000";
4013
            }
4014
            MASTERED_BY cpu_0/instruction_master
4015
            {
4016
               priority = "1";
4017
               Offset_Address = "0x00000000";
4018
            }
4019
            MASTERED_BY nios_vga_inst/vga_dma
4020
            {
4021
               priority = "1";
4022
               Offset_Address = "0x00000000";
4023
            }
4024
            Bridges_To = "tristate_master";
4025
            Base_Address = "N/A";
4026
            Has_IRQ = "0";
4027
            IRQ = "N/A";
4028
            Address_Group = "0";
4029
            IRQ_MASTER cpu_0/data_master
4030
            {
4031
               IRQ_Number = "NC";
4032
            }
4033
         }
4034
      }
4035
      MASTER tristate_master
4036
      {
4037
         SYSTEM_BUILDER_INFO
4038
         {
4039
            Bus_Type = "avalon_tristate";
4040
            Is_Asynchronous = "0";
4041
            DBS_Big_Endian = "0";
4042
            Adapts_To = "";
4043
            Maximum_Burst_Size = "1";
4044
            Register_Incoming_Signals = "0";
4045
            Register_Outgoing_Signals = "0";
4046
            Interleave_Bursts = "0";
4047
            Linewrap_Bursts = "0";
4048
            Burst_On_Burst_Boundaries_Only = "0";
4049
            Always_Burst_Max_Burst = "0";
4050
            Is_Big_Endian = "0";
4051
            Is_Enabled = "1";
4052
            Bridges_To = "avalon_slave";
4053
         }
4054
         PORT_WIRING
4055
         {
4056
         }
4057
         MEMORY_MAP
4058
         {
4059
            Entry cfi_flash/s1
4060
            {
4061
               address = "0x00000000";
4062
               span = "0x00800000";
4063
               is_bridge = "0";
4064
            }
4065
            Entry DBC3C40_SRAM_inst/avalon_tristate_slave
4066
            {
4067
               address = "0x00800000";
4068
               span = "0x00100000";
4069
               is_bridge = "0";
4070
            }
4071
         }
4072
      }
4073
      WIZARD_SCRIPT_ARGUMENTS
4074
      {
4075
      }
4076
      class = "altera_avalon_tri_state_bridge";
4077
      class_version = "7.08";
4078
      SYSTEM_BUILDER_INFO
4079
      {
4080
         Is_Enabled = "1";
4081
         Clock_Source = "clk";
4082
         Has_Clock = "1";
4083
         Instantiate_In_System_Module = "1";
4084
         Is_Bridge = "1";
4085
         Top_Level_Ports_Are_Enumerated = "1";
4086
         View
4087
         {
4088
            MESSAGES
4089
            {
4090
            }
4091
         }
4092
      }
4093
   }
4094
   MODULE sys_clk
4095
   {
4096
      SLAVE s1
4097
      {
4098
         PORT_WIRING
4099
         {
4100
            PORT clk
4101
            {
4102
               type = "clk";
4103
               width = "1";
4104
               direction = "input";
4105
               Is_Enabled = "1";
4106
            }
4107
            PORT reset_n
4108
            {
4109
               type = "reset_n";
4110
               width = "1";
4111
               direction = "input";
4112
               Is_Enabled = "1";
4113
            }
4114
            PORT irq
4115
            {
4116
               type = "irq";
4117
               width = "1";
4118
               direction = "output";
4119
               Is_Enabled = "1";
4120
            }
4121
            PORT address
4122
            {
4123
               type = "address";
4124
               width = "3";
4125
               direction = "input";
4126
               Is_Enabled = "1";
4127
            }
4128
            PORT writedata
4129
            {
4130
               type = "writedata";
4131
               width = "16";
4132
               direction = "input";
4133
               Is_Enabled = "1";
4134
            }
4135
            PORT readdata
4136
            {
4137
               type = "readdata";
4138
               width = "16";
4139
               direction = "output";
4140
               Is_Enabled = "1";
4141
            }
4142
            PORT chipselect
4143
            {
4144
               type = "chipselect";
4145
               width = "1";
4146
               direction = "input";
4147
               Is_Enabled = "1";
4148
            }
4149
            PORT write_n
4150
            {
4151
               type = "write_n";
4152
               width = "1";
4153
               direction = "input";
4154
               Is_Enabled = "1";
4155
            }
4156
         }
4157
         SYSTEM_BUILDER_INFO
4158
         {
4159
            Has_IRQ = "1";
4160
            Bus_Type = "avalon";
4161
            Write_Wait_States = "0cycles";
4162
            Read_Wait_States = "1cycles";
4163
            Hold_Time = "0cycles";
4164
            Setup_Time = "0cycles";
4165
            Is_Printable_Device = "0";
4166
            Address_Alignment = "native";
4167
            Well_Behaved_Waitrequest = "0";
4168
            Is_Nonvolatile_Storage = "0";
4169
            Read_Latency = "0";
4170
            Is_Memory_Device = "0";
4171
            Maximum_Pending_Read_Transactions = "0";
4172
            Minimum_Uninterrupted_Run_Length = "1";
4173
            Accepts_Internal_Connections = "1";
4174
            Write_Latency = "0";
4175
            Is_Flash = "0";
4176
            Data_Width = "16";
4177
            Address_Width = "3";
4178
            Maximum_Burst_Size = "1";
4179
            Register_Incoming_Signals = "0";
4180
            Register_Outgoing_Signals = "0";
4181
            Interleave_Bursts = "0";
4182
            Linewrap_Bursts = "0";
4183
            Burst_On_Burst_Boundaries_Only = "0";
4184
            Always_Burst_Max_Burst = "0";
4185
            Is_Big_Endian = "0";
4186
            Is_Enabled = "1";
4187
            MASTERED_BY cpu_0/data_master
4188
            {
4189
               priority = "1";
4190
               Offset_Address = "0x00900060";
4191
            }
4192
            IRQ_MASTER cpu_0/data_master
4193
            {
4194
               IRQ_Number = "3";
4195
            }
4196
            Base_Address = "0x00900060";
4197
            Address_Group = "0";
4198
         }
4199
      }
4200
      class = "altera_avalon_timer";
4201
      class_version = "7.08";
4202
      iss_model_name = "altera_avalon_timer";
4203
      SYSTEM_BUILDER_INFO
4204
      {
4205
         Instantiate_In_System_Module = "1";
4206
         Is_Enabled = "1";
4207
         Top_Level_Ports_Are_Enumerated = "1";
4208
         View
4209
         {
4210
            Settings_Summary = "Timer with 1 ms timeout period.";
4211
            Is_Collapsed = "1";
4212
            MESSAGES
4213
            {
4214
            }
4215
         }
4216
         Clock_Source = "clk";
4217
         Has_Clock = "1";
4218
      }
4219
      WIZARD_SCRIPT_ARGUMENTS
4220
      {
4221
         always_run = "0";
4222
         fixed_period = "0";
4223
         snapshot = "1";
4224
         period = "1.0";
4225
         period_units = "ms";
4226
         reset_output = "0";
4227
         timeout_pulse_output = "0";
4228
         load_value = "74999";
4229
         counter_size = "32";
4230
         mult = "0.0010";
4231
         ticks_per_sec = "1000";
4232
      }
4233
      HDL_INFO
4234
      {
4235
         Precompiled_Simulation_Library_Files = "";
4236
         Simulation_HDL_Files = "";
4237
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/sys_clk.vhd";
4238
         Synthesis_Only_Files = "";
4239
      }
4240
      PORT_WIRING
4241
      {
4242
      }
4243
   }
4244
   MODULE cfi_flash
4245
   {
4246
      SLAVE s1
4247
      {
4248
         PORT_WIRING
4249
         {
4250
            PORT data
4251
            {
4252
               type = "data";
4253
               width = "16";
4254
               direction = "inout";
4255
               Is_Enabled = "1";
4256
               is_shared = "1";
4257
            }
4258
            PORT address
4259
            {
4260
               type = "address";
4261
               width = "22";
4262
               direction = "input";
4263
               Is_Enabled = "1";
4264
               is_shared = "1";
4265
            }
4266
            PORT read_n
4267
            {
4268
               type = "read_n";
4269
               width = "1";
4270
               direction = "input";
4271
               Is_Enabled = "1";
4272
               is_shared = "1";
4273
            }
4274
            PORT write_n
4275
            {
4276
               type = "write_n";
4277
               width = "1";
4278
               direction = "input";
4279
               Is_Enabled = "1";
4280
               is_shared = "1";
4281
            }
4282
            PORT select_n
4283
            {
4284
               type = "chipselect_n";
4285
               width = "1";
4286
               direction = "input";
4287
               Is_Enabled = "1";
4288
               is_shared = "0";
4289
            }
4290
         }
4291
         SYSTEM_BUILDER_INFO
4292
         {
4293
            Bus_Type = "avalon_tristate";
4294
            Write_Wait_States = "100ns";
4295
            Read_Wait_States = "100ns";
4296
            Hold_Time = "20ns";
4297
            Setup_Time = "20ns";
4298
            Is_Printable_Device = "0";
4299
            Address_Alignment = "dynamic";
4300
            Well_Behaved_Waitrequest = "0";
4301
            Is_Nonvolatile_Storage = "1";
4302
            Address_Span = "8388608";
4303
            Read_Latency = "0";
4304
            Is_Memory_Device = "1";
4305
            Maximum_Pending_Read_Transactions = "0";
4306
            Minimum_Uninterrupted_Run_Length = "1";
4307
            Accepts_Internal_Connections = "1";
4308
            Write_Latency = "0";
4309
            Is_Flash = "1";
4310
            Active_CS_Through_Read_Latency = "0";
4311
            Data_Width = "16";
4312
            Address_Width = "22";
4313
            Maximum_Burst_Size = "1";
4314
            Register_Incoming_Signals = "0";
4315
            Register_Outgoing_Signals = "0";
4316
            Interleave_Bursts = "0";
4317
            Linewrap_Bursts = "0";
4318
            Burst_On_Burst_Boundaries_Only = "0";
4319
            Always_Burst_Max_Burst = "0";
4320
            Is_Big_Endian = "0";
4321
            Is_Enabled = "1";
4322
            MASTERED_BY tri_state_bridge_0/tristate_master
4323
            {
4324
               priority = "1";
4325
               Offset_Address = "0x00000000";
4326
            }
4327
            Base_Address = "0x00000000";
4328
            Has_IRQ = "0";
4329
            Simulation_Num_Lanes = "1";
4330
            Convert_Xs_To_0 = "1";
4331
            Address_Group = "0";
4332
            IRQ_MASTER cpu_0/data_master
4333
            {
4334
               IRQ_Number = "NC";
4335
            }
4336
         }
4337
         WIZARD_SCRIPT_ARGUMENTS
4338
         {
4339
            class = "altera_avalon_cfi_flash";
4340
            Supports_Flash_File_System = "1";
4341
            flash_reference_designator = "";
4342
         }
4343
      }
4344
      WIZARD_SCRIPT_ARGUMENTS
4345
      {
4346
         Setup_Value = "20";
4347
         Wait_Value = "100";
4348
         Hold_Value = "20";
4349
         Timing_Units = "ns";
4350
         Unit_Multiplier = "1";
4351
         Size = "8388608";
4352
         MAKE
4353
         {
4354
            MACRO
4355
            {
4356
               CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX = "$(CFI_FLASH_FLASHTARGET_TMP1:0=)";
4357
               CFI_FLASH_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
4358
            }
4359
            MASTER cpu_0
4360
            {
4361
               MACRO
4362
               {
4363
                  BOOT_COPIER = "boot_loader_cfi.srec";
4364
                  CPU_CLASS = "altera_nios2";
4365
                  CPU_RESET_ADDRESS = "0x0";
4366
               }
4367
            }
4368
            TARGET delete_placeholder_warning
4369
            {
4370
               cfi_flash
4371
               {
4372
                  Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
4373
                  Is_Phony = "1";
4374
                  Target_File = "do_delete_placeholder_warning";
4375
               }
4376
            }
4377
            TARGET flashfiles
4378
            {
4379
               cfi_flash
4380
               {
4381
                  Command1 = "@echo Post-processing to create $(notdir $@)";
4382
                  Command2 = "elf2flash --input=$(ELF) --flash= --boot=$(DBL_QUOTE)$(shell $(DBL_QUOTE)$(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir$(DBL_QUOTE) $(CPU_CLASS) $(QUARTUS_PROJECT_DIR))/$(BOOT_COPIER)$(DBL_QUOTE) --outfile=$(CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --base=0x0 --end=0x7FFFFF --reset=$(CPU_RESET_ADDRESS) ";
4383
                  Dependency = "$(ELF)";
4384
                  Target_File = "$(CFI_FLASH_FLASHTARGET_ALT_SIM_PREFIX)cfi_flash.flash";
4385
               }
4386
            }
4387
            TARGET sim
4388
            {
4389
               cfi_flash
4390
               {
4391
                  Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
4392
                  Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
4393
                  Command3 = "touch $(SIMDIR)/dummy_file";
4394
                  Dependency = "$(ELF)";
4395
                  Target_File = "$(SIMDIR)/dummy_file";
4396
               }
4397
            }
4398
         }
4399
      }
4400
      SYSTEM_BUILDER_INFO
4401
      {
4402
         Simulation_Num_Lanes = "2";
4403
         Is_Enabled = "1";
4404
         Clock_Source = "clk";
4405
         Has_Clock = "1";
4406
         Make_Memory_Model = "1";
4407
         Instantiate_In_System_Module = "0";
4408
         Top_Level_Ports_Are_Enumerated = "1";
4409
         View
4410
         {
4411
            MESSAGES
4412
            {
4413
            }
4414
         }
4415
      }
4416
      class = "altera_avalon_cfi_flash";
4417
      class_version = "7.08";
4418
      iss_model_name = "altera_avalon_flash";
4419
      HDL_INFO
4420
      {
4421
      }
4422
   }
4423
   MODULE nios_vga_inst
4424
   {
4425
      MASTER vga_dma
4426
      {
4427
         PORT_WIRING
4428
         {
4429
            PORT cpu_clk
4430
            {
4431
               type = "clk";
4432
               width = "1";
4433
               direction = "input";
4434
               Is_Enabled = "1";
4435
            }
4436
            PORT rst_n
4437
            {
4438
               type = "reset_n";
4439
               width = "1";
4440
               direction = "input";
4441
               Is_Enabled = "1";
4442
            }
4443
            PORT ram_in
4444
            {
4445
               type = "readdata";
4446
               width = "32";
4447
               direction = "input";
4448
               Is_Enabled = "1";
4449
            }
4450
            PORT wait_st
4451
            {
4452
               type = "waitrequest";
4453
               width = "1";
4454
               direction = "input";
4455
               Is_Enabled = "1";
4456
            }
4457
            PORT ram_cs
4458
            {
4459
               type = "chipselect";
4460
               width = "1";
4461
               direction = "output";
4462
               Is_Enabled = "1";
4463
            }
4464
            PORT ram_wr
4465
            {
4466
               type = "write";
4467
               width = "1";
4468
               direction = "output";
4469
               Is_Enabled = "1";
4470
            }
4471
            PORT ram_rd
4472
            {
4473
               type = "read";
4474
               width = "1";
4475
               direction = "output";
4476
               Is_Enabled = "1";
4477
            }
4478
            PORT ram_addr
4479
            {
4480
               type = "address";
4481
               width = "26";
4482
               direction = "output";
4483
               Is_Enabled = "1";
4484
            }
4485
            PORT ram_out
4486
            {
4487
               type = "writedata";
4488
               width = "32";
4489
               direction = "output";
4490
               Is_Enabled = "1";
4491
            }
4492
         }
4493
         SYSTEM_BUILDER_INFO
4494
         {
4495
            Bus_Type = "avalon";
4496
            Is_Asynchronous = "0";
4497
            DBS_Big_Endian = "0";
4498
            Adapts_To = "";
4499
            Do_Stream_Reads = "0";
4500
            Do_Stream_Writes = "0";
4501
            Max_Address_Width = "32";
4502
            Data_Width = "32";
4503
            Address_Width = "26";
4504
            Maximum_Burst_Size = "1";
4505
            Register_Incoming_Signals = "0";
4506
            Register_Outgoing_Signals = "0";
4507
            Interleave_Bursts = "0";
4508
            Linewrap_Bursts = "0";
4509
            Burst_On_Burst_Boundaries_Only = "0";
4510
            Always_Burst_Max_Burst = "0";
4511
            Is_Big_Endian = "0";
4512
            Is_Enabled = "1";
4513
         }
4514
         MEMORY_MAP
4515
         {
4516
            Entry cfi_flash/s1
4517
            {
4518
               address = "0x00000000";
4519
               span = "0x00800000";
4520
               is_bridge = "0";
4521
            }
4522
            Entry DBC3C40_SRAM_inst/avalon_tristate_slave
4523
            {
4524
               address = "0x00800000";
4525
               span = "0x00100000";
4526
               is_bridge = "0";
4527
            }
4528
         }
4529
      }
4530
      SLAVE vga_regs
4531
      {
4532
         SYSTEM_BUILDER_INFO
4533
         {
4534
            Bus_Type = "avalon";
4535
            Write_Wait_States = "1cycles";
4536
            Read_Wait_States = "1cycles";
4537
            Hold_Time = "0cycles";
4538
            Setup_Time = "0cycles";
4539
            Is_Printable_Device = "0";
4540
            Address_Alignment = "native";
4541
            Well_Behaved_Waitrequest = "0";
4542
            Is_Nonvolatile_Storage = "0";
4543
            Read_Latency = "0";
4544
            Is_Memory_Device = "0";
4545
            Maximum_Pending_Read_Transactions = "0";
4546
            Minimum_Uninterrupted_Run_Length = "1";
4547
            Accepts_Internal_Connections = "1";
4548
            Write_Latency = "0";
4549
            Is_Flash = "0";
4550
            Data_Width = "32";
4551
            Address_Width = "4";
4552
            Maximum_Burst_Size = "1";
4553
            Register_Incoming_Signals = "0";
4554
            Register_Outgoing_Signals = "0";
4555
            Interleave_Bursts = "0";
4556
            Linewrap_Bursts = "0";
4557
            Burst_On_Burst_Boundaries_Only = "0";
4558
            Always_Burst_Max_Burst = "0";
4559
            Is_Big_Endian = "0";
4560
            Is_Enabled = "1";
4561
            MASTERED_BY cpu_0/data_master
4562
            {
4563
               priority = "1";
4564
               Offset_Address = "0x00900000";
4565
            }
4566
            Base_Address = "0x00900000";
4567
            Address_Group = "0";
4568
            IRQ_MASTER cpu_0/data_master
4569
            {
4570
               IRQ_Number = "NC";
4571
            }
4572
         }
4573
         PORT_WIRING
4574
         {
4575
            PORT cpu_cs
4576
            {
4577
               type = "chipselect";
4578
               width = "1";
4579
               direction = "input";
4580
               Is_Enabled = "1";
4581
            }
4582
            PORT cpu_wr
4583
            {
4584
               type = "write";
4585
               width = "1";
4586
               direction = "input";
4587
               Is_Enabled = "1";
4588
            }
4589
            PORT cpu_addr
4590
            {
4591
               type = "address";
4592
               width = "4";
4593
               direction = "input";
4594
               Is_Enabled = "1";
4595
            }
4596
            PORT cpu_in
4597
            {
4598
               type = "writedata";
4599
               width = "32";
4600
               direction = "input";
4601
               Is_Enabled = "1";
4602
            }
4603
            PORT cpu_out
4604
            {
4605
               type = "readdata";
4606
               width = "32";
4607
               direction = "output";
4608
               Is_Enabled = "1";
4609
            }
4610
         }
4611
      }
4612
      PORT_WIRING
4613
      {
4614
         PORT r
4615
         {
4616
            type = "export";
4617
            width = "8";
4618
            direction = "output";
4619
            Is_Enabled = "1";
4620
         }
4621
         PORT g
4622
         {
4623
            type = "export";
4624
            width = "8";
4625
            direction = "output";
4626
            Is_Enabled = "1";
4627
         }
4628
         PORT b
4629
         {
4630
            type = "export";
4631
            width = "8";
4632
            direction = "output";
4633
            Is_Enabled = "1";
4634
         }
4635
         PORT hs
4636
         {
4637
            type = "export";
4638
            width = "1";
4639
            direction = "output";
4640
            Is_Enabled = "1";
4641
         }
4642
         PORT vs
4643
         {
4644
            type = "export";
4645
            width = "1";
4646
            direction = "output";
4647
            Is_Enabled = "1";
4648
         }
4649
         PORT m1
4650
         {
4651
            type = "export";
4652
            width = "1";
4653
            direction = "output";
4654
            Is_Enabled = "1";
4655
         }
4656
         PORT m2
4657
         {
4658
            type = "export";
4659
            width = "1";
4660
            direction = "output";
4661
            Is_Enabled = "1";
4662
         }
4663
         PORT blank_n
4664
         {
4665
            type = "export";
4666
            width = "1";
4667
            direction = "output";
4668
            Is_Enabled = "1";
4669
         }
4670
         PORT sync_n
4671
         {
4672
            type = "export";
4673
            width = "1";
4674
            direction = "output";
4675
            Is_Enabled = "1";
4676
         }
4677
         PORT sync_t
4678
         {
4679
            type = "export";
4680
            width = "1";
4681
            direction = "output";
4682
            Is_Enabled = "1";
4683
         }
4684
         PORT lcd_reg
4685
         {
4686
            type = "export";
4687
            width = "3";
4688
            direction = "output";
4689
            Is_Enabled = "1";
4690
         }
4691
         PORT video_clk
4692
         {
4693
            type = "export";
4694
            width = "1";
4695
            direction = "input";
4696
            Is_Enabled = "1";
4697
         }
4698
      }
4699
      class = "no_legacy_module";
4700
      class_version = "7.08";
4701
      gtf_class_name = "nios_vga";
4702
      gtf_class_version = "1.0.1";
4703
      SYSTEM_BUILDER_INFO
4704
      {
4705
         Do_Not_Generate = "1";
4706
         Instantiate_In_System_Module = "1";
4707
         Is_Enabled = "1";
4708
         Clock_Source = "clk";
4709
         Has_Clock = "1";
4710
         View
4711
         {
4712
            MESSAGES
4713
            {
4714
            }
4715
         }
4716
      }
4717
      HDL_INFO
4718
      {
4719
         Simulation_HDL_Files = "__PROJECT_DIRECTORY__/nios_vga_inst.vhd";
4720
      }
4721
      WIZARD_SCRIPT_ARGUMENTS
4722
      {
4723
         terminated_ports
4724
         {
4725
         }
4726
      }
4727
   }
4728
   MODULE DBC3C40_SRAM_inst
4729
   {
4730
      SLAVE avalon_tristate_slave
4731
      {
4732
         SYSTEM_BUILDER_INFO
4733
         {
4734
            Bus_Type = "avalon_tristate";
4735
            Write_Wait_States = "1cycles";
4736
            Read_Wait_States = "1cycles";
4737
            Hold_Time = "1cycles";
4738
            Setup_Time = "0cycles";
4739
            Is_Printable_Device = "0";
4740
            Address_Alignment = "dynamic";
4741
            Well_Behaved_Waitrequest = "0";
4742
            Is_Nonvolatile_Storage = "0";
4743
            Address_Span = "1048576";
4744
            Read_Latency = "0";
4745
            Is_Memory_Device = "1";
4746
            Maximum_Pending_Read_Transactions = "0";
4747
            Minimum_Uninterrupted_Run_Length = "1";
4748
            Accepts_Internal_Connections = "1";
4749
            Write_Latency = "0";
4750
            Is_Flash = "0";
4751
            Active_CS_Through_Read_Latency = "0";
4752
            Data_Width = "16";
4753
            Address_Width = "19";
4754
            Maximum_Burst_Size = "1";
4755
            Register_Incoming_Signals = "0";
4756
            Register_Outgoing_Signals = "0";
4757
            Interleave_Bursts = "0";
4758
            Linewrap_Bursts = "0";
4759
            Burst_On_Burst_Boundaries_Only = "0";
4760
            Always_Burst_Max_Burst = "0";
4761
            Is_Big_Endian = "0";
4762
            Is_Enabled = "1";
4763
            MASTERED_BY tri_state_bridge_0/tristate_master
4764
            {
4765
               priority = "1";
4766
               Offset_Address = "0x00800000";
4767
            }
4768
            Base_Address = "0x00800000";
4769
            Address_Group = "0";
4770
            IRQ_MASTER cpu_0/data_master
4771
            {
4772
               IRQ_Number = "NC";
4773
            }
4774
         }
4775
         PORT_WIRING
4776
         {
4777
            PORT addr
4778
            {
4779
               type = "address";
4780
               width = "19";
4781
               direction = "input";
4782
               Is_Enabled = "1";
4783
               is_shared = "1";
4784
            }
4785
            PORT data
4786
            {
4787
               type = "data";
4788
               width = "16";
4789
               direction = "inout";
4790
               Is_Enabled = "1";
4791
               is_shared = "1";
4792
            }
4793
            PORT ncs
4794
            {
4795
               type = "chipselect_n";
4796
               width = "1";
4797
               direction = "input";
4798
               Is_Enabled = "1";
4799
               is_shared = "0";
4800
            }
4801
            PORT wrn
4802
            {
4803
               type = "write_n";
4804
               width = "1";
4805
               direction = "input";
4806
               Is_Enabled = "1";
4807
               is_shared = "1";
4808
            }
4809
            PORT rdn
4810
            {
4811
               type = "read_n";
4812
               width = "1";
4813
               direction = "input";
4814
               Is_Enabled = "1";
4815
               is_shared = "1";
4816
            }
4817
            PORT ben
4818
            {
4819
               type = "byteenable_n";
4820
               width = "2";
4821
               direction = "input";
4822
               Is_Enabled = "1";
4823
               is_shared = "1";
4824
            }
4825
         }
4826
      }
4827
      class = "no_legacy_module";
4828
      class_version = "7.08";
4829
      gtf_class_name = "DBC3C40_SRAM";
4830
      gtf_class_version = "1.0";
4831
      SYSTEM_BUILDER_INFO
4832
      {
4833
         Do_Not_Generate = "1";
4834
         Instantiate_In_System_Module = "0";
4835
         Is_Enabled = "1";
4836
         Clock_Source = "clk";
4837
         View
4838
         {
4839
            MESSAGES
4840
            {
4841
            }
4842
         }
4843
      }
4844
      HDL_INFO
4845
      {
4846
         Simulation_HDL_Files = "";
4847
      }
4848
      WIZARD_SCRIPT_ARGUMENTS
4849
      {
4850
         terminated_ports
4851
         {
4852
         }
4853
      }
4854
   }
4855
}

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