OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [board.h] - Blame information for rev 773

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 584 jeremybenn
#ifndef _BOARD_H_
2
#define _BOARD_H_
3
 
4
#define MC_ENABLED          0
5
 
6 623 filepang
#define IC_ENABLE           0
7 584 jeremybenn
#define IC_SIZE         8192
8 623 filepang
#define DC_ENABLE           0
9 584 jeremybenn
#define DC_SIZE         8192
10
 
11
#define SYS_CLK                 25000000
12
#define IN_CLK              25000000
13
 
14 623 filepang
//#define UART_NUM_CORES        2
15
#undef  UART_NUM_CORES
16 584 jeremybenn
 
17 623 filepang
#define UART0_BAUD_RATE 115200
18
#define UART0_BASE              0x90000000
19
#define UART0_IRQ               2
20 584 jeremybenn
 
21 623 filepang
//#define GPIO_NUM_CORES        2
22
#undef  GPIO_NUM_CORES
23 584 jeremybenn
 
24 623 filepang
#define GPIO0_BASE              0x91000000
25
#define GPIO0_IRQ               3
26
 
27 584 jeremybenn
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.