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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [cache.c] - Blame information for rev 799

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1 799 filepang 
/*
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 * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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 * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 of
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 * the License, or (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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 * MA 02111-1307 USA
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 */
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/*
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 * copied from u-boot for OpenRISC
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 */
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#include "spr_defs.h"
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#include "support.h"
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void flush_dcache_range(unsigned long addr, unsigned long stop)
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{
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        unsigned long block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
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        while (addr < stop) {
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                mtspr(SPR_DCBFR, addr);
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                addr += block_size;
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        }
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}
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void invalidate_dcache_range(unsigned long addr, unsigned long stop)
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{
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        unsigned long block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
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        while (addr < stop) {
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                mtspr(SPR_DCBIR, addr);
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                addr += block_size;
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        }
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}
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static void invalidate_icache_range(unsigned long addr, unsigned long stop)
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{
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        unsigned long block_size = (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16;
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        unsigned long ie = icache_status();
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        icache_disable();
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        while (addr < stop) {
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                mtspr(SPR_ICBIR, addr);
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                addr += block_size;
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        }
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        if (ie)
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                icache_enable();
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}
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void flush_cache(unsigned long addr, unsigned long size)
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{
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        flush_dcache_range(addr, addr + size);
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        invalidate_icache_range(addr, addr + size);
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}
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int icache_status(void)
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{
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        return mfspr(SPR_SR) & SPR_SR_ICE;
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}
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int checkicache(void)
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{
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        unsigned long iccfgr;
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        unsigned long cache_set_size;
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        unsigned long cache_ways;
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        unsigned long cache_block_size;
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        iccfgr = mfspr(SPR_ICCFGR);
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        cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
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        cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
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        cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
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        return cache_set_size * cache_ways * cache_block_size;
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}
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int dcache_status(void)
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{
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        return mfspr(SPR_SR) & SPR_SR_DCE;
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}
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int checkdcache(void)
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{
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        unsigned long dccfgr;
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        unsigned long cache_set_size;
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        unsigned long cache_ways;
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        unsigned long cache_block_size;
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        dccfgr = mfspr(SPR_DCCFGR);
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        cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
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        cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
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        cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
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        return cache_set_size * cache_ways * cache_block_size;
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}
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void dcache_enable(void)
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{
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        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
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        asm volatile("l.nop");
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        asm volatile("l.nop");
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        asm volatile("l.nop");
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        asm volatile("l.nop");
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        asm volatile("l.nop");
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        asm volatile("l.nop");
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        asm volatile("l.nop");
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        asm volatile("l.nop");
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}
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void dcache_disable(void)
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{
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        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE);
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}
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void icache_enable(void)
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{
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        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_ICE);
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        asm volatile("l.nop");
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        asm volatile("l.nop");
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        asm volatile("l.nop");
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        asm volatile("l.nop");
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        asm volatile("l.nop");
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        asm volatile("l.nop");
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        asm volatile("l.nop");
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        asm volatile("l.nop");
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}
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void icache_disable(void)
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{
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        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE);
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}
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int cache_init(void)
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{
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        if (mfspr(SPR_UPR) & SPR_UPR_ICP) {
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                icache_disable();
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                invalidate_icache_range(0, checkicache());
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                icache_enable();
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        }
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        if (mfspr(SPR_UPR) & SPR_UPR_DCP) {
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                dcache_disable();
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                invalidate_dcache_range(0, checkdcache());
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                dcache_enable();
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        }
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        return 0;
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}

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