OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [cache.c] - Blame information for rev 831

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 799 filepang 
/*
2 
 * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
3 
 * (C) Copyright 2011, Julius Baxter <julius@opencores.org>
4 
 *
5 
 * This program is free software; you can redistribute it and/or
6 
 * modify it under the terms of the GNU General Public License as
7 
 * published by the Free Software Foundation; either version 2 of
8 
 * the License, or (at your option) any later version.
9 
 *
10 
 * This program is distributed in the hope that it will be useful,
11 
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13 
 * GNU General Public License for more details.
14 
 *
15 
 * You should have received a copy of the GNU General Public License
16 
 * along with this program; if not, write to the Free Software
17 
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 
 * MA 02111-1307 USA
19 
 */
20 
 
21 
/*
22 
 * copied from u-boot for OpenRISC
23 
 */
24 
 
25 
#include "spr_defs.h"
26 
#include "support.h"
27 
 
28 
void flush_dcache_range(unsigned long addr, unsigned long stop)
29 
{
30 
        unsigned long block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
31 
 
32 
        while (addr < stop) {
33 
                mtspr(SPR_DCBFR, addr);
34 
                addr += block_size;
35 
        }
36 
}
37 
 
38 
void invalidate_dcache_range(unsigned long addr, unsigned long stop)
39 
{
40 
        unsigned long block_size = (mfspr(SPR_DCCFGR) & SPR_DCCFGR_CBS) ? 32 : 16;
41 
 
42 
        while (addr < stop) {
43 
                mtspr(SPR_DCBIR, addr);
44 
                addr += block_size;
45 
        }
46 
}
47 
 
48 
static void invalidate_icache_range(unsigned long addr, unsigned long stop)
49 
{
50 
        unsigned long block_size = (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16;
51 
        unsigned long ie = icache_status();
52 
 
53 
        icache_disable();
54 
        while (addr < stop) {
55 
                mtspr(SPR_ICBIR, addr);
56 
                addr += block_size;
57 
        }
58 
        if (ie)
59 
                icache_enable();
60 
}
61 
 
62 
void flush_cache(unsigned long addr, unsigned long size)
63 
{
64 
        flush_dcache_range(addr, addr + size);
65 
        invalidate_icache_range(addr, addr + size);
66 
}
67 
 
68 
int icache_status(void)
69 
{
70 
        return mfspr(SPR_SR) & SPR_SR_ICE;
71 
}
72 
 
73 
int checkicache(void)
74 
{
75 
        unsigned long iccfgr;
76 
        unsigned long cache_set_size;
77 
        unsigned long cache_ways;
78 
        unsigned long cache_block_size;
79 
 
80 
        iccfgr = mfspr(SPR_ICCFGR);
81 
        cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
82 
        cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
83 
        cache_block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16;
84 
 
85 
        return cache_set_size * cache_ways * cache_block_size;
86 
}
87 
 
88 
int dcache_status(void)
89 
{
90 
        return mfspr(SPR_SR) & SPR_SR_DCE;
91 
}
92 
 
93 
int checkdcache(void)
94 
{
95 
        unsigned long dccfgr;
96 
        unsigned long cache_set_size;
97 
        unsigned long cache_ways;
98 
        unsigned long cache_block_size;
99 
 
100 
        dccfgr = mfspr(SPR_DCCFGR);
101 
        cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
102 
        cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
103 
        cache_block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16;
104 
 
105 
        return cache_set_size * cache_ways * cache_block_size;
106 
}
107 
 
108 
void dcache_enable(void)
109 
{
110 
        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
111 
        asm volatile("l.nop");
112 
        asm volatile("l.nop");
113 
        asm volatile("l.nop");
114 
        asm volatile("l.nop");
115 
        asm volatile("l.nop");
116 
        asm volatile("l.nop");
117 
        asm volatile("l.nop");
118 
        asm volatile("l.nop");
119 
}
120 
 
121 
void dcache_disable(void)
122 
{
123 
        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE);
124 
}
125 
 
126 
void icache_enable(void)
127 
{
128 
        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_ICE);
129 
        asm volatile("l.nop");
130 
        asm volatile("l.nop");
131 
        asm volatile("l.nop");
132 
        asm volatile("l.nop");
133 
        asm volatile("l.nop");
134 
        asm volatile("l.nop");
135 
        asm volatile("l.nop");
136 
        asm volatile("l.nop");
137 
}
138 
 
139 
void icache_disable(void)
140 
{
141 
        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE);
142 
}
143 
 
144 
int cache_init(void)
145 
{
146 
        if (mfspr(SPR_UPR) & SPR_UPR_ICP) {
147 
                icache_disable();
148 
                invalidate_icache_range(0, checkicache());
149 
                icache_enable();
150 
        }
151 
 
152 
        if (mfspr(SPR_UPR) & SPR_UPR_DCP) {
153 
                dcache_disable();
154 
                invalidate_dcache_range(0, checkdcache());
155 
                dcache_enable();
156 
        }
157 
 
158 
        return 0;
159 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.