OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [interrupts.c] - Blame information for rev 603

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 584 jeremybenn
#include "../../../Source/portable/GCC/OpenRISC/portmacro.h"
2
#include "spr_defs.h"
3
 
4
// Dummy or32 except vectors
5
void buserr_except(void) {
6
        uart_print_str("buserr_except\n\r");
7
        while(1) ;
8
}
9
 
10
void dpf_except(void) {
11
        uart_print_str("dpf_except\n\r");
12
        while(1) ;
13
}
14
 
15
void ipf_except(void) {
16
        uart_print_str("ipf_except\n\r");
17
        while(1) ;
18
}
19
 
20
void align_except(void) {
21
        uart_print_str("align_except\n\r");
22
        while(1) ;
23
}
24
 
25
void illegal_except(void) {
26
        uart_print_str("illegal_except\n\r");
27
        while(1) ;
28
}
29
 
30
void dtlbmiss_except(void) {
31
        uart_print_str("dtlbmiss_except\n\r");
32
        while(1) ;
33
}
34
 
35
void itlbmiss_except(void) {
36
        uart_print_str("itlbmiss_except\n\r");
37
        while(1) ;
38
}
39
 
40
void range_except(void) {
41
        uart_print_str("range_except\n\r");
42
        while(1) ;
43
}
44
 
45
static void syscall_enter_critical(void) {
46
        unsigned int exception_sr = mfspr(SPR_ESR_BASE);
47
        exception_sr &= (~SPR_SR_IEE);          // disable all external interrupt
48
        exception_sr &= (~SPR_SR_TEE);          // disable tick timer interrupt
49
 
50
        mtspr(SPR_ESR_BASE, exception_sr);
51
}
52
 
53
static void syscall_exit_critical(void) {
54
        unsigned int exception_sr = mfspr(SPR_ESR_BASE);
55
        exception_sr |= SPR_SR_IEE;             // enable all external interrupt
56
        exception_sr |= SPR_SR_TEE;             // enable tick timer interrupt
57
 
58
        mtspr(SPR_ESR_BASE, exception_sr);
59
}
60
 
61
void syscall_except(int id) {
62
        if(id == 0x0FCE) {
63
                syscall_enter_critical();
64
        } else if(id == 0x0FCF) {
65
                syscall_exit_critical();
66
        } else {
67
                uart_put_int(id);
68
                uart_print_str(" syscall is not impelmented yet....\n\r");
69
        }
70
}
71
 
72
 
73
void res1_except(void) {
74
        uart_print_str("res1_except\n\r");
75
        while(1) ;
76
}
77
 
78
void trap_except(void) {
79
        uart_print_str("trap_except\n\r");
80
        while(1) ;
81
}
82
 
83
void res2_except(void) {
84
        uart_print_str("res2_except\n\r");
85
        while(1) ;
86
}
87
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.