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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [interrupts.c] - Blame information for rev 621

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Line No. Rev Author Line
1 621 filepang 
/* This file is part of test microkernel for OpenRISC 1000. */
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/* (C) 2001 Simon Srot, srot@opencores.org */
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#include "support.h"
5 584 jeremybenn 
#include "spr_defs.h"
6 621 filepang 
#include "interrupts.h"
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8 621 filepang 
/* Interrupt handlers table */
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static struct ihnd int_handlers[MAX_INT_HANDLERS];
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/* Initialize routine */
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int int_init(void) {
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        int i;
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        // initialize Interrupt handler table
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        for(i = 0; i < MAX_INT_HANDLERS; i++) {
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                int_handlers[i].handler = 0;
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                int_handlers[i].arg = 0;
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        }
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        // mask all interrupt
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        mtspr(SPR_PICMR, 0x00000000);
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        // set OR1200 to accept exceptions (external interrupt enable)
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        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
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        return 0;
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}
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/* Add interrupt handler */
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int int_add(unsigned long vect, void (* handler)(void *), void *arg) {
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        if(vect >= MAX_INT_HANDLERS)
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                return -1;
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        int_handlers[vect].handler = handler;
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        int_handlers[vect].arg = arg;
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        mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
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        return 0;
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}
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/* Disable interrupt */
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int int_disable(unsigned long vect) {
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        if(vect >= MAX_INT_HANDLERS)
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                return -1;
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        mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect));
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        return 0;
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}
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/* Enable interrupt */
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int int_enable(unsigned long vect) {
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        if(vect >= MAX_INT_HANDLERS)
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                return -1;
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        mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
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        return 0;
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}
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/* Main interrupt handler */
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void int_main(void) {
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        unsigned long picsr = mfspr(SPR_PICSR);   // process only the interrupts asserted at signal catch, ignore all during process
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        unsigned long i = 0;
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        while(i < 32) {
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                if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
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                        (*int_handlers[i].handler)(int_handlers[i].arg);
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                }
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                i++;
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        }
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        mtspr(SPR_PICSR, 0);     // clear interrupt status: all modules have level interrupts, which have to be cleared by software,
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}                               // thus this is safe, since non processed interrupts will get re-asserted soon enough
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// Dummy or32 except vectors
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void buserr_except(void) {
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        uart_print_str("buserr_except\n\r");
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}
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void dpf_except(void) {
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        uart_print_str("dpf_except\n\r");
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}
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void ipf_except(void) {
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        uart_print_str("ipf_except\n\r");
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}
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void align_except(void) {
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        uart_print_str("align_except\n\r");
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}
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void illegal_except(void) {
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        uart_print_str("illegal_except\n\r");
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}
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void dtlbmiss_except(void) {
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        uart_print_str("dtlbmiss_except\n\r");
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}
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void itlbmiss_except(void) {
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        uart_print_str("itlbmiss_except\n\r");
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}
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void range_except(void) {
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        uart_print_str("range_except\n\r");
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}
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111 621 filepang 
void res1_except(void) {
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        uart_print_str("res1_except\n\r");
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}
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void trap_except(void) {
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        uart_print_str("trap_except\n\r");
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}
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void res2_except(void) {
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        uart_print_str("res2_except\n\r");
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}
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void misc_int_handler(int arg) {
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        switch(arg) {
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        case 0x200: { buserr_except();   break; }
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        case 0x300: { dpf_except();              break; }
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        case 0x400: { ipf_except();      break; }
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        case 0x600: { align_except();    break; }
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        case 0x700: { illegal_except();  break; }
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        case 0x900: { dtlbmiss_except(); break; }
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        case 0xa00: { itlbmiss_except(); break; }
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        case 0xb00: { range_except();    break; }
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        case 0xd00: { res1_except();     break; }
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        case 0xe00: { trap_except();     break; }
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        case 0xf00: { res2_except();     break; }
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        default: { break; }
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        }
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}
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140 584 jeremybenn 
static void syscall_enter_critical(void) {
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        unsigned int exception_sr = mfspr(SPR_ESR_BASE);
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        exception_sr &= (~SPR_SR_IEE);          // disable all external interrupt
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        exception_sr &= (~SPR_SR_TEE);          // disable tick timer interrupt
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        mtspr(SPR_ESR_BASE, exception_sr);
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}
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static void syscall_exit_critical(void) {
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        unsigned int exception_sr = mfspr(SPR_ESR_BASE);
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        exception_sr |= SPR_SR_IEE;             // enable all external interrupt
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        exception_sr |= SPR_SR_TEE;             // enable tick timer interrupt
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        mtspr(SPR_ESR_BASE, exception_sr);
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}
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void syscall_except(int id) {
157 621 filepang 
        if(id == 0x0FCC) {
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                vTaskSwitchContext();
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        } else if(id == 0x0FCE) {
160 584 jeremybenn 
                syscall_enter_critical();
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        } else if(id == 0x0FCF) {
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                syscall_exit_critical();
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        } else {
164 621 filepang 
                uart_print_int(id);
165 584 jeremybenn 
                uart_print_str(" syscall is not impelmented yet....\n\r");
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        }
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}
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