OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [interrupts.c] - Blame information for rev 773

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 621 filepang 
/* This file is part of test microkernel for OpenRISC 1000. */
2 
/* (C) 2001 Simon Srot, srot@opencores.org */
3 
 
4 
#include "support.h"
5 584 jeremybenn 
#include "spr_defs.h"
6 621 filepang 
#include "interrupts.h"
7 584 jeremybenn 
 
8 621 filepang 
/* Interrupt handlers table */
9 
static struct ihnd int_handlers[MAX_INT_HANDLERS];
10 
 
11 
/* Initialize routine */
12 
int int_init(void) {
13 
        int i;
14 
 
15 
        // initialize Interrupt handler table
16 
        for(i = 0; i < MAX_INT_HANDLERS; i++) {
17 
                int_handlers[i].handler = 0;
18 
                int_handlers[i].arg = 0;
19 
        }
20 
 
21 
        // mask all interrupt
22 
        mtspr(SPR_PICMR, 0x00000000);
23 
 
24 
        // set OR1200 to accept exceptions (external interrupt enable)
25 
        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
26 
 
27 
        return 0;
28 
}
29 
 
30 
/* Add interrupt handler */
31 
int int_add(unsigned long vect, void (* handler)(void *), void *arg) {
32 
        if(vect >= MAX_INT_HANDLERS)
33 
                return -1;
34 
 
35 
        int_handlers[vect].handler = handler;
36 
        int_handlers[vect].arg = arg;
37 
 
38 
        mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
39 
 
40 
        return 0;
41 
}
42 
 
43 
/* Disable interrupt */
44 
int int_disable(unsigned long vect) {
45 
        if(vect >= MAX_INT_HANDLERS)
46 
                return -1;
47 
 
48 
        mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect));
49 
 
50 
        return 0;
51 
}
52 
 
53 
/* Enable interrupt */
54 
int int_enable(unsigned long vect) {
55 
        if(vect >= MAX_INT_HANDLERS)
56 
                return -1;
57 
 
58 
        mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
59 
 
60 
        return 0;
61 
}
62 
 
63 
/* Main interrupt handler */
64 
void int_main(void) {
65 
        unsigned long picsr = mfspr(SPR_PICSR);   // process only the interrupts asserted at signal catch, ignore all during process
66 
        unsigned long i = 0;
67 
 
68 
        while(i < 32) {
69 
                if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
70 
                        (*int_handlers[i].handler)(int_handlers[i].arg);
71 
                }
72 
                i++;
73 
        }
74 
 
75 
        mtspr(SPR_PICSR, 0);     // clear interrupt status: all modules have level interrupts, which have to be cleared by software,
76 
}                               // thus this is safe, since non processed interrupts will get re-asserted soon enough
77 
 
78 584 jeremybenn 
// Dummy or32 except vectors
79 
void buserr_except(void) {
80 
        uart_print_str("buserr_except\n\r");
81 
}
82 
 
83 
void dpf_except(void) {
84 
        uart_print_str("dpf_except\n\r");
85 
}
86 
 
87 
void ipf_except(void) {
88 
        uart_print_str("ipf_except\n\r");
89 
}
90 
 
91 
void align_except(void) {
92 
        uart_print_str("align_except\n\r");
93 
}
94 
 
95 
void illegal_except(void) {
96 
        uart_print_str("illegal_except\n\r");
97 
}
98 
 
99 
void dtlbmiss_except(void) {
100 
        uart_print_str("dtlbmiss_except\n\r");
101 
}
102 
 
103 
void itlbmiss_except(void) {
104 
        uart_print_str("itlbmiss_except\n\r");
105 
}
106 
 
107 
void range_except(void) {
108 
        uart_print_str("range_except\n\r");
109 
}
110 
 
111 621 filepang 
void res1_except(void) {
112 
        uart_print_str("res1_except\n\r");
113 
}
114 
 
115 
void trap_except(void) {
116 
        uart_print_str("trap_except\n\r");
117 
}
118 
 
119 
void res2_except(void) {
120 
        uart_print_str("res2_except\n\r");
121 
}
122 
 
123 
void misc_int_handler(int arg) {
124 
        switch(arg) {
125 
        case 0x200: { buserr_except();   break; }
126 
        case 0x300: { dpf_except();              break; }
127 
        case 0x400: { ipf_except();      break; }
128 
        case 0x600: { align_except();    break; }
129 
        case 0x700: { illegal_except();  break; }
130 
        case 0x900: { dtlbmiss_except(); break; }
131 
        case 0xa00: { itlbmiss_except(); break; }
132 
        case 0xb00: { range_except();    break; }
133 
        case 0xd00: { res1_except();     break; }
134 
        case 0xe00: { trap_except();     break; }
135 
        case 0xf00: { res2_except();     break; }
136 
        default: { break; }
137 
        }
138 
}
139 
 
140 584 jeremybenn 
static void syscall_enter_critical(void) {
141 
        unsigned int exception_sr = mfspr(SPR_ESR_BASE);
142 
        exception_sr &= (~SPR_SR_IEE);          // disable all external interrupt
143 
        exception_sr &= (~SPR_SR_TEE);          // disable tick timer interrupt
144 
 
145 
        mtspr(SPR_ESR_BASE, exception_sr);
146 
}
147 
 
148 
static void syscall_exit_critical(void) {
149 
        unsigned int exception_sr = mfspr(SPR_ESR_BASE);
150 
        exception_sr |= SPR_SR_IEE;             // enable all external interrupt
151 
        exception_sr |= SPR_SR_TEE;             // enable tick timer interrupt
152 
 
153 
        mtspr(SPR_ESR_BASE, exception_sr);
154 
}
155 
 
156 
void syscall_except(int id) {
157 621 filepang 
        if(id == 0x0FCC) {
158 
                vTaskSwitchContext();
159 
        } else if(id == 0x0FCE) {
160 584 jeremybenn 
                syscall_enter_critical();
161 
        } else if(id == 0x0FCF) {
162 
                syscall_exit_critical();
163 
        } else {
164 621 filepang 
                uart_print_int(id);
165 584 jeremybenn 
                uart_print_str(" syscall is not impelmented yet....\n\r");
166 
        }
167 
}
168 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.