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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [link.ld] - Blame information for rev 584

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Line No. Rev Author Line
1 584 jeremybenn 
MEMORY
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{
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        vectors : ORIGIN = 0x00000000, LENGTH = 0x00001100
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        ram     : ORIGIN = 0x00001200, LENGTH = 0x00080000 - 0x00001200
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}
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SECTIONS
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{
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        .vectors :
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        {
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                _vec_start = .;
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                *(.vectors)
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                _vec_end = .;
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        } > vectors
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        .text ALIGN(4) :
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        {
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                *(.text)
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        } > ram
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        .rodata ALIGN(4) :
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        {
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                *(.rodata)
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                *(.rodata.*)
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        } > ram
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        .icm ALIGN(4) :
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        {
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                _icm_start = .;
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                *(.icm)
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                _icm_end = .;
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        } > ram
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        .data ALIGN(4) :
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        {
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                _dst_beg = .;
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                *(.data)
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                _dst_end = .;
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        } > ram
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        .bss ALIGN(4) :
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        {
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                _bss_beg = .;
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                *(.bss)
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                _bss_end = .;
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        } > ram
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        PROVIDE(_stack_top = 0x00080000);
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}

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