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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [link.ld] - Blame information for rev 773

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MEMORY
{
        vectors : ORIGIN = 0x00000000, LENGTH = 0x00001000
        ram     : ORIGIN = 0x00001000, LENGTH = 0x00080000 - 0x00001000
}
 
SECTIONS
{
        .vectors :
        {
                _vec_start = .;
                *(.vectors)
                _vec_end = .;
        } > vectors
 
        .text ALIGN(4) :
        {
                *(.text)
        } > ram
 
        .rodata ALIGN(4) :
        {
                *(.rodata)
                *(.rodata.*)
        } > ram
 
        .icm ALIGN(4) :
        {
                _icm_start = .;
                *(.icm)
                _icm_end = .;
        } > ram
 
        .data ALIGN(4) :
        {
                _dst_beg = .;
                *(.data)
                _dst_end = .;
        } > ram
 
        .bss ALIGN(4) :
        {
                _bss_beg = .;
                *(.bss)
                _bss_end = .;
        } > ram
 
        PROVIDE(_stack_top = 0x00080000);
}

Line No.	Rev	Author	Line
1	584	jeremybenn	`MEMORY`
2			`{`
3	623	filepang	`vectors : ORIGIN = 0x00000000, LENGTH = 0x00001000`
4			`ram : ORIGIN = 0x00001000, LENGTH = 0x00080000 - 0x00001000`
5	584	jeremybenn	`}`
6
7			`SECTIONS`
8			`{`
9			`.vectors :`
10			`{`
11			`_vec_start = .;`
12			`*(.vectors)`
13			`_vec_end = .;`
14			`} > vectors`
15
16			`.text ALIGN(4) :`
17			`{`
18			`*(.text)`
19			`} > ram`
20
21			`.rodata ALIGN(4) :`
22			`{`
23			`*(.rodata)`
24			`(.rodata.)`
25			`} > ram`
26
27			`.icm ALIGN(4) :`
28			`{`
29			`_icm_start = .;`
30			`*(.icm)`
31			`_icm_end = .;`
32			`} > ram`
33
34			`.data ALIGN(4) :`
35			`{`
36			`_dst_beg = .;`
37			`*(.data)`
38			`_dst_end = .;`
39			`} > ram`
40
41			`.bss ALIGN(4) :`
42			`{`
43			`_bss_beg = .;`
44			`*(.bss)`
45			`_bss_end = .;`
46			`} > ram`
47
48			`PROVIDE(_stack_top = 0x00080000);`
49			`}`

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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [link.ld] - Blame information for rev 773