URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [reset.S] - Blame information for rev 621

Details | Compare with Previous | View Log


/* Support file for c based tests */
#include "spr_defs.h"
#include "board.h"
#include "mc.h"
 
        .global         _stack_top
        .section        .vectors, "ax"
 
        .org    0x100
_reset_vector:
        l.nop
        l.nop
        l.addi  r2,r0,0x0
        l.addi  r3,r0,0x0
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r7,r0,0x0
        l.addi  r8,r0,0x0
        l.addi  r9,r0,0x0
        l.addi  r10,r0,0x0
        l.addi  r11,r0,0x0
        l.addi  r12,r0,0x0
        l.addi  r13,r0,0x0
        l.addi  r14,r0,0x0
        l.addi  r15,r0,0x0
        l.addi  r16,r0,0x0
        l.addi  r17,r0,0x0
        l.addi  r18,r0,0x0
        l.addi  r19,r0,0x0
        l.addi  r20,r0,0x0
        l.addi  r21,r0,0x0
        l.addi  r22,r0,0x0
        l.addi  r23,r0,0x0
        l.addi  r24,r0,0x0
        l.addi  r25,r0,0x0
        l.addi  r26,r0,0x0
        l.addi  r27,r0,0x0
        l.addi  r28,r0,0x0
        l.addi  r29,r0,0x0
        l.addi  r30,r0,0x0
        l.addi  r31,r0,0x0
 
        l.movhi r3,hi(_start)
        l.ori   r3,r3,lo(_start)
        l.jr    r3
        l.nop
 
 
.org 0x200
_except_200:
        l.nop
        l.sw    -4(r1), r3
        l.addi  r3, r0, 0x200
        l.sw    -132(r1), r3
        l.lwz   r3, -4(r1)
        l.j             vPortMiscIntHandler
        l.nop
 
 
.org 0x300
_except_300:
        l.nop
        l.sw    -4(r1), r3
        l.addi  r3, r0, 0x300
        l.sw    -132(r1), r3
        l.lwz   r3, -4(r1)
        l.j             vPortMiscIntHandler
        l.nop
 
 
.org 0x400
_except_400:
        l.nop
        l.sw    -4(r1), r3
        l.addi  r3, r0, 0x400
        l.sw    -132(r1), r3
        l.lwz   r3, -4(r1)
        l.j             vPortMiscIntHandler
        l.nop
 
 
.org 0x500
_except_500:
        l.nop
        l.j     vPortTickHandler
        l.nop
 
 
.org 0x600
_except_600:
        l.nop
        l.sw    -4(r1), r3
        l.addi  r3, r0, 0x600
        l.sw    -132(r1), r3
        l.lwz   r3, -4(r1)
        l.j             vPortMiscIntHandler
        l.nop
 
 
.org 0x700
_except_700:
        l.nop
        l.sw    -4(r1), r3
        l.addi  r3, r0, 0x700
        l.sw    -132(r1), r3
        l.lwz   r3, -4(r1)
        l.j             vPortMiscIntHandler
        l.nop
 
 
.org 0x800
_except_800:
        l.nop
    l.j vPortExtIntHandler
    l.nop
 
 
.org 0x900
_except_900:
        l.nop
        l.sw    -4(r1), r3
        l.addi  r3, r0, 0x900
        l.sw    -132(r1), r3
        l.lwz   r3, -4(r1)
        l.j             vPortMiscIntHandler
        l.nop
 
 
.org 0xa00
_except_a00:
        l.nop
        l.sw    -4(r1), r3
        l.addi  r3, r0, 0xa00
        l.sw    -132(r1), r3
        l.lwz   r3, -4(r1)
        l.j             vPortMiscIntHandler
        l.nop
 
 
.org 0xb00
_except_b00:
        l.nop
        l.sw    -4(r1), r3
        l.addi  r3, r0, 0xb00
        l.sw    -132(r1), r3
        l.lwz   r3, -4(r1)
        l.j             vPortMiscIntHandler
        l.nop
 
 
.org 0xc00
_except_c00:
        .global         vPortSystemCall
        l.nop
        l.j vPortSystemCall
        l.nop
 
 
.org 0xd00
_except_d00:
        l.nop
        l.sw    -4(r1), r3
        l.addi  r3, r0, 0xd00
        l.sw    -132(r1), r3
        l.lwz   r3, -4(r1)
        l.j             vPortMiscIntHandler
        l.nop
 
 
.org 0xe00
_except_e00:
        l.nop
        l.sw    -4(r1), r3
        l.addi  r3, r0, 0xe00
        l.sw    -132(r1), r3
        l.lwz   r3, -4(r1)
        l.j             vPortMiscIntHandler
        l.nop
 
 
.org 0xf00
_except_f00:
        l.nop
        l.sw    -4(r1), r3
        l.addi  r3, r0, 0xf00
        l.sw    -132(r1), r3
        l.lwz   r3, -4(r1)
        l.j             vPortMiscIntHandler
        l.nop
 
 
        .section .text
 
_start:
.if IC | DC
        /* Flush IC and/or DC */
        l.addi  r10,r0,0
        l.addi  r11,r0,0
        l.addi  r12,r0,0
.if IC
        l.addi  r11,r0,IC_SIZE
.endif
.if DC
        l.addi  r12,r0,DC_SIZE
.endif
        l.sfleu r12,r11
        l.bf    loop
        l.nop
        l.add   r11,r0,r12
loop:
.if IC
        l.mtspr r0,r10,SPR_ICBIR
.endif
.if DC
        l.mtspr r0,r10,SPR_DCBIR
.endif
        l.sfne  r10,r11
        l.bf    loop
        l.addi  r10,r10,16
 
        /* Enable IC and/or DC */
        l.addi  r10,r0,(SPR_SR_SM)
.if IC
        l.ori   r10,r10,(SPR_SR_ICE)
.endif
.if DC
        l.ori   r10,r10,(SPR_SR_DCE)
.endif
        l.mtspr r0,r10,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
.endif
 
        /* Set stack pointer */
        l.movhi r1, hi(_stack_top)
        l.ori   r1, r1, lo(_stack_top)
 
        /* clear BSS */
        l.movhi r2, hi(_bss_beg)
        l.ori   r2, r2, lo(_bss_beg)
        l.movhi r3, hi(_bss_end)
        l.ori   r3, r2, lo(_bss_end)
1:
        l.sfeq  r2, r3
        l.bf    __main
        l.nop
 
        l.sw    0x0(r2), r0
        l.addi  r2, r2, 0x4
        l.j             1b
        l.nop
 
        /* Jump to main */
__main:
        l.movhi r2, hi(_main)
        l.ori   r2, r2, lo(_main)
        l.jr    r2
        l.nop

Line No.	Rev	Author	Line
1	584	jeremybenn	`/* Support file for c based tests */`
2			`#include "spr_defs.h"`
3			`#include "board.h"`
4			`#include "mc.h"`
5
6			`.global _stack_top`
7			`.section .vectors, "ax"`
8
9			`.org 0x100`
10			`_reset_vector:`
11			`l.nop`
12			`l.nop`
13			`l.addi r2,r0,0x0`
14			`l.addi r3,r0,0x0`
15			`l.addi r4,r0,0x0`
16			`l.addi r5,r0,0x0`
17			`l.addi r6,r0,0x0`
18			`l.addi r7,r0,0x0`
19			`l.addi r8,r0,0x0`
20			`l.addi r9,r0,0x0`
21			`l.addi r10,r0,0x0`
22			`l.addi r11,r0,0x0`
23			`l.addi r12,r0,0x0`
24			`l.addi r13,r0,0x0`
25			`l.addi r14,r0,0x0`
26			`l.addi r15,r0,0x0`
27			`l.addi r16,r0,0x0`
28			`l.addi r17,r0,0x0`
29			`l.addi r18,r0,0x0`
30			`l.addi r19,r0,0x0`
31			`l.addi r20,r0,0x0`
32			`l.addi r21,r0,0x0`
33			`l.addi r22,r0,0x0`
34			`l.addi r23,r0,0x0`
35			`l.addi r24,r0,0x0`
36			`l.addi r25,r0,0x0`
37			`l.addi r26,r0,0x0`
38			`l.addi r27,r0,0x0`
39			`l.addi r28,r0,0x0`
40			`l.addi r29,r0,0x0`
41			`l.addi r30,r0,0x0`
42			`l.addi r31,r0,0x0`
43
44			`l.movhi r3,hi(_start)`
45			`l.ori r3,r3,lo(_start)`
46			`l.jr r3`
47			`l.nop`
48
49	621	filepang
50	584	jeremybenn	`.org 0x200`
51			`_except_200:`
52			`l.nop`
53	621	filepang	`l.sw -4(r1), r3`
54			`l.addi r3, r0, 0x200`
55			`l.sw -132(r1), r3`
56			`l.lwz r3, -4(r1)`
57			`l.j vPortMiscIntHandler`
58	584	jeremybenn	`l.nop`
59
60	621	filepang
61	584	jeremybenn	`.org 0x300`
62			`_except_300:`
63			`l.nop`
64	621	filepang	`l.sw -4(r1), r3`
65			`l.addi r3, r0, 0x300`
66			`l.sw -132(r1), r3`
67			`l.lwz r3, -4(r1)`
68			`l.j vPortMiscIntHandler`
69	584	jeremybenn	`l.nop`
70
71	621	filepang
72	584	jeremybenn	`.org 0x400`
73			`_except_400:`
74			`l.nop`
75	621	filepang	`l.sw -4(r1), r3`
76			`l.addi r3, r0, 0x400`
77			`l.sw -132(r1), r3`
78			`l.lwz r3, -4(r1)`
79			`l.j vPortMiscIntHandler`
80	584	jeremybenn	`l.nop`
81
82	621	filepang
83	584	jeremybenn	`.org 0x500`
84			`_except_500:`
85			`l.nop`
86	621	filepang	`l.j vPortTickHandler`
87	584	jeremybenn	`l.nop`
88
89	621	filepang
90	584	jeremybenn	`.org 0x600`
91			`_except_600:`
92			`l.nop`
93	621	filepang	`l.sw -4(r1), r3`
94			`l.addi r3, r0, 0x600`
95			`l.sw -132(r1), r3`
96			`l.lwz r3, -4(r1)`
97			`l.j vPortMiscIntHandler`
98	584	jeremybenn	`l.nop`
99
100	621	filepang
101	584	jeremybenn	`.org 0x700`
102			`_except_700:`
103			`l.nop`
104	621	filepang	`l.sw -4(r1), r3`
105			`l.addi r3, r0, 0x700`
106			`l.sw -132(r1), r3`
107			`l.lwz r3, -4(r1)`
108			`l.j vPortMiscIntHandler`
109	584	jeremybenn	`l.nop`
110
111	621	filepang
112	584	jeremybenn	`.org 0x800`
113			`_except_800:`
114			`l.nop`
115	621	filepang	`l.j vPortExtIntHandler`
116	584	jeremybenn	`l.nop`
117
118
119			`.org 0x900`
120			`_except_900:`
121			`l.nop`
122	621	filepang	`l.sw -4(r1), r3`
123			`l.addi r3, r0, 0x900`
124			`l.sw -132(r1), r3`
125			`l.lwz r3, -4(r1)`
126			`l.j vPortMiscIntHandler`
127	584	jeremybenn	`l.nop`
128
129	621	filepang
130	584	jeremybenn	`.org 0xa00`
131			`_except_a00:`
132			`l.nop`
133	621	filepang	`l.sw -4(r1), r3`
134			`l.addi r3, r0, 0xa00`
135			`l.sw -132(r1), r3`
136			`l.lwz r3, -4(r1)`
137			`l.j vPortMiscIntHandler`
138	584	jeremybenn	`l.nop`
139
140	621	filepang
141	584	jeremybenn	`.org 0xb00`
142			`_except_b00:`
143			`l.nop`
144	621	filepang	`l.sw -4(r1), r3`
145			`l.addi r3, r0, 0xb00`
146			`l.sw -132(r1), r3`
147			`l.lwz r3, -4(r1)`
148			`l.j vPortMiscIntHandler`
149	584	jeremybenn	`l.nop`
150
151	621	filepang
152	584	jeremybenn	`.org 0xc00`
153			`_except_c00:`
154	621	filepang	`.global vPortSystemCall`
155	584	jeremybenn	`l.nop`
156	621	filepang	`l.j vPortSystemCall`
157	584	jeremybenn	`l.nop`
158
159
160			`.org 0xd00`
161			`_except_d00:`
162			`l.nop`
163	621	filepang	`l.sw -4(r1), r3`
164			`l.addi r3, r0, 0xd00`
165			`l.sw -132(r1), r3`
166			`l.lwz r3, -4(r1)`
167			`l.j vPortMiscIntHandler`
168	584	jeremybenn	`l.nop`
169
170	621	filepang
171	584	jeremybenn	`.org 0xe00`
172			`_except_e00:`
173			`l.nop`
174	621	filepang	`l.sw -4(r1), r3`
175			`l.addi r3, r0, 0xe00`
176			`l.sw -132(r1), r3`
177			`l.lwz r3, -4(r1)`
178			`l.j vPortMiscIntHandler`
179	584	jeremybenn	`l.nop`
180
181	621	filepang
182	584	jeremybenn	`.org 0xf00`
183			`_except_f00:`
184			`l.nop`
185	621	filepang	`l.sw -4(r1), r3`
186			`l.addi r3, r0, 0xf00`
187			`l.sw -132(r1), r3`
188			`l.lwz r3, -4(r1)`
189			`l.j vPortMiscIntHandler`
190	584	jeremybenn	`l.nop`
191
192
193			`.section .text`
194
195			`_start:`
196			`.if IC \| DC`
197			`/* Flush IC and/or DC */`
198			`l.addi r10,r0,0`
199			`l.addi r11,r0,0`
200			`l.addi r12,r0,0`
201			`.if IC`
202			`l.addi r11,r0,IC_SIZE`
203			`.endif`
204			`.if DC`
205			`l.addi r12,r0,DC_SIZE`
206			`.endif`
207			`l.sfleu r12,r11`
208			`l.bf loop`
209			`l.nop`
210			`l.add r11,r0,r12`
211			`loop:`
212			`.if IC`
213			`l.mtspr r0,r10,SPR_ICBIR`
214			`.endif`
215			`.if DC`
216			`l.mtspr r0,r10,SPR_DCBIR`
217			`.endif`
218			`l.sfne r10,r11`
219			`l.bf loop`
220			`l.addi r10,r10,16`
221
222			`/* Enable IC and/or DC */`
223			`l.addi r10,r0,(SPR_SR_SM)`
224			`.if IC`
225			`l.ori r10,r10,(SPR_SR_ICE)`
226			`.endif`
227			`.if DC`
228			`l.ori r10,r10,(SPR_SR_DCE)`
229			`.endif`
230			`l.mtspr r0,r10,SPR_SR`
231			`l.nop`
232			`l.nop`
233			`l.nop`
234			`l.nop`
235			`l.nop`
236			`.endif`
237
238			`/* Set stack pointer */`
239			`l.movhi r1, hi(_stack_top)`
240			`l.ori r1, r1, lo(_stack_top)`
241
242			`/* clear BSS */`
243			`l.movhi r2, hi(_bss_beg)`
244			`l.ori r2, r2, lo(_bss_beg)`
245			`l.movhi r3, hi(_bss_end)`
246			`l.ori r3, r2, lo(_bss_end)`
247			`1:`
248			`l.sfeq r2, r3`
249			`l.bf __main`
250	621	filepang	`l.nop`
251	584	jeremybenn
252			`l.sw 0x0(r2), r0`
253			`l.addi r2, r2, 0x4`
254			`l.j 1b`
255			`l.nop`
256
257			`/* Jump to main */`
258			`__main:`
259	621	filepang	`l.movhi r2, hi(_main)`
260			`l.ori r2, r2, lo(_main)`
261	584	jeremybenn	`l.jr r2`
262			`l.nop`

Browse

Tools

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [reset.S] - Blame information for rev 621