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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [arch/] [spr_defs.h] - Blame information for rev 584

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Line No. Rev Author Line
1 584 jeremybenn
/* spr_defs.h -- Defines OR1K architecture specific special-purpose registers
2
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5
 
6
This program is free software; you can redistribute it and/or modify
7
it under the terms of the GNU General Public License as published by
8
the Free Software Foundation; either version 2 of the License, or
9
(at your option) any later version.
10
 
11
This program is distributed in the hope that it will be useful,
12
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with this program; if not, write to the Free Software
18
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19
 
20
/* This file is also used by microkernel test bench. Among
21
others it is also used in assembly file(s). */
22
 
23
/* Definition of special-purpose registers (SPRs) */
24
 
25
#define MAX_GRPS (32)
26
#define MAX_SPRS_PER_GRP_BITS (11)
27
#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
28
#define MAX_SPRS (0x10000)
29
 
30
/* Base addresses for the groups */
31
#define SPRGROUP_SYS    (0<< MAX_SPRS_PER_GRP_BITS)
32
#define SPRGROUP_DMMU   (1<< MAX_SPRS_PER_GRP_BITS)
33
#define SPRGROUP_IMMU   (2<< MAX_SPRS_PER_GRP_BITS)
34
#define SPRGROUP_DC             (3<< MAX_SPRS_PER_GRP_BITS)
35
#define SPRGROUP_IC             (4<< MAX_SPRS_PER_GRP_BITS)
36
#define SPRGROUP_MAC    (5<< MAX_SPRS_PER_GRP_BITS)
37
#define SPRGROUP_D              (6<< MAX_SPRS_PER_GRP_BITS)
38
#define SPRGROUP_PC             (7<< MAX_SPRS_PER_GRP_BITS)
39
#define SPRGROUP_PM             (8<< MAX_SPRS_PER_GRP_BITS)
40
#define SPRGROUP_PIC    (9<< MAX_SPRS_PER_GRP_BITS)
41
#define SPRGROUP_TT             (10<< MAX_SPRS_PER_GRP_BITS)
42
 
43
/* System control and status group */
44
#define SPR_VR                  (SPRGROUP_SYS + 0)
45
#define SPR_UPR                 (SPRGROUP_SYS + 1)
46
#define SPR_CPUCFGR             (SPRGROUP_SYS + 2)
47
#define SPR_DMMUCFGR    (SPRGROUP_SYS + 3)
48
#define SPR_IMMUCFGR    (SPRGROUP_SYS + 4)
49
#define SPR_DCCFGR              (SPRGROUP_SYS + 5)
50
#define SPR_ICCFGR              (SPRGROUP_SYS + 6)
51
#define SPR_DCFGR               (SPRGROUP_SYS + 7)
52
#define SPR_PCCFGR              (SPRGROUP_SYS + 8)
53
#define SPR_NPC         (SPRGROUP_SYS + 16)  /* CZ 21/06/01 */
54
#define SPR_SR                  (SPRGROUP_SYS + 17)  /* CZ 21/06/01 */
55
#define SPR_PPC         (SPRGROUP_SYS + 18)  /* CZ 21/06/01 */
56
#define SPR_EPCR_BASE   (SPRGROUP_SYS + 32)  /* CZ 21/06/01 */
57
#define SPR_EPCR_LAST   (SPRGROUP_SYS + 47)  /* CZ 21/06/01 */
58
#define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)
59
#define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)
60
#define SPR_ESR_BASE    (SPRGROUP_SYS + 64)
61
#define SPR_ESR_LAST    (SPRGROUP_SYS + 79)
62
 
63
/* Data MMU group */
64
#define SPR_DMMUCR                      (SPRGROUP_DMMU + 0)
65
#define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
66
#define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
67
#define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
68
#define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
69
 
70
/* Instruction MMU group */
71
#define SPR_IMMUCR                      (SPRGROUP_IMMU + 0)
72
#define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
73
#define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
74
#define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
75
#define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
76
 
77
/* Data cache group */
78
#define SPR_DCCR                        (SPRGROUP_DC + 0)
79
#define SPR_DCBPR                       (SPRGROUP_DC + 1)
80
#define SPR_DCBFR                       (SPRGROUP_DC + 2)
81
#define SPR_DCBIR                       (SPRGROUP_DC + 3)
82
#define SPR_DCBWR                       (SPRGROUP_DC + 4)
83
#define SPR_DCBLR                       (SPRGROUP_DC + 5)
84
#define SPR_DCR_BASE(WAY)       (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
85
#define SPR_DCR_LAST(WAY)       (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
86
 
87
/* Instruction cache group */
88
#define SPR_ICCR                        (SPRGROUP_IC + 0)
89
#define SPR_ICBPR                       (SPRGROUP_IC + 1)
90
#define SPR_ICBIR                       (SPRGROUP_IC + 2)
91
#define SPR_ICBLR                       (SPRGROUP_IC + 3)
92
#define SPR_ICR_BASE(WAY)       (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
93
#define SPR_ICR_LAST(WAY)       (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
94
 
95
/* MAC group */
96
#define SPR_MACLO       (SPRGROUP_MAC + 1)
97
#define SPR_MACHI       (SPRGROUP_MAC + 2)
98
 
99
/* Debug group */
100
#define SPR_DVR(N)      (SPRGROUP_D + (N))
101
#define SPR_DCR(N)      (SPRGROUP_D + 8 + (N))
102
#define SPR_DMR1        (SPRGROUP_D + 16)
103
#define SPR_DMR2        (SPRGROUP_D + 17)
104
#define SPR_DWCR0       (SPRGROUP_D + 18)
105
#define SPR_DWCR1       (SPRGROUP_D + 19)
106
#define SPR_DSR         (SPRGROUP_D + 20)
107
#define SPR_DRR         (SPRGROUP_D + 21)
108
 
109
/* Performance counters group */
110
#define SPR_PCCR(N)     (SPRGROUP_PC + (N))
111
#define SPR_PCMR(N)     (SPRGROUP_PC + 8 + (N))
112
 
113
/* Power management group */
114
#define SPR_PMR (SPRGROUP_PM + 0)
115
 
116
/* PIC group */
117
#define SPR_PICMR (SPRGROUP_PIC + 0)
118
#define SPR_PICPR (SPRGROUP_PIC + 1)
119
#define SPR_PICSR (SPRGROUP_PIC + 2)
120
 
121
/* Tick Timer group */
122
#define SPR_TTMR (SPRGROUP_TT + 0)
123
#define SPR_TTCR (SPRGROUP_TT + 1)
124
 
125
/*
126
 * Bit definitions for the Version Register
127
 *
128
 */
129
#define SPR_VR_VER      0xffff0000  /* Processor version */
130
#define SPR_VR_REV      0x0000003f  /* Processor revision */
131
 
132
/*
133
 * Bit definitions for the Unit Present Register
134
 *
135
 */
136
#define SPR_UPR_UP              0x00000001  /* UPR present */
137
#define SPR_UPR_DCP             0x00000002  /* Data cache present */
138
#define SPR_UPR_ICP             0x00000004  /* Instruction cache present */
139
#define SPR_UPR_DMP             0x00000008  /* Data MMU present */
140
#define SPR_UPR_IMP             0x00000010  /* Instruction MMU present */
141
#define SPR_UPR_OB32P   0x00000020  /* ORBIS32 present */
142
#define SPR_UPR_OB64P   0x00000040  /* ORBIS64 present */
143
#define SPR_UPR_OF32P   0x00000080  /* ORFPX32 present */
144
#define SPR_UPR_OF64P   0x00000100  /* ORFPX64 present */
145
#define SPR_UPR_OV32P   0x00000200  /* ORVDX32 present */
146
#define SPR_UPR_OV64P   0x00000400  /* ORVDX64 present */
147
#define SPR_UPR_DUP             0x00000800  /* Debug unit present */
148
#define SPR_UPR_PCUP    0x00001000  /* Performance counters unit present */
149
#define SPR_UPR_PMP             0x00002000  /* Power management present */
150
#define SPR_UPR_PICP    0x00004000  /* PIC present */
151
#define SPR_UPR_TTP             0x00008000  /* Tick timer present */
152
#define SPR_UPR_SRP             0x00010000  /* Shadow registers present */
153
#define SPR_UPR_RES             0x00fe0000  /* ORVDX32 present */
154
#define SPR_UPR_CUST    0xff000000  /* Custom units */
155
 
156
/*
157
 * Bit definitions for the Supervision Register
158
 *
159
 */
160
#define SPR_SR_CID      0xf0000000  /* Context ID */
161
#define SPR_SR_FO       0x00008000  /* Fixed one */
162
#define SPR_SR_EPH      0x00004000  /* Exception Prefixi High */
163
#define SPR_SR_DSX      0x00002000  /* Delay Slot Exception */
164
#define SPR_SR_OVE      0x00001000  /* Overflow flag Exception */
165
#define SPR_SR_OV       0x00000800  /* Overflow flag */
166
#define SPR_SR_CY       0x00000400  /* Carry flag */
167
#define SPR_SR_F        0x00000200  /* Condition Flag */
168
#define SPR_SR_CE       0x00000100  /* CID Enable */
169
#define SPR_SR_LEE      0x00000080  /* Little Endian Enable */
170
#define SPR_SR_IME      0x00000040  /* Instruction MMU Enable */
171
#define SPR_SR_DME      0x00000020  /* Data MMU Enable */
172
#define SPR_SR_ICE      0x00000010  /* Instruction Cache Enable */
173
#define SPR_SR_DCE      0x00000008  /* Data Cache Enable */
174
#define SPR_SR_IEE      0x00000004  /* Interrupt Exception Enable */
175
#define SPR_SR_TEE      0x00000002  /* Tick timer Exception Enable */
176
#define SPR_SR_SM       0x00000001  /* Supervisor Mode */
177
 
178
/*
179
 * Bit definitions for the Data MMU Control Register
180
 *
181
 */
182
#define SPR_DMMUCR_P2S                  0x0000003e  /* Level 2 Page Size */
183
#define SPR_DMMUCR_P1S                  0x000007c0  /* Level 1 Page Size */
184
#define SPR_DMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
185
#define SPR_DMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
186
 
187
/*
188
 * Bit definitions for the Instruction MMU Control Register
189
 *
190
 */
191
#define SPR_IMMUCR_P2S                  0x0000003e  /* Level 2 Page Size */
192
#define SPR_IMMUCR_P1S                  0x000007c0  /* Level 1 Page Size */
193
#define SPR_IMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
194
#define SPR_IMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
195
 
196
/*
197
 * Bit definitions for the Data TLB Match Register
198
 *
199
 */
200
#define SPR_DTLBMR_V    0x00000001  /* Valid */
201
#define SPR_DTLBMR_PL1  0x00000002  /* Page Level 1 (if 0 then PL2) */
202
#define SPR_DTLBMR_CID  0x0000003c  /* Context ID */
203
#define SPR_DTLBMR_LRU  0x000000c0  /* Least Recently Used */
204
#define SPR_DTLBMR_VPN  0xfffff000  /* Virtual Page Number */
205
 
206
/*
207
 * Bit definitions for the Data TLB Translate Register
208
 *
209
 */
210
#define SPR_DTLBTR_CC   0x00000001  /* Cache Coherency */
211
#define SPR_DTLBTR_CI   0x00000002  /* Cache Inhibit */
212
#define SPR_DTLBTR_WBC  0x00000004  /* Write-Back Cache */
213
#define SPR_DTLBTR_WOM  0x00000008  /* Weakly-Ordered Memory */
214
#define SPR_DTLBTR_A    0x00000010  /* Accessed */
215
#define SPR_DTLBTR_D    0x00000020  /* Dirty */
216
#define SPR_DTLBTR_URE  0x00000040  /* User Read Enable */
217
#define SPR_DTLBTR_UWE  0x00000080  /* User Write Enable */
218
#define SPR_DTLBTR_SRE  0x00000100  /* Supervisor Read Enable */
219
#define SPR_DTLBTR_SWE  0x00000200  /* Supervisor Write Enable */
220
#define SPR_DTLBTR_PPN  0xfffff000  /* Physical Page Number */
221
#define DTLB_PR_NOLIMIT  (SPR_DTLBTR_URE  | \
222
                          SPR_DTLBTR_UWE  | \
223
                          SPR_DTLBTR_SRE  | \
224
                          SPR_DTLBTR_SWE  )
225
/*
226
 * Bit definitions for the Instruction TLB Match Register
227
 *
228
 */
229
#define SPR_ITLBMR_V    0x00000001  /* Valid */
230
#define SPR_ITLBMR_PL1  0x00000002  /* Page Level 1 (if 0 then PL2) */
231
#define SPR_ITLBMR_CID  0x0000003c  /* Context ID */
232
#define SPR_ITLBMR_LRU  0x000000c0  /* Least Recently Used */
233
#define SPR_ITLBMR_VPN  0xfffff000  /* Virtual Page Number */
234
 
235
/*
236
 * Bit definitions for the Instruction TLB Translate Register
237
 *
238
 */
239
#define SPR_ITLBTR_CC   0x00000001  /* Cache Coherency */
240
#define SPR_ITLBTR_CI   0x00000002  /* Cache Inhibit */
241
#define SPR_ITLBTR_WBC  0x00000004  /* Write-Back Cache */
242
#define SPR_ITLBTR_WOM  0x00000008  /* Weakly-Ordered Memory */
243
#define SPR_ITLBTR_A    0x00000010  /* Accessed */
244
#define SPR_ITLBTR_D    0x00000020  /* Dirty */
245
#define SPR_ITLBTR_SXE  0x00000040  /* User Read Enable */
246
#define SPR_ITLBTR_UXE  0x00000080  /* User Write Enable */
247
#define SPR_ITLBTR_PPN  0xfffff000  /* Physical Page Number */
248
#define ITLB_PR_NOLIMIT  (SPR_ITLBTR_SXE  | \
249
                          SPR_ITLBTR_UXE  )
250
 
251
 
252
/*
253
 * Bit definitions for Data Cache Control register
254
 *
255
 */
256
#define SPR_DCCR_EW     0x000000ff  /* Enable ways */
257
 
258
/*
259
 * Bit definitions for Insn Cache Control register
260
 *
261
 */
262
#define SPR_ICCR_EW     0x000000ff  /* Enable ways */
263
 
264
/*
265
 * Bit definitions for Debug Control registers
266
 *
267
 */
268
#define SPR_DCR_DP      0x00000001  /* DVR/DCR present */
269
#define SPR_DCR_CC      0x0000000e  /* Compare condition */
270
#define SPR_DCR_SC      0x00000010  /* Signed compare */
271
#define SPR_DCR_CT      0x000000e0  /* Compare to */
272
 
273
/* Bit results with SPR_DCR_CC mask */
274
#define SPR_DCR_CC_MASKED 0x00000000
275
#define SPR_DCR_CC_EQUAL  0x00000001
276
#define SPR_DCR_CC_LESS   0x00000002
277
#define SPR_DCR_CC_LESSE  0x00000003
278
#define SPR_DCR_CC_GREAT  0x00000004
279
#define SPR_DCR_CC_GREATE 0x00000005
280
#define SPR_DCR_CC_NEQUAL 0x00000006
281
 
282
/* Bit results with SPR_DCR_CT mask */
283
#define SPR_DCR_CT_DISABLED 0x00000000
284
#define SPR_DCR_CT_IFEA     0x00000020
285
#define SPR_DCR_CT_LEA      0x00000040
286
#define SPR_DCR_CT_SEA      0x00000060
287
#define SPR_DCR_CT_LD       0x00000080
288
#define SPR_DCR_CT_SD       0x000000a0
289
#define SPR_DCR_CT_LSEA     0x000000c0
290
 
291
/*
292
 * Bit definitions for Debug Mode 1 register
293
 *
294
 */
295
#define SPR_DMR1_CW0    0x00000003  /* Chain watchpoint 0 */
296
#define SPR_DMR1_CW1    0x0000000c  /* Chain watchpoint 1 */
297
#define SPR_DMR1_CW2    0x00000030  /* Chain watchpoint 2 */
298
#define SPR_DMR1_CW3    0x000000c0  /* Chain watchpoint 3 */
299
#define SPR_DMR1_CW4    0x00000300  /* Chain watchpoint 4 */
300
#define SPR_DMR1_CW5    0x00000c00  /* Chain watchpoint 5 */
301
#define SPR_DMR1_CW6    0x00003000  /* Chain watchpoint 6 */
302
#define SPR_DMR1_CW7    0x0000c000  /* Chain watchpoint 7 */
303
#define SPR_DMR1_CW8    0x00030000  /* Chain watchpoint 8 */
304
#define SPR_DMR1_CW9    0x000c0000  /* Chain watchpoint 9 */
305
#define SPR_DMR1_CW10   0x00300000  /* Chain watchpoint 10 */
306
#define SPR_DMR1_ST             0x00400000  /* Single-step trace*/
307
#define SPR_DMR1_BT             0x00800000  /* Branch trace */
308
#define SPR_DMR1_DXFW   0x01000000  /* Disable external force watchpoint */
309
 
310
/*
311
 * Bit definitions for Debug Mode 2 register
312
 *
313
 */
314
#define SPR_DMR2_WCE0   0x00000001  /* Watchpoint counter 0 enable */
315
#define SPR_DMR2_WCE1   0x00000002  /* Watchpoint counter 0 enable */
316
#define SPR_DMR2_AWTC   0x00001ffc  /* Assign watchpoints to counters */
317
#define SPR_DMR2_WGB    0x00ffe000  /* Watchpoints generating breakpoint */
318
 
319
/*
320
 * Bit definitions for Debug watchpoint counter registers
321
 *
322
 */
323
#define SPR_DWCR_COUNT  0x0000ffff  /* Count */
324
#define SPR_DWCR_MATCH  0xffff0000  /* Match */
325
 
326
/*
327
 * Bit definitions for Debug stop register
328
 *
329
 */
330
#define SPR_DSR_RSTE    0x00000001  /* Reset exception */
331
#define SPR_DSR_BUSEE   0x00000002  /* Bus error exception */
332
#define SPR_DSR_DPFE    0x00000004  /* Data Page Fault exception */
333
#define SPR_DSR_IPFE    0x00000008  /* Insn Page Fault exception */
334
#define SPR_DSR_TTE             0x00000010  /* Tick Timer exception */
335
#define SPR_DSR_AE              0x00000020  /* Alignment exception */
336
#define SPR_DSR_IIE             0x00000040  /* Illegal Instruction exception */
337
#define SPR_DSR_IE              0x00000080  /* Interrupt exception */
338
#define SPR_DSR_DME             0x00000100  /* DTLB miss exception */
339
#define SPR_DSR_IME             0x00000200  /* ITLB miss exception */
340
#define SPR_DSR_RE              0x00000400  /* Range exception */
341
#define SPR_DSR_SCE             0x00000800  /* System call exception */
342
#define SPR_DSR_SSE     0x00001000  /* Single Step Exception */
343
#define SPR_DSR_TE              0x00002000  /* Trap exception */
344
 
345
/*
346
 * Bit definitions for Debug reason register
347
 *
348
 */
349
#define SPR_DRR_RSTE    0x00000001  /* Reset exception */
350
#define SPR_DRR_BUSEE   0x00000002  /* Bus error exception */
351
#define SPR_DRR_DPFE    0x00000004  /* Data Page Fault exception */
352
#define SPR_DRR_IPFE    0x00000008  /* Insn Page Fault exception */
353
#define SPR_DRR_TTE             0x00000010  /* Tick Timer exception */
354
#define SPR_DRR_AE              0x00000020  /* Alignment exception */
355
#define SPR_DRR_IIE             0x00000040  /* Illegal Instruction exception */
356
#define SPR_DRR_IE              0x00000080  /* Interrupt exception */
357
#define SPR_DRR_DME             0x00000100  /* DTLB miss exception */
358
#define SPR_DRR_IME             0x00000200  /* ITLB miss exception */
359
#define SPR_DRR_RE              0x00000400  /* Range exception */
360
#define SPR_DRR_SCE             0x00000800  /* System call exception */
361
#define SPR_DRR_TE              0x00001000  /* Trap exception */
362
 
363
/*
364
 * Bit definitions for Performance counters mode registers
365
 *
366
 */
367
#define SPR_PCMR_CP             0x00000001  /* Counter present */
368
#define SPR_PCMR_UMRA   0x00000002  /* User mode read access */
369
#define SPR_PCMR_CISM   0x00000004  /* Count in supervisor mode */
370
#define SPR_PCMR_CIUM   0x00000008  /* Count in user mode */
371
#define SPR_PCMR_LA             0x00000010  /* Load access event */
372
#define SPR_PCMR_SA             0x00000020  /* Store access event */
373
#define SPR_PCMR_IF             0x00000040  /* Instruction fetch event*/
374
#define SPR_PCMR_DCM    0x00000080  /* Data cache miss event */
375
#define SPR_PCMR_ICM    0x00000100  /* Insn cache miss event */
376
#define SPR_PCMR_IFS    0x00000200  /* Insn fetch stall event */
377
#define SPR_PCMR_LSUS   0x00000400  /* LSU stall event */
378
#define SPR_PCMR_BS             0x00000800  /* Branch stall event */
379
#define SPR_PCMR_DTLBM  0x00001000  /* DTLB miss event */
380
#define SPR_PCMR_ITLBM  0x00002000  /* ITLB miss event */
381
#define SPR_PCMR_DDS    0x00004000  /* Data dependency stall event */
382
#define SPR_PCMR_WPE    0x03ff8000  /* Watchpoint events */
383
 
384
/*
385
 * Bit definitions for the Power management register
386
 *
387
 */
388
#define SPR_PMR_SDF             0x0000000f  /* Slow down factor */
389
#define SPR_PMR_DME             0x00000010  /* Doze mode enable */
390
#define SPR_PMR_SME             0x00000020  /* Sleep mode enable */
391
#define SPR_PMR_DCGE    0x00000040  /* Dynamic clock gating enable */
392
#define SPR_PMR_SUME    0x00000080  /* Suspend mode enable */
393
 
394
/*
395
 * Bit definitions for PICMR
396
 *
397
 */
398
#define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask */
399
 
400
/*
401
 * Bit definitions for PICPR
402
 *
403
 */
404
#define SPR_PICPR_IPRIO 0xfffffffc  /* Interrupt priority */
405
 
406
/*
407
 * Bit definitions for PICSR
408
 *
409
 */
410
#define SPR_PICSR_IS    0xffffffff  /* Interrupt status */
411
 
412
/*
413
 * Bit definitions for Tick Timer Control Register
414
 *
415
 */
416
#define SPR_TTCR_PERIOD 0x0fffffff  /* Time Period */
417
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD
418
#define SPR_TTMR_IP             0x10000000  /* Interrupt Pending */
419
#define SPR_TTMR_IE             0x20000000  /* Interrupt Enable */
420
#define SPR_TTMR_RT             0x40000000  /* Restart tick */
421
#define SPR_TTMR_SR     0x80000000  /* Single run */
422
#define SPR_TTMR_CR     0xc0000000  /* Continuous run */
423
#define SPR_TTMR_M      0xc0000000  /* Tick mode */
424
 
425
/*
426
 * l.nop constants
427
 *
428
 */
429
#define NOP_NOP         0x0000      /* Normal nop instruction */
430
#define NOP_EXIT        0x0001      /* End of simulation */
431
#define NOP_REPORT      0x0002      /* Simple report */
432
#define NOP_PRINTF      0x0003      /* Simprintf instruction */
433
#define NOP_REPORT_FIRST 0x0400     /* Report with number */
434
#define NOP_REPORT_LAST 0x03ff      /* Report with number */

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