OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [drivers/] [gpio.c] - Blame information for rev 750

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 623 filepang
#include "board.h"
2
#include "gpio.h"
3
#include "support.h"
4
 
5
#ifdef GPIO_NUM_CORES
6
const int GPIO_BASE_ADR[GPIO_NUM_CORES] = {GPIO0_BASE, GPIO1_BASE};
7
#else
8
const int GPIO_BASE_ADR[1] = {GPIO0_BASE};
9
#endif
10
 
11
void gpio_init(int core)
12
{
13
        // interrupt setup
14
        // global interrupt disable
15
        REG32(GPIO_BASE_ADR[core] + GPIO_CTRL   ) = 0x0;
16
 
17
        // mask all input interrupt
18
        REG32(GPIO_BASE_ADR[core] + GPIO_INTE   ) = 0x0;
19
 
20
        // clear interrupt interrupt
21
        REG32(GPIO_BASE_ADR[core] + GPIO_INTS   ) = 0x0;
22
 
23
        // set input interrupt posedge trigering mode
24
        REG32(GPIO_BASE_ADR[core] + GPIO_PTRIG  ) = 0xFFFFFFFF;
25
 
26
        // I/O setup
27
        // clear all GPIO output
28
        REG32(GPIO_BASE_ADR[core] + GPIO_OUT    ) = 0x0;
29
 
30
        // set all GPIO is input
31
        REG32(GPIO_BASE_ADR[core] + GPIO_OE             ) = 0xFFFFFFFF;
32
 
33
        // disable AUX input 
34
        REG32(GPIO_BASE_ADR[core] + GPIO_AUX    ) = 0x0;
35
 
36
 
37
        // Input sampling mode setup
38
        // use system bus clock to sampling GPIO inputs
39
        REG32(GPIO_BASE_ADR[core] + GPIO_ECLK   ) = 0x0;
40
 
41
        // ECLK active posedge
42
        REG32(GPIO_BASE_ADR[core] + GPIO_NEC    ) = 0x0;
43
}
44
 
45
void set_gpio_direction(int core, unsigned int dirs)
46
{
47
        REG32(GPIO_BASE_ADR[core] + GPIO_OE             ) = dirs;
48
}
49
 
50
unsigned int gpio_read(int core)
51
{
52
        return REG32(GPIO_BASE_ADR[core] + GPIO_IN      );
53
}
54
 
55
void gpio_write(int core, unsigned int value)
56
{
57
        REG32(GPIO_BASE_ADR[core] + GPIO_OUT    ) = value;
58
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.