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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [drivers/] [gpio.c] - Blame information for rev 623

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1 623 filepang
#include "board.h"
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#include "gpio.h"
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#include "support.h"
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#ifdef GPIO_NUM_CORES
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const int GPIO_BASE_ADR[GPIO_NUM_CORES] = {GPIO0_BASE, GPIO1_BASE};
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#else
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const int GPIO_BASE_ADR[1] = {GPIO0_BASE};
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#endif
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void gpio_init(int core)
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{
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        // interrupt setup
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        // global interrupt disable
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        REG32(GPIO_BASE_ADR[core] + GPIO_CTRL   ) = 0x0;
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        // mask all input interrupt
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        REG32(GPIO_BASE_ADR[core] + GPIO_INTE   ) = 0x0;
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        // clear interrupt interrupt
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        REG32(GPIO_BASE_ADR[core] + GPIO_INTS   ) = 0x0;
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        // set input interrupt posedge trigering mode
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        REG32(GPIO_BASE_ADR[core] + GPIO_PTRIG  ) = 0xFFFFFFFF;
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        // I/O setup
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        // clear all GPIO output
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        REG32(GPIO_BASE_ADR[core] + GPIO_OUT    ) = 0x0;
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        // set all GPIO is input
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        REG32(GPIO_BASE_ADR[core] + GPIO_OE             ) = 0xFFFFFFFF;
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        // disable AUX input 
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        REG32(GPIO_BASE_ADR[core] + GPIO_AUX    ) = 0x0;
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        // Input sampling mode setup
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        // use system bus clock to sampling GPIO inputs
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        REG32(GPIO_BASE_ADR[core] + GPIO_ECLK   ) = 0x0;
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        // ECLK active posedge
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        REG32(GPIO_BASE_ADR[core] + GPIO_NEC    ) = 0x0;
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}
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void set_gpio_direction(int core, unsigned int dirs)
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{
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        REG32(GPIO_BASE_ADR[core] + GPIO_OE             ) = dirs;
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}
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unsigned int gpio_read(int core)
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{
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        return REG32(GPIO_BASE_ADR[core] + GPIO_IN      );
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}
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void gpio_write(int core, unsigned int value)
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{
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        REG32(GPIO_BASE_ADR[core] + GPIO_OUT    ) = value;
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}

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