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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [drivers/] [uart.c] - Blame information for rev 666

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Line No. Rev Author Line
1 584 jeremybenn 
#include "board.h"
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#include "uart.h"
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#include "support.h"
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#ifdef UART_NUM_CORES
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const int UART_BASE_ADR[UART_NUM_CORES] = {UART0_BASE, UART1_BASE};
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const int UART_BAUDS[UART_NUM_CORES] = {UART0_BAUD_RATE, UART1_BAUS_RATE};
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#else
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const int UART_BASE_ADR[1] = {UART0_BASE};
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const int UART_BAUDS[1] = {UART0_BAUD_RATE};
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#endif
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#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
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#define WAIT_FOR_XMITR(core)                    \
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        do { \
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                lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
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        } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
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#define WAIT_FOR_THRE(core)                     \
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        do { \
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                lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
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        } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
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#define CHECK_FOR_CHAR(core) (REG8(UART_BASE_ADR[core] + UART_LSR) & UART_LSR_DR)
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#define WAIT_FOR_CHAR(core)                     \
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         do { \
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                lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
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         } while ((lsr & UART_LSR_DR) != UART_LSR_DR)
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void uart_init(int core)
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{
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        int divisor;
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        float float_divisor;
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        /* Reset receiver and transmiter */
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        REG8(UART_BASE_ADR[core] + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
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        /* Disable all interrupts */
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        REG8(UART_BASE_ADR[core] + UART_IER) = 0x00;
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        /* Set 8 bit char, 1 stop bit, no parity */
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        REG8(UART_BASE_ADR[core] + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
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        /* Set baud rate */
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        float_divisor = (float) IN_CLK/(16 * UART_BAUDS[core]);
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        float_divisor += 0.50f; // Ensure round up
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        divisor = (int) float_divisor;
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        REG8(UART_BASE_ADR[core] + UART_LCR) |= UART_LCR_DLAB;
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        REG8(UART_BASE_ADR[core] + UART_DLL) = divisor & 0x000000ff;
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        REG8(UART_BASE_ADR[core] + UART_DLM) = (divisor >> 8) & 0x000000ff;
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        REG8(UART_BASE_ADR[core] + UART_LCR) &= ~(UART_LCR_DLAB);
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        return;
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}
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void uart_putc(int core, char c)
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{
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        unsigned char lsr;
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        WAIT_FOR_THRE(core);
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        REG8(UART_BASE_ADR[core] + UART_TX) = c;
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        if(c == '\n') {
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                WAIT_FOR_THRE(core);
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                REG8(UART_BASE_ADR[core] + UART_TX) = '\r';
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        }
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        WAIT_FOR_XMITR(core);
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}
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// Only used when we know THRE is empty, typically in interrupt
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void uart_putc_noblock(int core, char c)
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{
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        REG8(UART_BASE_ADR[core] + UART_TX) = c;
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}
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char uart_getc(int core)
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{
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        unsigned char lsr;
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        char c;
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        WAIT_FOR_CHAR(core);
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        c = REG8(UART_BASE_ADR[core] + UART_RX);
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        return c;
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}
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char uart_getc_noblock(int core)
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{
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        char c;
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        c = REG8(UART_BASE_ADR[core] + UART_RX);
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        return c;
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}
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int uart_check_for_char(int core)
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{
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        return CHECK_FOR_CHAR(core);
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}
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void uart_rxint_enable(int core)
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{
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        REG8(UART_BASE_ADR[core] + UART_IER) |= UART_IER_RDI;
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}
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void uart_rxint_disable(int core)
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{
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        REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_RDI);
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}
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void uart_txint_enable(int core)
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{
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        REG8(UART_BASE_ADR[core] + UART_IER) |= UART_IER_THRI;
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}
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void uart_txint_disable(int core)
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{
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        REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_THRI);
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}
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char uart_get_iir(int core)
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{
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        return REG8(UART_BASE_ADR[core] + UART_IIR);
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}
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char uart_get_lsr(int core)
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{
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        return REG8(UART_BASE_ADR[core] + UART_LSR);
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}
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char uart_get_msr(int core)
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{
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        return REG8(UART_BASE_ADR[core] + UART_MSR);
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}
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void uart_print_str(char *p)
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{
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        while(*p != 0) {
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                uart_putc(0, *p);
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                p++;
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        }
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}
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void uart_print_int(int n)
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{
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        int  a;
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        char c;
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        if (n<0) {
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                uart_putc(0, '-');
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                n = -n;
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        }
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        a = n/10;
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        if(a) uart_print_int(a);
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        c = '0' + (n % 10);
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        uart_putc(0, c);
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}

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