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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [sim.cfg] - Blame information for rev 610

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1 584 jeremybenn
/* sim.cfg -- Simulator configuration script file
2
   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5
It contains the default configuration and help about configuring
6
the simulator.
7
 
8
This program is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 2 of the License, or
11
(at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program; if not, write to the Free Software
20
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
21
 
22
 
23
/* INTRODUCTION
24
 
25
   The ork1sim has various parameters, that are set in configuration files
26
   like this one. The user can switch between configurations at startup by
27
   specifying the required configuration file with the -f  option.
28
   If no configuration file is specified or1ksim searches for the default
29
   configuration file sim.cfg. First it searches for './sim.cfg'. If this
30
   file is not found, it searches for '~/or1k/sim.cfg'. If this file is
31
   not found too, it reverts to the built-in default configuration.
32
 
33
   NOTE: Users should not rely on the built-in configuration, since the
34
         default configuration may differ between version.
35
         Rather create a configuration file that sets all critical values.
36
 
37
   This file may contain (standard C) comments only - no // support.
38
 
39
   Configure files may be be included, using:
40
   include "file_name_to_include"
41
 
42
   Like normal configuration files, the included file is divided into
43
   sections. Each section is described in detail also.
44
 
45
   Some section have subsections. One example of such a subsection is:
46
 
47
   device 
48
     instance specific parameters...
49
   enddevice
50
 
51
   which creates a device instance.
52
*/
53
 
54
 
55
/* MEMORY SECTION
56
 
57
   This section specifies how the memory is generated and the blocks
58
   it consists of.
59
 
60
   type = random/unknown/pattern
61
      Specifies the initial memory values.
62
      'random' generates random memory using seed 'random_seed'.
63
      'pattern' fills memory with 'pattern'.
64
      'unknown' does not specify how memory should be generated,
65
      leaving the memory in a undefined state. This is the fastest
66
      option.
67
 
68
   random_seed = 
69
      random seed for randomizer, used if type = 'random'.
70
 
71
   pattern = 
72
      pattern to fill memory, used if type = 'pattern'.
73
 
74
   nmemories = 
75
      number of memory instances connected
76
 
77
   baseaddr = 
78
      memory start address
79
 
80
   size = 
81
      memory size
82
 
83
   name = ""
84
      memory block name
85
 
86
   ce = 
87
      chip enable index of the memory instance
88
 
89
   mc = 
90
      memory controller this memory is connected to
91
 
92
   delayr = 
93
      cycles, required for read access, -1 if instance does not support reading
94
 
95
   delayw = 
96
      cycles, required for write access, -1 if instance does not support writing
97
 
98
   log = ""
99
      filename, where to log memory accesses to, no log, if log command is not specified
100
*/
101
 
102
 
103
section memory
104
  random_seed = 12345
105
  type = random
106
  pattern = 0x00
107
 
108
  name = "FLASH"
109
  ce = 0
110
  mc = 0
111
  baseaddr = 0x04000000
112
  size = 0x00200000
113
  delayr = 1
114
  delayw = -1
115
end
116
 
117
section memory
118
  random_seed = 12345
119
  type = random
120
  pattern = 0x00
121
 
122
  name = "RAM"
123
  ce = 1
124
  mc = 0
125
  baseaddr = 0x00000000
126
  size = 0x00200000
127
  delayr = 1
128
  delayw = 5
129
end
130
 
131
section memory
132
  random_seed = 12345
133
  type = random
134
  pattern = 0x00
135
 
136
  name = "ICM"
137
  mc = 0
138
  ce = 2
139
  baseaddr = 0x00800000
140
  size = 0x00004000
141
  delayr = 1
142
  delayw = 1
143
end
144
 
145
 
146
/* IMMU SECTION
147
 
148
    This section configures the Instruction Memory Manangement Unit
149
 
150
    enabled = 0/1
151
       '0': disabled
152
       '1': enabled
153
       (NOTE: UPR bit is set)
154
 
155
    nsets = 
156
       number of ITLB sets; must be power of two
157
 
158
    nways = 
159
       number of ITLB ways
160
 
161
    pagesize = 
162
       instruction page size; must be power of two
163
 
164
    entrysize = 
165
       instruction entry size in bytes
166
 
167
    ustates = 
168
       number of ITLB usage states (2, 3, 4 etc., max is 4)
169
 
170
    hitdelay = 
171
       number of cycles immu hit costs
172
 
173
    missdelay = 
174
       number of cycles immu miss costs
175
*/
176
 
177
section immu
178
  enabled = 0
179
  nsets = 32
180
  nways = 1
181
  pagesize = 8192
182
end
183
 
184
 
185
/* DMMU SECTION
186
 
187
    This section configures the Data Memory Manangement Unit
188
 
189
    enabled = 0/1
190
       '0': disabled
191
       '1': enabled
192
       (NOTE: UPR bit is set)
193
 
194
    nsets = 
195
       number of DTLB sets; must be power of two
196
 
197
    nways = 
198
       number of DTLB ways
199
 
200
    pagesize = 
201
       data page size; must be power of two
202
 
203
    entrysize = 
204
       data entry size in bytes
205
 
206
    ustates = 
207
       number of DTLB usage states (2, 3, 4 etc., max is 4)
208
 
209
    hitdelay = 
210
       number of cycles dmmu hit costs
211
 
212
    missdelay = 
213
       number of cycles dmmu miss costs
214
*/
215
 
216
section dmmu
217
  enabled = 0
218
  nsets = 32
219
  nways = 1
220
  pagesize = 8192
221
end
222
 
223
 
224
/* IC SECTION
225
 
226
   This section configures the Instruction Cache
227
 
228
   enabled = 0/1
229
       '0': disabled
230
       '1': enabled
231
      (NOTE: UPR bit is set)
232
 
233
   nsets = 
234
      number of IC sets; must be power of two
235
 
236
   nways = 
237
      number of IC ways
238
 
239
   blocksize = 
240
      IC block size in bytes; must be power of two
241
 
242
   ustates = 
243
      number of IC usage states (2, 3, 4 etc., max is 4)
244
 
245
   hitdelay = 
246
      number of cycles ic hit costs
247
 
248
    missdelay = 
249
      number of cycles ic miss costs
250
*/
251
 
252
section ic
253
  enabled = 0
254
  nsets = 512
255
  nways = 1
256
  blocksize = 16
257
end
258
 
259
 
260
/* DC SECTION
261
 
262
   This section configures the Data Cache
263
 
264
   enabled = 0/1
265
       '0': disabled
266
       '1': enabled
267
      (NOTE: UPR bit is set)
268
 
269
   nsets = 
270
      number of DC sets; must be power of two
271
 
272
   nways = 
273
      number of DC ways
274
 
275
   blocksize = 
276
      DC block size in bytes; must be power of two
277
 
278
   ustates = 
279
      number of DC usage states (2, 3, 4 etc., max is 4)
280
 
281
   load_hitdelay = 
282
      number of cycles dc load hit costs
283
 
284
   load_missdelay = 
285
      number of cycles dc load miss costs
286
 
287
   store_hitdelay = 
288
      number of cycles dc load hit costs
289
 
290
   store_missdelay = 
291
      number of cycles dc load miss costs
292
*/
293
 
294
section dc
295
  enabled = 0
296
  nsets = 512
297
  nways = 1
298
  blocksize = 16
299
end
300
 
301
 
302
/* SIM SECTION
303
 
304
  This section specifies how or1ksim should behave.
305
 
306
  verbose = 0/1
307
       '0': don't print extra messages
308
       '1': print extra messages
309
 
310
  debug = 0-9
311
 
312
      1-9: debug message level.
313
           higher numbers produce more messages
314
 
315
  profile = 0/1
316
      '0': don't generate profiling file 'sim.profile'
317
      '1': don't generate profiling file 'sim.profile'
318
 
319
  prof_fn = ""
320
      optional filename for the profiling file.
321
      valid only if 'profile' is set
322
 
323
  mprofile = 0/1
324
      '0': don't generate memory profiling file 'sim.mprofile'
325
      '1': generate memory profiling file 'sim.mprofile'
326
 
327
  mprof_fn = ""
328
      optional filename for the memory profiling file.
329
      valid only if 'mprofile' is set
330
 
331
  history = 0/1
332
      '0': don't track execution flow
333
      '1': track execution flow
334
      Execution flow can be tracked for the simulator's
335
      'hist' command. Useful for back-trace debugging.
336
 
337
  iprompt = 0/1
338
     '0': start in  (so what do we start in ???)
339
     '1': start in interactive prompt.
340
 
341
  exe_log = 0/1
342
      '0': don't generate execution log.
343
      '1': generate execution log.
344
 
345
  exe_log = default/hardware/simple/software
346
      type of execution log, default is used when not specified
347
 
348
  exe_log_start = 
349
      index of first instruction to start logging, default = 0
350
 
351
  exe_log_end = 
352
      index of last instruction to end logging; not limited, if omitted
353
 
354
  exe_log_marker = 
355
       specifies number of instructions before horizontal marker is
356
      printed; if zero, markers are disabled (default)
357
 
358
  exe_log_fn = ""
359
      filename for the exection log file.
360
      valid only if 'exe_log' is set
361
 
362
  clkcycle = [ps|ns|us|ms]
363
      specifies time measurement for one cycle
364
*/
365
 
366
section sim
367
  verbose = 1
368
  debug = 0
369
  profile = 0
370
  prof_fn = "sim.profile"
371
 
372
  history = 1
373
  /* iprompt = 0 */
374
  exe_log = 0
375
  exe_log_type = simple
376
/*  exe_log_start = 0 */
377
/*  exe_log_end = 2000000 */
378
/*  exe_log_marker = 50 */
379
  exe_log_fn = "executed.log"
380
 
381
/*  clkcycle = 10000ns */
382
 
383
end
384
 
385
 
386
/* SECTION VAPI
387
 
388
    This section configures the Verification API, used for Advanced
389
    Core Verification.
390
 
391
    enabled = 0/1
392
        '0': disbable VAPI server
393
        '1': enable/start VAPI server
394
 
395
    server_port = 
396
        TCP/IP port to start VAPI server on
397
 
398
    log_enabled = 0/1
399
       '0': disable VAPI requests logging
400
       '1': enable VAPI requests logging
401
 
402
    hide_device_id = 0/1
403
       '0': don't log device id (for compatability with old version)
404
       '1': log device id
405
 
406
 
407
    vapi_fn = 
408
       filename for the log file.
409
       valid only if log_enabled is set
410
*/
411
 
412
section VAPI
413
  enabled = 0
414
  server_port = 9998
415
  log_enabled = 0
416
  vapi_log_fn = "vapi.log"
417
end
418
 
419
 
420
/* CPU SECTION
421
 
422
   This section specifies various CPU parameters.
423
 
424
   ver = 
425
   rev = 
426
      specifies version and revision of the CPU used
427
 
428
   upr = 
429
      changes the upr register
430
 
431
   sr = 
432
      sets the initial Supervision Register value
433
 
434
   superscalar = 0/1
435
      '0': CPU is scalar
436
      '1': CPU is superscalar
437
      (modify cpu/or32/execute.c to tune superscalar model)
438
 
439
   hazards = 0/1
440
      '0': don't track data hazards in superscalar CPU
441
      '1': track data hazards in superscalar CPU
442
      If tracked, data hazards can be displayed using the
443
      simulator's 'r' command.
444
 
445
   dependstats = 0/1
446
      '0': don't calculate inter-instruction dependencies.
447
      '1': calculate inter-instruction dependencies.
448
      If calculated, inter-instruction dependencies can be
449
      displayed using the simulator's 'stat' command.
450
 
451
   sbuf_len = 
452
      length of store buffer (<= 256), 0 = disabled
453
*/
454
 
455
section cpu
456
  ver = 0x1200
457
  rev = 0x0001
458
  /* upr = */
459
  superscalar = 0
460
  hazards = 1
461
  dependstats = 1
462
  sbuf_len = 1
463
end
464
 
465
 
466
/* PM SECTION
467
 
468
   This section specifies Power Management parameters
469
 
470
   enabled = 0/1
471
      '0': disable power management
472
      '1': enable power management
473
*/
474
 
475
section pm
476
  enabled = 0
477
end
478
 
479
 
480
/* BPB SECTION
481
 
482
   This section specifies how branch prediction should behave.
483
 
484
   enabled = 0/1
485
     '0': disable branch prediction
486
     '1': enable branch prediction
487
 
488
   btic = 0/1
489
     '0': disable branch target instruction cache model
490
     '1': enable branch target instruction cache model
491
 
492
   sbp_bf_fwd = 0/1
493
     Static branch prediction for 'l.bf'
494
     '0': don't use forward prediction
495
     '1': use forward prediction
496
 
497
   sbp_bnf_fwd = 0/1
498
     Static branch prediction for 'l.bnf'
499
     '0': don't use forward prediction
500
     '1': use forward prediction
501
 
502
   hitdelay = 
503
       number of cycles bpb hit costs
504
 
505
   missdelay = 
506
       number of cycles bpb miss costs
507
*/
508
 
509
section bpb
510
  enabled = 1
511
  btic = 1
512
  sbp_bf_fwd = 0
513
  sbp_bnf_fwd = 0
514
  hitdelay = 0
515
  missdelay = 0
516
end
517
 
518
 
519
/* DEBUG SECTION
520
 
521
   This sections specifies how the debug unit should behave.
522
 
523
   enabled = 0/1
524
      '0': disable debug unit
525
      '1': enable debug unit
526
 
527
   gdb_enabled = 0/1
528
      '0': don't start gdb server
529
      '1': start gdb server at port 'server_port'
530
 
531
   server_port = 
532
      TCP/IP port to start gdb server on
533
      valid only if gdb_enabled is set
534
 
535
   vapi_id = 
536
      Used to create "fake" vapi log file containing the JTAG proxy messages.
537
*/
538
section debug
539
  enabled = 1
540
  gdb_enabled = 1
541
  server_port = 9999
542
end
543
 
544
/* MC SECTION
545
 
546
   This section configures the memory controller
547
 
548
   enabled = 0/1
549
     '0': disable memory controller
550
     '1': enable memory controller
551
 
552
   baseaddr = 
553
      address of first MC register
554
 
555
   POC = 
556
      Power On Configuration register
557
 
558
   index = 
559
      Index of this memory controller amongst all the memory controllers
560
*/
561
 
562
section mc
563
  enabled = 0
564
  baseaddr = 0x60000000
565
  POC = 0x00000008                 /* Power on configuration register */
566
  index = 0
567
end
568
 
569
 
570
/* UART SECTION
571
 
572
   This section configures the UARTs
573
 
574
     enabled = <0|1>
575
        Enable/disable the peripheral.  By default if it is enabled.
576
 
577
     baseaddr = 
578
        address of first UART register for this device
579
 
580
 
581
     channel = :
582
 
583
        The channel parameter indicates the source of received UART characters
584
        and the sink for transmitted UART characters.
585
 
586
        The  can be either "file", "xterm", "tcp", "fd", or "tty"
587
        (without quotes).
588
 
589
          A) To send/receive characters from a pair of files, use a file
590
             channel:
591
 
592
               channel=file:,
593
 
594
          B) To create an interactive terminal window, use an xterm channel:
595
 
596
               channel=xterm:[]*
597
 
598
          C) To create a bidirectional tcp socket which one could, for example,
599
             access via telnet, use a tcp channel:
600
 
601
               channel=tcp:
602
 
603
          D) To cause the UART to read/write from existing numeric file
604
             descriptors, use an fd channel:
605
 
606
               channel=fd:,
607
 
608
          E) To connect the UART to a physical serial port, create a tty
609
             channel:
610
 
611
               channel=tty:device=/dev/ttyS0,baud=9600
612
 
613
     irq = 
614
        irq number for this device
615
 
616
     16550 = 0/1
617
        '0': this device is a UART16450
618
        '1': this device is a UART16550
619
 
620
     jitter = 
621
        in msecs... time to block, -1 to disable it
622
 
623
     vapi_id = 
624
        VAPI id of this instance
625
*/
626
 
627
section uart
628
  enabled = 1
629
  baseaddr = 0x90000000
630
  irq = 2
631
  /*channel = "file:uart0.rx,uart0.tx"*/
632
  /*channel = "tcp:10084" */
633
  channel = "xterm:"
634
  /*channel = "tcp:10000"*/
635
  jitter = -1                     /* async behaviour */
636
  16550 = 1
637
end
638
 
639
 
640
/* DMA SECTION
641
 
642
   This section configures the DMAs
643
 
644
     enabled = <0|1>
645
        Enable/disable the peripheral.  By default if it is enabled.
646
 
647
     baseaddr = 
648
        address of first DMA register for this device
649
 
650
     irq = 
651
        irq number for this device
652
 
653
     vapi_id = 
654
        VAPI id of this instance
655
*/
656
 
657
section dma
658
  enabled = 0
659
  baseaddr = 0x9a000000
660
  irq = 11
661
end
662
 
663
 
664
/* ETHERNET SECTION
665
 
666
   This section configures the ETHERNETs
667
 
668
     enabled = <0|1>
669
        Enable/disable the peripheral.  By default if it is enabled.
670
 
671
     baseaddr = 
672
        address of first ethernet register for this device
673
 
674
     dma = 
675
        which controller is this ethernet "connected" to
676
 
677
     irq = 
678
        ethernet mac IRQ level
679
 
680
     rtx_type = 
681
        use 0 - file interface, 1 - socket interface
682
 
683
     rx_channel = 
684
        DMA channel used for RX
685
 
686
     tx_channel = 
687
        DMA channel used for TX
688
 
689
     rxfile = ""
690
        filename, where to read data from
691
 
692
     txfile = ""
693
        filename, where to write data to
694
 
695
     sockif = ""
696
        interface name of ethernet socket
697
 
698
     vapi_id = 
699
        VAPI id of this instance
700
*/
701
 
702
section ethernet
703
  enabled = 0
704
  baseaddr = 0x92000000
705
  dma = 0
706
  irq = 4
707
  rtx_type = 0
708
  tx_channel = 0
709
  rx_channel = 1
710
  rxfile = "eth0.rx"
711
  txfile = "eth0.tx"
712
  sockif = "eth0"
713
end
714
 
715
 
716
/* GPIO SECTION
717
 
718
   This section configures the GPIOs
719
 
720
     enabled = <0|1>
721
        Enable/disable the peripheral.  By default if it is enabled.
722
 
723
     baseaddr = 
724
        address of first GPIO register for this device
725
 
726
     irq = 
727
        irq number for this device
728
 
729
     base_vapi_id = 
730
        first VAPI id of this instance
731
        GPIO uses 8 consecutive VAPI IDs
732
*/
733
 
734
section gpio
735
  enabled = 1
736
  baseaddr = 0x91000000
737
  irq = 3
738
  base_vapi_id = 0x0200
739
end
740
 
741
/* VGA SECTION
742
 
743
    This section configures the VGA/LCD controller
744
 
745
      enabled = <0|1>
746
        Enable/disable the peripheral.  By default if it is enabled.
747
 
748
      baseaddr = 
749
        address of first VGA register
750
 
751
      irq = 
752
        irq number for this device
753
 
754
      refresh_rate = 
755
        number of cycles between screen dumps
756
 
757
      filename = ""
758
        template name for generated names (e.g. "primary" produces "primary0023.bmp")
759
*/
760
 
761
section vga
762
  enabled = 0
763
  baseaddr = 0x97100000
764
  irq = 8
765
  refresh_rate = 100000
766
  filename = "primary"
767
end
768
 
769
 
770
/* TICK TIMER SECTION
771
 
772
    This section configures tick timer
773
 
774
    enabled = 0/1
775
      whether tick timer is enabled
776
*/
777
section tick
778
  enabled = 1
779
  irq = 3
780
end
781
 
782
section pic
783
  enabled = 1
784
  edge_trigger = 1
785
end
786
 
787
/* FB SECTION
788
 
789
    This section configures the frame buffer
790
 
791
    enabled = <0|1>
792
      Enable/disable the peripheral.  By default if it is enabled.
793
 
794
    baseaddr = 
795
      base address of frame buffer
796
 
797
    paladdr = 
798
      base address of first palette entry
799
 
800
    refresh_rate = 
801
      number of cycles between screen dumps
802
 
803
    filename = ""
804
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
805
*/
806
section fb
807
  enabled = 0
808
  baseaddr = 0x97000000
809
  refresh_rate = 1000000
810
  filename = "primary"
811
end
812
 
813
/* KBD SECTION
814
 
815
    This section configures the PS/2 compatible keyboard
816
 
817
    baseaddr = 
818
      base address of the keyboard device
819
 
820
    rxfile = ""
821
      filename, where to read data from
822
*/
823
section kbd
824
  enabled = 0
825
  irq = 5
826
  baseaddr = 0x94000000
827
  rxfile = "kbd.rx"
828
end
829
 
830
/* ATA SECTION
831
 
832
    This section configures the ATA/ATAPI host controller
833
 
834
      baseaddr = 
835
        address of first ATA register
836
 
837
      enabled = <0|1>
838
        Enable/disable the peripheral.  By default if it is enabled.
839
 
840
      irq = 
841
        irq number for this device
842
 
843
      debug = 
844
        debug level for ata models.
845
        0: no debug messages
846
        1: verbose messages
847
        3: normal messages (more messages than verbose)
848
        5: debug messages (normal debug messages)
849
        7: flow control messages (debug statemachine flows)
850
        9: low priority message (display everything the code does)
851
 
852
      dev_type0/1 = 
853
        ata device 0 type
854
        0: NO_CONNeCT: none (not connected)
855
        1: FILE      : simulated harddisk
856
        2: LOCAL     : local system harddisk
857
 
858
      dev_file0/1 = ""
859
        filename for simulated ATA device
860
        valid only if dev_type0 == 1
861
 
862
      dev_size0/1 = 
863
        size of simulated hard-disk (in MBytes)
864
        valid only if dev_type0 == 1
865
 
866
      dev_packet0/1 = 
867
        0: simulated ATA device does NOT implement PACKET command feature set
868
        1: simulated ATA device does implement PACKET command feature set
869
 
870
   FIXME: irq number
871
*/
872
section ata
873
  enabled = 0
874
  baseaddr = 0x9e000000
875
  irq = 15
876
 
877
  dev_type0   = 1
878
  dev_file0   = "/tmp/sim_atadev0"
879
  dev_size0   = 1
880
  dev_packet0 = 0
881
 
882
  dev_type1   = 0
883
  dev_file1   = ""
884
  dev_size1   = 0
885
  dev_packet1 = 0
886
end
887
 

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