URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [sim.cfg] - Blame information for rev 622

Go to most recent revision | Details | Compare with Previous | View Log


/* sim.cfg -- Simulator configuration script file
 
   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
   Copyright (C) 2010, Embecosm Limited
 
   Contributor Jeremy Bennett 
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see . */
 
 
/* -------------------------------------------------------------------------- */
/* The Ork1sim has various parameters, that can be set in configuration files
   like this one. The user can specify a configuration file at startu[ with
   the -f  option.
 
   The user guide (see the 'doc' directory) gives full details on
   configuration files. This is a reference configuration, which may be used
   as a starting point for customization.
 
   A number of peripherals are mapped at standard addresses (above 0x80000000)
   in the Verilog RTL of ORPSoC standard sitribution. The same values should
   be used in Or1ksim section definitions to match the behavior of the Verilog
 
      0x90000000 UART
      0x91000000 GPIO
      0x92000000 Ethernet
      0x93000000 Memory controller
      0x94000000 PS2 keyboard
      0x97000000 Frame buffer
      0x97100000 VGA
      0x9a000000 DMA controller
      0x9e000000 ATA disc
 
   Section ordering matches that in the user guide. All optional peripherals
   and functionality is disabled. Comments only list the possible entries and
   values. Consult the user guide for their meaning.
 
   Unless otherwise indicated, the first named option is the default.         */
/* -------------------------------------------------------------------------- */
 
 
/* Simulator section
 
   verbose               = 0|1
   debug                 = 0-9
   profile               = 0|1
   prof_file             = "" (default: "sim.profile")
   mprofile              = 0|1
   mprof_file            = "" (default: "sim.mprofile")
   history               = 0|1
   exe_log               = 0|1
   exe_log_type          = hardware|simple|software|default
   exe_log_start         =  (default: 0)
   exe_log_end           =  (default: never end)
   exe_log_marker        =  (default: no markers)
   exe_log_file          = "" (default: "executed.log")
   exe_bin_insn_log      = 0|1
   exe_bin_insn_log_file = "" (default: "exe-insn.bin")
   clkcycle              = [ps|ns|us|ms]
*/
section sim
  clkcycle = 100ns
end
 
 
/* VAPI section
 
   enabled        = 0|1
   server_port    =  (default: 50000)
   log_enabled    = 0|1
   hide_device_id = 0|1
   vapi_log_file  = "" (default "vapi.log")
*/
section VAPI
  server_port = 50000
  log_enabled = 0
  vapi_log_file = "vapi.log"
end
 
 
/* CUC section
 
    memory_order       = none|weak|strong|exact (default: strong)
    calling_convention = 0|1
    enable_bursts      = 0|1
    no_multicycle      = 0|1
    timings_file       = "" (default: virtex.tim)
*/
section cuc
  memory_order       = weak
  calling_convention = 1
  enable_bursts      = 1
  no_multicycle      = 1
end
 
 
/* CPU section
 
   ver         =  (default: 0)
   cfg         =  (default: 0)
   rev         =  (default: 0)
   upr         =  (see user manual for default settings)
   cfgr        =  (default: 0x00000020)
   sr          =  (default: 0x00008001)
   superscalar = 0|1
   hazards     = 0|1
   dependstats = 0|1
   sbuf_len    =  (default: 0)
   hardfloat   = 0|1
*/
section cpu
  ver = 0x12
  cfg = 0x00
  rev = 0x0001
end
 
 
/* Memory section
 
   type        = unknown|random|unknown|pattern
   random_seed =  (default: -1)
   pattern     =  (default: 0)
   baseaddr    =  (default: 0)
   size        =  (default: 1024)
   name        = "" (default: "anonymous memory block")
   ce          =  (default: -1)
   mc          =  (default: 0)
   delayr      =  (default: 1)
   delayw      =  (default: 1)
   log         = "" (default: NULL)
*/
section memory
  name        = "RAM"
  type        = unknown
  baseaddr    = 0x00000000
  size        = 0x00080000
  delayr      = 1
  delayw      = 2
end
 
 
/* Data MMU section
 
   enabled   = 0|1
   nsets     =  (default: 1)
   nways     =  (default: 1)
   pagesize  =  (default: 8192)
   entrysize =  (default: 1)
   ustates   =  (default: 1)
   hitdelay  =  (default: 1)
   missdelay =  (default: 1)
*/
section dmmu
  enabled   = 0
  nsets     = 64
  nways     = 1
  pagesize  = 8192
  hitdelay  = 0
  missdelay = 0
end
 
 
/* Instruction MMU section
 
   enabled   = 0|1
   nsets     =  (default: 1)
   nways     =  (default: 1)
   pagesize  =  (default: 8192)
   entrysize =  (default: 1)
   ustates   =  (default: 1)
   hitdelay  =  (default: 1)
   missdelay =  (default: 1)
*/
section immu
  enabled   = 0
  nsets     = 64
  nways     = 1
  pagesize  = 8192
  hitdelay  = 0
  missdelay = 0
end
 
 
/* Data cache section
 
   enabled         = 0|1
   nsets           =  (default: 1)
   nways           =  (default: 1)
   blocksize       =  (default: 16)
   ustates         =  (default: 2)
   load_hitdelay   =  (default: 2)
   load_missdelay  =  (default: 2)
   store_hitdelay  =  (default: 0)
   store_missdelay =  (default: 0)
*/
 
section dc
  enabled         = 0
  nsets           = 256
  nways           = 1
  blocksize       = 16
  load_hitdelay   = 0
  load_missdelay  = 0
  store_hitdelay  = 0
  store_missdelay = 0
end
 
 
/* Instruction cache section
 
   enabled    = 0|1
   nsets      =  (default: 1)
   nways      =  (default: 1)
   blocksize  =  (default: 16)
   ustates    =  (default: 2)
   hitdelay   =  (default: 1)
   missdelay  =  (default: 1)
*/
section ic
  enabled   = 0
  nsets     = 256
  nways     = 1
  blocksize = 16
  hitdelay  = 0
  missdelay = 0
end
 
 
/* Programmable interrupt controller section
 
  enabled      = 0|1
  edge_trigger = 0|1 (default: 1)
*/
 
section pic
  enabled = 1
end
 
 
/* Power management section
 
   enabled = 0|1
*/
 
section pm
  enabled = 0
end
 
 
/* Branch prediction section
 
   enabled     = 0|1
   btic        = 0|1
   sbp_bf_fwd  = 0|1
   sbp_bnf_fwd = 0|1
   hitdelay    =  (default: 0)
   missdelay   =  (default: 0)
*/
 
section bpb
  enabled = 0
end
 
 
/* Debug unit section
 
   enabled     = 0|1
   rsp_enabled = 0|1
   rsp_port    =  (default: 51000)
   vapi_id     =  (default: 0)
*/
section debug
  enabled = 1
  rsp_enabled = 1
  rsp_port    = 9999
end
 
 
/* Memory controller section
 
   enabled  = 0|1
   baseaddr =  (default: 0)
   POC      =  (default: 0)
   index    =  (default: 0)
*/
 
section mc
  enabled  = 0
  baseaddr = 0x93000000
  POC      = 0x0000000a                 /* 32 bit SSRAM */
  index    = 0
end
 
 
/* UART section
 
   enabled  = 0|1
   baseaddr =  (default: 0)
   channel  = "value>" (default: "xterm:")
   irq      =  (default: 0)
   16550    = 0|1
   jitter   =  (default: 0)
   vapi_id  =  (default: 0)
*/
 
section uart
  enabled  = 1
  baseaddr = 0x90000000
  irq      = 2
  16550    = 1
end
 
 
/* DMA section
 
   enabled  = 0|1
   baseaddr =  (default: 0)
   irq      =  (default: 0)
   vapi_id  =  (default: 0)
*/
section dma
  enabled  = 0
  baseaddr = 0x9a000000
  irq      = 11
end
 
 
/* Ethernet section
 
   enabled    = 0|1
   baseaddr   =  (default: 0)
   dma        =  (default: 0)
   irq        =  (default: 0)
   rtx_type   = 0|1
   rx_channel =  (default: 0)
   tx_channel =  (default: 0)
   rxfile     = "" (default: "eth_rx")
   txfile     = "" (default: "eth_rx")
   sockif     = "" (default: "or1ksim_eth")
   vapi_id    =  (default: 0)
*/
section ethernet
  enabled  = 0
  baseaddr = 0x92000000
  irq      = 4
  rtx_type = 0
end
 
 
/* GPIO section
 
   enabled      = 0|1
   baseaddr     =  (default: 0)
   irq          =  (default: 0)
   base_vapi_id =  (default: 0)
*/
section gpio
  enabled      = 1
  baseaddr     = 0x91000000
  irq          = 3
  base_vapi_id = 0x0200
end
 
/* VGA section
 
   enabled      = 0|1
   baseaddr     =  (default: 0)
   irq          =  (default: 0)
   refresh_rate =  (default: cycles equivalent to 50Hz)
   filename     = "" (default: "vga_out))
*/
section vga
  enabled      = 0
  baseaddr     = 0x97100000
  irq          = 8
end
 
 
/* Frame buffer section
 
   enabled      = 0|1
   baseaddr     =  (default: 0)
   refresh_rate =  (default: cycles equivalent to 50Hz)
   filename     = "" (default: "fb_out))
*/
section fb
  enabled      = 0
  baseaddr     = 0x97000000
end
 
 
/* PS2 keyboard section
 
    This section configures the PS/2 compatible keyboard
 
    enabled  = 0|1
    baseaddr =  (default: 0)
    irq      =  (default: 0)
    rxfile   = "" (default: "kbd_in")
*/
section kbd
  enabled  = 0
  baseaddr = 0x94000000
  irq      = 5
end
 
 
/* ATA disc section
 
   enabled        = 0|1
   baseaddr       =  (default: 0)
   irq            =  (default: 0)
   dev_id         = 1|2|3
   rev            = 0-15 (default: 1)
   pio_mode0_t1   = 0-255 (default: 6)
   pio_mode0_t2   = 0-255 (default: 28)
   pio_mode0_t4   = 0-255 (default: 2)
   pio_mode0_teoc = 0-255 (default: 23)
   dma_mode0_tm   = 0-255 (default: 4)
   dma_mode0_td   = 0-255 (default: 21)
   dma_mode0_teoc = 0-255 (default: 21)
   device         = 0|1
 
   Device specific:
 
      type     = 0|1|2
      file     = "" (default: "ata_file")
      size     =  (default: 0)
      packet   = 0|1
      firmware = "" (default: "02207031")
      heads    =  (default: 7)
      sectors  =  (default: 32)
      mwdma    = 2|1|0|-1
      pio      = 4|3|2|1|0
*/
section ata
  enabled  = 0
  baseaddr = 0x9e000000
  irq      = 15
 
  device 0
    type = 1
    size = 1
  enddevice
end
 
 
/* Generic peripheral section
 
   enabled      = 0|1
   baseaddr     =  (default: 0)
   size         =  (default: 0)
   name         = "" (default: "anonymous external peripheral")
   byte_enabled = 1|0
   hw_enabled   = 1|0
   word_enabled = 1|0
*/
section generic
  enabled  = 0
end

Line No.	Rev	Author	Line
1	584	jeremybenn	`/* sim.cfg -- Simulator configuration script file`
2	621	filepang
3	584	jeremybenn	`Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org`
4	621	filepang	`Copyright (C) 2010, Embecosm Limited`
5	584	jeremybenn
6	621	filepang	`Contributor Jeremy Bennett`
7	584	jeremybenn
8	621	filepang	`This file is part of OpenRISC 1000 Architectural Simulator.`
9
10			`This program is free software; you can redistribute it and/or modify it`
11			`under the terms of the GNU General Public License as published by the Free`
12			`Software Foundation; either version 3 of the License, or (at your option)`
13			`any later version.`
14
15			`This program is distributed in the hope that it will be useful, but WITHOUT`
16			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
17			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
18			`more details.`
19
20			`You should have received a copy of the GNU General Public License along`
21			`with this program. If not, see . */`
22	584	jeremybenn
23
24	621	filepang	`/* -------------------------------------------------------------------------- */`
25			`/* The Ork1sim has various parameters, that can be set in configuration files`
26			`like this one. The user can specify a configuration file at startu[ with`
27			`the -f option.`
28	584	jeremybenn
29	621	filepang	`The user guide (see the 'doc' directory) gives full details on`
30			`configuration files. This is a reference configuration, which may be used`
31			`as a starting point for customization.`
32	584	jeremybenn
33	621	filepang	`A number of peripherals are mapped at standard addresses (above 0x80000000)`
34			`in the Verilog RTL of ORPSoC standard sitribution. The same values should`
35			`be used in Or1ksim section definitions to match the behavior of the Verilog`
36	584	jeremybenn
37	621	filepang	`0x90000000 UART`
38			`0x91000000 GPIO`
39			`0x92000000 Ethernet`
40			`0x93000000 Memory controller`
41			`0x94000000 PS2 keyboard`
42			`0x97000000 Frame buffer`
43			`0x97100000 VGA`
44			`0x9a000000 DMA controller`
45			`0x9e000000 ATA disc`
46	584	jeremybenn
47	621	filepang	`Section ordering matches that in the user guide. All optional peripherals`
48			`and functionality is disabled. Comments only list the possible entries and`
49			`values. Consult the user guide for their meaning.`
50	584	jeremybenn
51	621	filepang	`Unless otherwise indicated, the first named option is the default. */`
52			`/* -------------------------------------------------------------------------- */`
53	584	jeremybenn
54
55	621	filepang	`/* Simulator section`
56	584	jeremybenn
57	621	filepang	`verbose = 0\|1`
58			`debug = 0-9`
59			`profile = 0\|1`
60			`prof_file = "" (default: "sim.profile")`
61			`mprofile = 0\|1`
62			`mprof_file = "" (default: "sim.mprofile")`
63			`history = 0\|1`
64			`exe_log = 0\|1`
65			`exe_log_type = hardware\|simple\|software\|default`
66			`exe_log_start = (default: 0)`
67			`exe_log_end = (default: never end)`
68			`exe_log_marker = (default: no markers)`
69			`exe_log_file = "" (default: "executed.log")`
70			`exe_bin_insn_log = 0\|1`
71			`exe_bin_insn_log_file = "" (default: "exe-insn.bin")`
72			`clkcycle = [ps\|ns\|us\|ms]`
73	584	jeremybenn	`*/`
74	621	filepang	`section sim`
75			`clkcycle = 100ns`
76			`end`
77	584	jeremybenn
78
79	621	filepang	`/* VAPI section`
80	584	jeremybenn
81	621	filepang	`enabled = 0\|1`
82			`server_port = (default: 50000)`
83			`log_enabled = 0\|1`
84			`hide_device_id = 0\|1`
85			`vapi_log_file = "" (default "vapi.log")`
86			`*/`
87			`section VAPI`
88			`server_port = 50000`
89			`log_enabled = 0`
90			`vapi_log_file = "vapi.log"`
91			`end`
92	584	jeremybenn
93
94	621	filepang	`/* CUC section`
95	584	jeremybenn
96	621	filepang	`memory_order = none\|weak\|strong\|exact (default: strong)`
97			`calling_convention = 0\|1`
98			`enable_bursts = 0\|1`
99			`no_multicycle = 0\|1`
100			`timings_file = "" (default: virtex.tim)`
101	584	jeremybenn	`*/`
102	621	filepang	`section cuc`
103			`memory_order = weak`
104			`calling_convention = 1`
105			`enable_bursts = 1`
106			`no_multicycle = 1`
107	584	jeremybenn	`end`
108
109
110	621	filepang	`/* CPU section`
111	584	jeremybenn
112	621	filepang	`ver = (default: 0)`
113			`cfg = (default: 0)`
114			`rev = (default: 0)`
115			`upr = (see user manual for default settings)`
116			`cfgr = (default: 0x00000020)`
117			`sr = (default: 0x00008001)`
118			`superscalar = 0\|1`
119			`hazards = 0\|1`
120			`dependstats = 0\|1`
121			`sbuf_len = (default: 0)`
122			`hardfloat = 0\|1`
123			`*/`
124			`section cpu`
125			`ver = 0x12`
126			`cfg = 0x00`
127			`rev = 0x0001`
128	584	jeremybenn	`end`
129
130
131	621	filepang	`/* Memory section`
132	584	jeremybenn
133	621	filepang	`type = unknown\|random\|unknown\|pattern`
134			`random_seed = (default: -1)`
135			`pattern = (default: 0)`
136			`baseaddr = (default: 0)`
137			`size = (default: 1024)`
138			`name = "" (default: "anonymous memory block")`
139			`ce = (default: -1)`
140			`mc = (default: 0)`
141			`delayr = (default: 1)`
142			`delayw = (default: 1)`
143			`log = "" (default: NULL)`
144	584	jeremybenn	`*/`
145	621	filepang	`section memory`
146			`name = "RAM"`
147			`type = unknown`
148			`baseaddr = 0x00000000`
149			`size = 0x00080000`
150			`delayr = 1`
151			`delayw = 2`
152	584	jeremybenn	`end`
153
154
155	621	filepang	`/* Data MMU section`
156	584	jeremybenn
157	621	filepang	`enabled = 0\|1`
158			`nsets = (default: 1)`
159			`nways = (default: 1)`
160			`pagesize = (default: 8192)`
161			`entrysize = (default: 1)`
162			`ustates = (default: 1)`
163			`hitdelay = (default: 1)`
164			`missdelay = (default: 1)`
165	584	jeremybenn	`*/`
166			`section dmmu`
167	621	filepang	`enabled = 0`
168			`nsets = 64`
169			`nways = 1`
170			`pagesize = 8192`
171			`hitdelay = 0`
172			`missdelay = 0`
173	584	jeremybenn	`end`
174
175
176	621	filepang	`/* Instruction MMU section`
177	584	jeremybenn
178	621	filepang	`enabled = 0\|1`
179			`nsets = (default: 1)`
180			`nways = (default: 1)`
181			`pagesize = (default: 8192)`
182			`entrysize = (default: 1)`
183			`ustates = (default: 1)`
184			`hitdelay = (default: 1)`
185			`missdelay = (default: 1)`
186	584	jeremybenn	`*/`
187	621	filepang	`section immu`
188			`enabled = 0`
189			`nsets = 64`
190			`nways = 1`
191			`pagesize = 8192`
192			`hitdelay = 0`
193			`missdelay = 0`
194	584	jeremybenn	`end`
195
196
197	621	filepang	`/* Data cache section`
198	584	jeremybenn
199	621	filepang	`enabled = 0\|1`
200			`nsets = (default: 1)`
201			`nways = (default: 1)`
202			`blocksize = (default: 16)`
203			`ustates = (default: 2)`
204			`load_hitdelay = (default: 2)`
205			`load_missdelay = (default: 2)`
206			`store_hitdelay = (default: 0)`
207			`store_missdelay = (default: 0)`
208	584	jeremybenn	`*/`
209
210			`section dc`
211	621	filepang	`enabled = 0`
212			`nsets = 256`
213			`nways = 1`
214			`blocksize = 16`
215			`load_hitdelay = 0`
216			`load_missdelay = 0`
217			`store_hitdelay = 0`
218			`store_missdelay = 0`
219	584	jeremybenn	`end`
220
221
222	621	filepang	`/* Instruction cache section`
223	584	jeremybenn
224	621	filepang	`enabled = 0\|1`
225			`nsets = (default: 1)`
226			`nways = (default: 1)`
227			`blocksize = (default: 16)`
228			`ustates = (default: 2)`
229			`hitdelay = (default: 1)`
230			`missdelay = (default: 1)`
231	584	jeremybenn	`*/`
232	621	filepang	`section ic`
233			`enabled = 0`
234			`nsets = 256`
235			`nways = 1`
236			`blocksize = 16`
237			`hitdelay = 0`
238			`missdelay = 0`
239	584	jeremybenn	`end`
240
241
242	621	filepang	`/* Programmable interrupt controller section`
243	584	jeremybenn
244	621	filepang	`enabled = 0\|1`
245			`edge_trigger = 0\|1 (default: 1)`
246	584	jeremybenn	`*/`
247
248	621	filepang	`section pic`
249			`enabled = 1`
250	584	jeremybenn	`end`
251
252
253	621	filepang	`/* Power management section`
254	584	jeremybenn
255	621	filepang	`enabled = 0\|1`
256	584	jeremybenn	`*/`
257
258			`section pm`
259			`enabled = 0`
260			`end`
261
262
263	621	filepang	`/* Branch prediction section`
264	584	jeremybenn
265	621	filepang	`enabled = 0\|1`
266			`btic = 0\|1`
267			`sbp_bf_fwd = 0\|1`
268			`sbp_bnf_fwd = 0\|1`
269			`hitdelay = (default: 0)`
270			`missdelay = (default: 0)`
271	584	jeremybenn	`*/`
272
273			`section bpb`
274	621	filepang	`enabled = 0`
275	584	jeremybenn	`end`
276
277
278	621	filepang	`/* Debug unit section`
279	584	jeremybenn
280	621	filepang	`enabled = 0\|1`
281			`rsp_enabled = 0\|1`
282			`rsp_port = (default: 51000)`
283			`vapi_id = (default: 0)`
284	584	jeremybenn	`*/`
285			`section debug`
286			`enabled = 1`
287	621	filepang	`rsp_enabled = 1`
288			`rsp_port = 9999`
289	584	jeremybenn	`end`
290
291
292	621	filepang	`/* Memory controller section`
293	584	jeremybenn
294	621	filepang	`enabled = 0\|1`
295			`baseaddr = (default: 0)`
296			`POC = (default: 0)`
297			`index = (default: 0)`
298	584	jeremybenn	`*/`
299
300			`section mc`
301	621	filepang	`enabled = 0`
302			`baseaddr = 0x93000000`
303			`POC = 0x0000000a /* 32 bit SSRAM */`
304			`index = 0`
305	584	jeremybenn	`end`
306
307
308	621	filepang	`/* UART section`
309	584	jeremybenn
310	621	filepang	`enabled = 0\|1`
311			`baseaddr = (default: 0)`
312			`channel = "value>" (default: "xterm:")`
313			`irq = (default: 0)`
314			`16550 = 0\|1`
315			`jitter = (default: 0)`
316			`vapi_id = (default: 0)`
317	584	jeremybenn	`*/`
318
319			`section uart`
320	621	filepang	`enabled = 1`
321	584	jeremybenn	`baseaddr = 0x90000000`
322	621	filepang	`irq = 2`
323			`16550 = 1`
324	584	jeremybenn	`end`
325
326
327	621	filepang	`/* DMA section`
328	584	jeremybenn
329	621	filepang	`enabled = 0\|1`
330			`baseaddr = (default: 0)`
331			`irq = (default: 0)`
332			`vapi_id = (default: 0)`
333	584	jeremybenn	`*/`
334			`section dma`
335	621	filepang	`enabled = 0`
336	584	jeremybenn	`baseaddr = 0x9a000000`
337	621	filepang	`irq = 11`
338	584	jeremybenn	`end`
339
340
341	621	filepang	`/* Ethernet section`
342	584	jeremybenn
343	621	filepang	`enabled = 0\|1`
344			`baseaddr = (default: 0)`
345			`dma = (default: 0)`
346			`irq = (default: 0)`
347			`rtx_type = 0\|1`
348			`rx_channel = (default: 0)`
349			`tx_channel = (default: 0)`
350			`rxfile = "" (default: "eth_rx")`
351			`txfile = "" (default: "eth_rx")`
352			`sockif = "" (default: "or1ksim_eth")`
353			`vapi_id = (default: 0)`
354	584	jeremybenn	`*/`
355			`section ethernet`
356	621	filepang	`enabled = 0`
357	584	jeremybenn	`baseaddr = 0x92000000`
358	621	filepang	`irq = 4`
359	584	jeremybenn	`rtx_type = 0`
360			`end`
361
362
363	621	filepang	`/* GPIO section`
364	584	jeremybenn
365	621	filepang	`enabled = 0\|1`
366			`baseaddr = (default: 0)`
367			`irq = (default: 0)`
368			`base_vapi_id = (default: 0)`
369	584	jeremybenn	`*/`
370			`section gpio`
371	621	filepang	`enabled = 1`
372			`baseaddr = 0x91000000`
373			`irq = 3`
374	584	jeremybenn	`base_vapi_id = 0x0200`
375			`end`
376
377	621	filepang	`/* VGA section`
378	584	jeremybenn
379	621	filepang	`enabled = 0\|1`
380			`baseaddr = (default: 0)`
381			`irq = (default: 0)`
382			`refresh_rate = (default: cycles equivalent to 50Hz)`
383			`filename = "" (default: "vga_out))`
384	584	jeremybenn	`*/`
385			`section vga`
386	621	filepang	`enabled = 0`
387			`baseaddr = 0x97100000`
388			`irq = 8`
389	584	jeremybenn	`end`
390
391
392	621	filepang	`/* Frame buffer section`
393	584	jeremybenn
394	621	filepang	`enabled = 0\|1`
395			`baseaddr = (default: 0)`
396			`refresh_rate = (default: cycles equivalent to 50Hz)`
397			`filename = "" (default: "fb_out))`
398	584	jeremybenn	`*/`
399			`section fb`
400	621	filepang	`enabled = 0`
401			`baseaddr = 0x97000000`
402	584	jeremybenn	`end`
403
404
405	621	filepang	`/* PS2 keyboard section`
406
407	584	jeremybenn	`This section configures the PS/2 compatible keyboard`
408
409	621	filepang	`enabled = 0\|1`
410			`baseaddr = (default: 0)`
411			`irq = (default: 0)`
412			`rxfile = "" (default: "kbd_in")`
413	584	jeremybenn	`*/`
414			`section kbd`
415	621	filepang	`enabled = 0`
416	584	jeremybenn	`baseaddr = 0x94000000`
417	621	filepang	`irq = 5`
418	584	jeremybenn	`end`
419
420	621	filepang
421			`/* ATA disc section`
422	584	jeremybenn
423	621	filepang	`enabled = 0\|1`
424			`baseaddr = (default: 0)`
425			`irq = (default: 0)`
426			`dev_id = 1\|2\|3`
427			`rev = 0-15 (default: 1)`
428			`pio_mode0_t1 = 0-255 (default: 6)`
429			`pio_mode0_t2 = 0-255 (default: 28)`
430			`pio_mode0_t4 = 0-255 (default: 2)`
431			`pio_mode0_teoc = 0-255 (default: 23)`
432			`dma_mode0_tm = 0-255 (default: 4)`
433			`dma_mode0_td = 0-255 (default: 21)`
434			`dma_mode0_teoc = 0-255 (default: 21)`
435			`device = 0\|1`
436	584	jeremybenn
437	621	filepang	`Device specific:`
438	584	jeremybenn
439	621	filepang	`type = 0\|1\|2`
440			`file = "" (default: "ata_file")`
441			`size = (default: 0)`
442			`packet = 0\|1`
443			`firmware = "" (default: "02207031")`
444			`heads = (default: 7)`
445			`sectors = (default: 32)`
446			`mwdma = 2\|1\|0\|-1`
447			`pio = 4\|3\|2\|1\|0`
448	584	jeremybenn	`*/`
449			`section ata`
450	621	filepang	`enabled = 0`
451	584	jeremybenn	`baseaddr = 0x9e000000`
452	621	filepang	`irq = 15`
453	584	jeremybenn
454	621	filepang	`device 0`
455			`type = 1`
456			`size = 1`
457			`enddevice`
458			`end`
459	584	jeremybenn
460	621	filepang
461			`/* Generic peripheral section`
462
463			`enabled = 0\|1`
464			`baseaddr = (default: 0)`
465			`size = (default: 0)`
466			`name = "" (default: "anonymous external peripheral")`
467			`byte_enabled = 1\|0`
468			`hw_enabled = 1\|0`
469			`word_enabled = 1\|0`
470			`*/`
471			`section generic`
472			`enabled = 0`
473	584	jeremybenn	`end`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [OpenRISC_SIM_GCC/] [sim.cfg] - Blame information for rev 622