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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PIC32MX_MPLAB/] [RegisterTestTasks.s] - Blame information for rev 622

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/*
    FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
 
    ***************************************************************************
    *                                                                         *
    * If you are:                                                             *
    *                                                                         *
    *    + New to FreeRTOS,                                                   *
    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *
    *    + Looking for basic training,                                        *
    *    + Wanting to improve your FreeRTOS skills and productivity           *
    *                                                                         *
    * then take a look at the FreeRTOS books - available as PDF or paperback  *
    *                                                                         *
    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *
    *                  http://www.FreeRTOS.org/Documentation                  *
    *                                                                         *
    * A pdf reference manual is also available.  Both are usually delivered   *
    * to your inbox within 20 minutes to two hours when purchased between 8am *
    * and 8pm GMT (although please allow up to 24 hours in case of            *
    * exceptional circumstances).  Thank you for your support!                *
    *                                                                         *
    ***************************************************************************
 
    This file is part of the FreeRTOS distribution.
 
    FreeRTOS is free software; you can redistribute it and/or modify it under
    the terms of the GNU General Public License (version 2) as published by the
    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
    ***NOTE*** The exception to the GPL is included to allow you to distribute
    a combined work that includes FreeRTOS without being obliged to provide the
    source code for proprietary components outside of the FreeRTOS kernel.
    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
    more details. You should have received a copy of the GNU General Public
    License and the FreeRTOS license exception along with FreeRTOS; if not it 
    can be viewed here: http://www.freertos.org/a00114.html and also obtained
    by writing to Richard Barry, contact details for whom are available on the
    FreeRTOS WEB site.
 
    1 tab == 4 spaces!
 
    http://www.FreeRTOS.org - Documentation, latest information, license and
    contact details.
 
    http://www.SafeRTOS.com - A version that is certified for use in safety
    critical systems.
 
    http://www.OpenRTOS.com - Commercial support, development, porting,
    licensing and training services.
*/
 
 
#include <p32xxxx.h>
#include <sys/asm.h>
 
        .set    nomips16
        .set    noreorder
 
 
        .global vRegTest1
        .global vRegTest2
 
 
/*      .section        .FreeRTOS, ax, @progbits */
        .set            noreorder
        .set            noat
        .ent            vRegTest1
 
/* Address of $4 ulStatus1 is held in A0, so don't mess with the value of $4 */
 
vRegTest1:
                        addiu   $1, $0, 0x11
                        addiu   $2, $0, 0x12
                        addiu   $3, $0, 0x13
                        addiu   $5, $0, 0x15
                        addiu   $6, $0, 0x16
                        addiu   $7, $0, 0x17
                        addiu   $8, $0, 0x18
                        addiu   $9, $0, 0x19
                        addiu   $10, $0, 0x110
                        addiu   $11, $0, 0x111
                        addiu   $12, $0, 0x112
                        addiu   $13, $0, 0x113
                        addiu   $14, $0, 0x114
                        addiu   $15, $0, 0x115
                        addiu   $16, $0, 0x116
                        addiu   $17, $0, 0x117
                        addiu   $18, $0, 0x118
                        addiu   $19, $0, 0x119
                        addiu   $20, $0, 0x120
                        addiu   $21, $0, 0x121
                        addiu   $22, $0, 0x122
                        addiu   $23, $0, 0x123
                        addiu   $24, $0, 0x124
                        addiu   $25, $0, 0x125
                        addiu   $30, $0, 0x130
 
                        addiu   $1, $1, -0x11
                        beq             $1, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $2, $2, -0x12
                        beq     $2, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $3, $3, -0x13
                        beq     $3, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $5, $5, -0x15
                        beq     $5, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $6, $6, -0x16
                        beq     $6, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $7, $7, -0x17
                        beq     $7, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $8, $8, -0x18
                        beq     $8, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $9, $9, -0x19
                        beq     $9, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $10, $10, -0x110
                        beq     $10, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $11, $11, -0x111
                        beq     $11, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $12, $12, -0x112
                        beq     $12, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $13, $13, -0x113
                        beq     $13, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $14, $14, -0x114
                        beq     $14, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $15, $15, -0x115
                        beq     $15, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $16, $16, -0x116
                        beq     $16, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $17, $17, -0x117
                        beq     $17, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $18, $18, -0x118
                        beq     $18, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $19, $19, -0x119
                        beq     $19, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $20, $20, -0x120
                        beq     $20, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $21, $21, -0x121
                        beq     $21, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $22, $22, -0x122
                        beq     $22, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $23, $23, -0x123
                        beq     $23, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $24, $24, -0x124
                        beq     $24, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $25, $25, -0x125
                        beq     $25, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $30, $30, -0x130
                        beq     $30, $0, .+12
                        nop
                        sw              $0,     0($4)
                        jr              $31
                        nop
 
        .end            vRegTest1
 
 
/*      .section        .FreeRTOS, ax, @progbits */
        .set            noreorder
        .set            noat
        .ent            vRegTest2
 
vRegTest2:
 
                        addiu   $1, $0, 0x10
                        addiu   $2, $0, 0x20
                        addiu   $3, $0, 0x30
                        addiu   $5, $0, 0x50
                        addiu   $6, $0, 0x60
                        addiu   $7, $0, 0x70
                        addiu   $8, $0, 0x80
                        addiu   $9, $0, 0x90
                        addiu   $10, $0, 0x100
                        addiu   $11, $0, 0x110
                        addiu   $12, $0, 0x120
                        addiu   $13, $0, 0x130
                        addiu   $14, $0, 0x140
                        addiu   $15, $0, 0x150
                        addiu   $16, $0, 0x160
                        addiu   $17, $0, 0x170
                        addiu   $18, $0, 0x180
                        addiu   $19, $0, 0x190
                        addiu   $20, $0, 0x200
                        addiu   $21, $0, 0x210
                        addiu   $22, $0, 0x220
                        addiu   $23, $0, 0x230
                        addiu   $24, $0, 0x240
                        addiu   $25, $0, 0x250
                        addiu   $30, $0, 0x300
 
                        addiu   $1, $1, -0x10
                        beq             $1, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $2, $2, -0x20
                        beq     $2, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $3, $3, -0x30
                        beq     $3, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $5, $5, -0x50
                        beq     $5, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $6, $6, -0x60
                        beq     $6, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $7, $7, -0x70
                        beq     $7, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $8, $8, -0x80
                        beq     $8, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $9, $9, -0x90
                        beq     $9, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $10, $10, -0x100
                        beq     $10, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $11, $11, -0x110
                        beq     $11, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $12, $12, -0x120
                        beq     $12, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $13, $13, -0x130
                        beq     $13, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $14, $14, -0x140
                        beq     $14, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $15, $15, -0x150
                        beq     $15, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $16, $16, -0x160
                        beq     $16, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $17, $17, -0x170
                        beq     $17, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $18, $18, -0x180
                        beq     $18, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $19, $19, -0x190
                        beq     $19, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $20, $20, -0x200
                        beq     $20, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $21, $21, -0x210
                        beq     $21, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $22, $22, -0x220
                        beq     $22, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $23, $23, -0x230
                        beq     $23, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $24, $24, -0x240
                        beq     $24, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $25, $25, -0x250
                        beq     $25, $0, .+12
                        nop
                        sw              $0,     0($4)
                        addiu   $30, $30, -0x300
                        beq     $30, $0, .+12
                        nop
                        sw              $0,     0($4)
                        jr              $31
                        nop
 
        .end vRegTest2

Browse

Tools

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PIC32MX_MPLAB/] [RegisterTestTasks.s] - Blame information for rev 622

Line No.	Rev	Author	Line
1	614	jeremybenn	`/*`
2			`FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.`
3
4			`***************************************************************************`
5			`* *`
6			`* If you are: *`
7			`* *`
8			`* + New to FreeRTOS, *`
9			`* + Wanting to learn FreeRTOS or multitasking in general quickly *`
10			`* + Looking for basic training, *`
11			`* + Wanting to improve your FreeRTOS skills and productivity *`
12			`* *`
13			`* then take a look at the FreeRTOS books - available as PDF or paperback *`
14			`* *`
15			`* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *`
16			`* http://www.FreeRTOS.org/Documentation *`
17			`* *`
18			`* A pdf reference manual is also available. Both are usually delivered *`
19			`* to your inbox within 20 minutes to two hours when purchased between 8am *`
20			`* and 8pm GMT (although please allow up to 24 hours in case of *`
21			`* exceptional circumstances). Thank you for your support! *`
22			`* *`
23			`***************************************************************************`
24
25			`This file is part of the FreeRTOS distribution.`
26
27			`FreeRTOS is free software; you can redistribute it and/or modify it under`
28			`the terms of the GNU General Public License (version 2) as published by the`
29			`Free Software Foundation AND MODIFIED BY the FreeRTOS exception.`
30			`*NOTE* The exception to the GPL is included to allow you to distribute`
31			`a combined work that includes FreeRTOS without being obliged to provide the`
32			`source code for proprietary components outside of the FreeRTOS kernel.`
33			`FreeRTOS is distributed in the hope that it will be useful, but WITHOUT`
34			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
35			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
36			`more details. You should have received a copy of the GNU General Public`
37			`License and the FreeRTOS license exception along with FreeRTOS; if not it`
38			`can be viewed here: http://www.freertos.org/a00114.html and also obtained`
39			`by writing to Richard Barry, contact details for whom are available on the`
40			`FreeRTOS WEB site.`
41
42			`1 tab == 4 spaces!`
43
44			`http://www.FreeRTOS.org - Documentation, latest information, license and`
45			`contact details.`
46
47			`http://www.SafeRTOS.com - A version that is certified for use in safety`
48			`critical systems.`
49
50			`http://www.OpenRTOS.com - Commercial support, development, porting,`
51			`licensing and training services.`
52			`*/`
53
54
55			`#include <p32xxxx.h>`
56			`#include <sys/asm.h>`
57
58			`.set nomips16`
59			`.set noreorder`
60
61
62			`.global vRegTest1`
63			`.global vRegTest2`
64
65
66			`/* .section .FreeRTOS, ax, @progbits */`
67			`.set noreorder`
68			`.set noat`
69			`.ent vRegTest1`
70
71			`/* Address of $4 ulStatus1 is held in A0, so don't mess with the value of $4 */`
72
73			`vRegTest1:`
74			`addiu $1, $0, 0x11`
75			`addiu $2, $0, 0x12`
76			`addiu $3, $0, 0x13`
77			`addiu $5, $0, 0x15`
78			`addiu $6, $0, 0x16`
79			`addiu $7, $0, 0x17`
80			`addiu $8, $0, 0x18`
81			`addiu $9, $0, 0x19`
82			`addiu $10, $0, 0x110`
83			`addiu $11, $0, 0x111`
84			`addiu $12, $0, 0x112`
85			`addiu $13, $0, 0x113`
86			`addiu $14, $0, 0x114`
87			`addiu $15, $0, 0x115`
88			`addiu $16, $0, 0x116`
89			`addiu $17, $0, 0x117`
90			`addiu $18, $0, 0x118`
91			`addiu $19, $0, 0x119`
92			`addiu $20, $0, 0x120`
93			`addiu $21, $0, 0x121`
94			`addiu $22, $0, 0x122`
95			`addiu $23, $0, 0x123`
96			`addiu $24, $0, 0x124`
97			`addiu $25, $0, 0x125`
98			`addiu $30, $0, 0x130`
99
100			`addiu $1, $1, -0x11`
101			`beq $1, $0, .+12`
102			`nop`
103			`sw $0, 0($4)`
104			`addiu $2, $2, -0x12`
105			`beq $2, $0, .+12`
106			`nop`
107			`sw $0, 0($4)`
108			`addiu $3, $3, -0x13`
109			`beq $3, $0, .+12`
110			`nop`
111			`sw $0, 0($4)`
112			`addiu $5, $5, -0x15`
113			`beq $5, $0, .+12`
114			`nop`
115			`sw $0, 0($4)`
116			`addiu $6, $6, -0x16`
117			`beq $6, $0, .+12`
118			`nop`
119			`sw $0, 0($4)`
120			`addiu $7, $7, -0x17`
121			`beq $7, $0, .+12`
122			`nop`
123			`sw $0, 0($4)`
124			`addiu $8, $8, -0x18`
125			`beq $8, $0, .+12`
126			`nop`
127			`sw $0, 0($4)`
128			`addiu $9, $9, -0x19`
129			`beq $9, $0, .+12`
130			`nop`
131			`sw $0, 0($4)`
132			`addiu $10, $10, -0x110`
133			`beq $10, $0, .+12`
134			`nop`
135			`sw $0, 0($4)`
136			`addiu $11, $11, -0x111`
137			`beq $11, $0, .+12`
138			`nop`
139			`sw $0, 0($4)`
140			`addiu $12, $12, -0x112`
141			`beq $12, $0, .+12`
142			`nop`
143			`sw $0, 0($4)`
144			`addiu $13, $13, -0x113`
145			`beq $13, $0, .+12`
146			`nop`
147			`sw $0, 0($4)`
148			`addiu $14, $14, -0x114`
149			`beq $14, $0, .+12`
150			`nop`
151			`sw $0, 0($4)`
152			`addiu $15, $15, -0x115`
153			`beq $15, $0, .+12`
154			`nop`
155			`sw $0, 0($4)`
156			`addiu $16, $16, -0x116`
157			`beq $16, $0, .+12`
158			`nop`
159			`sw $0, 0($4)`
160			`addiu $17, $17, -0x117`
161			`beq $17, $0, .+12`
162			`nop`
163			`sw $0, 0($4)`
164			`addiu $18, $18, -0x118`
165			`beq $18, $0, .+12`
166			`nop`
167			`sw $0, 0($4)`
168			`addiu $19, $19, -0x119`
169			`beq $19, $0, .+12`
170			`nop`
171			`sw $0, 0($4)`
172			`addiu $20, $20, -0x120`
173			`beq $20, $0, .+12`
174			`nop`
175			`sw $0, 0($4)`
176			`addiu $21, $21, -0x121`
177			`beq $21, $0, .+12`
178			`nop`
179			`sw $0, 0($4)`
180			`addiu $22, $22, -0x122`
181			`beq $22, $0, .+12`
182			`nop`
183			`sw $0, 0($4)`
184			`addiu $23, $23, -0x123`
185			`beq $23, $0, .+12`
186			`nop`
187			`sw $0, 0($4)`
188			`addiu $24, $24, -0x124`
189			`beq $24, $0, .+12`
190			`nop`
191			`sw $0, 0($4)`
192			`addiu $25, $25, -0x125`
193			`beq $25, $0, .+12`
194			`nop`
195			`sw $0, 0($4)`
196			`addiu $30, $30, -0x130`
197			`beq $30, $0, .+12`
198			`nop`
199			`sw $0, 0($4)`
200			`jr $31`
201			`nop`
202
203			`.end vRegTest1`
204
205
206			`/* .section .FreeRTOS, ax, @progbits */`
207			`.set noreorder`
208			`.set noat`
209			`.ent vRegTest2`
210
211			`vRegTest2:`
212
213			`addiu $1, $0, 0x10`
214			`addiu $2, $0, 0x20`
215			`addiu $3, $0, 0x30`
216			`addiu $5, $0, 0x50`
217			`addiu $6, $0, 0x60`
218			`addiu $7, $0, 0x70`
219			`addiu $8, $0, 0x80`
220			`addiu $9, $0, 0x90`
221			`addiu $10, $0, 0x100`
222			`addiu $11, $0, 0x110`
223			`addiu $12, $0, 0x120`
224			`addiu $13, $0, 0x130`
225			`addiu $14, $0, 0x140`
226			`addiu $15, $0, 0x150`
227			`addiu $16, $0, 0x160`
228			`addiu $17, $0, 0x170`
229			`addiu $18, $0, 0x180`
230			`addiu $19, $0, 0x190`
231			`addiu $20, $0, 0x200`
232			`addiu $21, $0, 0x210`
233			`addiu $22, $0, 0x220`
234			`addiu $23, $0, 0x230`
235			`addiu $24, $0, 0x240`
236			`addiu $25, $0, 0x250`
237			`addiu $30, $0, 0x300`
238
239			`addiu $1, $1, -0x10`
240			`beq $1, $0, .+12`
241			`nop`
242			`sw $0, 0($4)`
243			`addiu $2, $2, -0x20`
244			`beq $2, $0, .+12`
245			`nop`
246			`sw $0, 0($4)`
247			`addiu $3, $3, -0x30`
248			`beq $3, $0, .+12`
249			`nop`
250			`sw $0, 0($4)`
251			`addiu $5, $5, -0x50`
252			`beq $5, $0, .+12`
253			`nop`
254			`sw $0, 0($4)`
255			`addiu $6, $6, -0x60`
256			`beq $6, $0, .+12`
257			`nop`
258			`sw $0, 0($4)`
259			`addiu $7, $7, -0x70`
260			`beq $7, $0, .+12`
261			`nop`
262			`sw $0, 0($4)`
263			`addiu $8, $8, -0x80`
264			`beq $8, $0, .+12`
265			`nop`
266			`sw $0, 0($4)`
267			`addiu $9, $9, -0x90`
268			`beq $9, $0, .+12`
269			`nop`
270			`sw $0, 0($4)`
271			`addiu $10, $10, -0x100`
272			`beq $10, $0, .+12`
273			`nop`
274			`sw $0, 0($4)`
275			`addiu $11, $11, -0x110`
276			`beq $11, $0, .+12`
277			`nop`
278			`sw $0, 0($4)`
279			`addiu $12, $12, -0x120`
280			`beq $12, $0, .+12`
281			`nop`
282			`sw $0, 0($4)`
283			`addiu $13, $13, -0x130`
284			`beq $13, $0, .+12`
285			`nop`
286			`sw $0, 0($4)`
287			`addiu $14, $14, -0x140`
288			`beq $14, $0, .+12`
289			`nop`
290			`sw $0, 0($4)`
291			`addiu $15, $15, -0x150`
292			`beq $15, $0, .+12`
293			`nop`
294			`sw $0, 0($4)`
295			`addiu $16, $16, -0x160`
296			`beq $16, $0, .+12`
297			`nop`
298			`sw $0, 0($4)`
299			`addiu $17, $17, -0x170`
300			`beq $17, $0, .+12`
301			`nop`
302			`sw $0, 0($4)`
303			`addiu $18, $18, -0x180`
304			`beq $18, $0, .+12`
305			`nop`
306			`sw $0, 0($4)`
307			`addiu $19, $19, -0x190`
308			`beq $19, $0, .+12`
309			`nop`
310			`sw $0, 0($4)`
311			`addiu $20, $20, -0x200`
312			`beq $20, $0, .+12`
313			`nop`
314			`sw $0, 0($4)`
315			`addiu $21, $21, -0x210`
316			`beq $21, $0, .+12`
317			`nop`
318			`sw $0, 0($4)`
319			`addiu $22, $22, -0x220`
320			`beq $22, $0, .+12`
321			`nop`
322			`sw $0, 0($4)`
323			`addiu $23, $23, -0x230`
324			`beq $23, $0, .+12`
325			`nop`
326			`sw $0, 0($4)`
327			`addiu $24, $24, -0x240`
328			`beq $24, $0, .+12`
329			`nop`
330			`sw $0, 0($4)`
331			`addiu $25, $25, -0x250`
332			`beq $25, $0, .+12`
333			`nop`
334			`sw $0, 0($4)`
335			`addiu $30, $30, -0x300`
336			`beq $30, $0, .+12`
337			`nop`
338			`sw $0, 0($4)`
339			`jr $31`
340			`nop`
341
342			`.end vRegTest2`