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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC405_FPU_Xilinx_Virtex4_GCC/] [RTOSDemo/] [RTOSDemo_linker_script.ld] - Blame information for rev 586

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/*******************************************************************/
/*                                                                 */
/* This file is automatically generated by linker script generator.*/
/*                                                                 */
/* Version: Xilinx EDK 10.1.01 EDK_K_SP1.3                                */
/*                                                                 */
/* Copyright (c) 2004 Xilinx, Inc.  All rights reserved.           */
/*                                                                 */
/* Description : PowerPC405 Linker Script                          */
/*                                                                 */
/*******************************************************************/
 
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x100;
 
/* Define Memories in the system */
 
MEMORY
{
   SRAM_C_MEM0_BASEADDR : ORIGIN = 0xFFF00000, LENGTH = 0x000FFFEC
}
 
/* Specify the default entry point to the program */
 
ENTRY(_boot)
STARTUP(boot.o)
 
/* Define the sections, and where they are mapped in memory */
 
SECTIONS
{
.vectors : {
   __vectors_start = .;
   *(.vectors)
   __vectors_end = .;
} > SRAM_C_MEM0_BASEADDR
 
.text : {
   *(.text)
   *(.text.*)
   *(.gnu.linkonce.t.*)
} > SRAM_C_MEM0_BASEADDR
 
.init : {
   KEEP (*(.init))
} > SRAM_C_MEM0_BASEADDR
 
.fini : {
   KEEP (*(.fini))
} > SRAM_C_MEM0_BASEADDR
 
.rodata : {
   __rodata_start = .;
   *(.rodata)
   *(.rodata.*)
   *(.gnu.linkonce.r.*)
   __rodata_end = .;
} > SRAM_C_MEM0_BASEADDR
 
.sdata2 : {
   __sdata2_start = .;
   *(.sdata2)
   *(.sdata2.*)
   *(.gnu.linkonce.s2.*)
   __sdata2_end = .;
} > SRAM_C_MEM0_BASEADDR
 
.sbss2 : {
   __sbss2_start = .;
   *(.sbss2)
   *(.sbss2.*)
   *(.gnu.linkonce.sb2.*)
   __sbss2_end = .;
} > SRAM_C_MEM0_BASEADDR
 
.data : {
   __data_start = .;
   *(.data)
   *(.data.*)
   *(.gnu.linkonce.d.*)
   __data_end = .;
} > SRAM_C_MEM0_BASEADDR
 
.got : {
   *(.got)
} > SRAM_C_MEM0_BASEADDR
 
.got1 : {
   *(.got1)
} > SRAM_C_MEM0_BASEADDR
 
.got2 : {
   *(.got2)
} > SRAM_C_MEM0_BASEADDR
 
.ctors : {
   __CTOR_LIST__ = .;
   ___CTORS_LIST___ = .;
   KEEP (*crtbegin.o(.ctors))
   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
   KEEP (*(SORT(.ctors.*)))
   KEEP (*(.ctors))
   __CTOR_END__ = .;
   ___CTORS_END___ = .;
} > SRAM_C_MEM0_BASEADDR
 
.dtors : {
   __DTOR_LIST__ = .;
   ___DTORS_LIST___ = .;
   KEEP (*crtbegin.o(.dtors))
   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
   KEEP (*(SORT(.dtors.*)))
   KEEP (*(.dtors))
   __DTOR_END__ = .;
   ___DTORS_END___ = .;
} > SRAM_C_MEM0_BASEADDR
 
.fixup : {
   __fixup_start = .;
   *(.fixup)
   __fixup_end = .;
} > SRAM_C_MEM0_BASEADDR
 
.eh_frame : {
   *(.eh_frame)
} > SRAM_C_MEM0_BASEADDR
 
.jcr : {
   *(.jcr)
} > SRAM_C_MEM0_BASEADDR
 
.gcc_except_table : {
   *(.gcc_except_table)
} > SRAM_C_MEM0_BASEADDR
 
.sdata : {
   __sdata_start = .;
   *(.sdata)
   *(.sdata.*)
   *(.gnu.linkonce.s.*)
   __sdata_end = .;
} > SRAM_C_MEM0_BASEADDR
 
.sbss : {
   __sbss_start = .;
   *(.sbss)
   *(.sbss.*)
   *(.gnu.linkonce.sb.*)
   __sbss_end = .;
} > SRAM_C_MEM0_BASEADDR
 
.tdata : {
   __tdata_start = .;
   *(.tdata)
   *(.tdata.*)
   *(.gnu.linkonce.td.*)
   __tdata_end = .;
} > SRAM_C_MEM0_BASEADDR
 
.tbss : {
   __tbss_start = .;
   *(.tbss)
   *(.tbss.*)
   *(.gnu.linkonce.tb.*)
   __tbss_end = .;
} > SRAM_C_MEM0_BASEADDR
 
.bss : {
   __bss_start = .;
   *(.bss)
   *(.bss.*)
   *(.gnu.linkonce.b.*)
   *(COMMON)
   . = ALIGN(4);
   __bss_end = .;
} > SRAM_C_MEM0_BASEADDR
 
.boot0 0xFFFFFFEC : {
   __boot0_start = .;
   *(.boot0)
   __boot0_end = .;
}
 
.boot 0xFFFFFFFC : {
   __boot_start = .;
   *(.boot)
   __boot_end = .;
}
 
/* Generate Stack and Heap Sections */
 
.stack : {
   _stack_end = .;
   . += _STACK_SIZE;
   . = ALIGN(16);
   __stack = .;
} > SRAM_C_MEM0_BASEADDR
 
.heap : {
   . = ALIGN(16);
   _heap_start = .;
   . += _HEAP_SIZE;
   . = ALIGN(16);
   _heap_end = .;
   _end = .;
} > SRAM_C_MEM0_BASEADDR
 
}
 

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC405_FPU_Xilinx_Virtex4_GCC/] [RTOSDemo/] [RTOSDemo_linker_script.ld] - Blame information for rev 586

Line No.	Rev	Author	Line
1	586	jeremybenn	`/*******************************************************************/`
2			`/* */`
3			`/* This file is automatically generated by linker script generator.*/`
4			`/* */`
5			`/* Version: Xilinx EDK 10.1.01 EDK_K_SP1.3 */`
6			`/* */`
7			`/* Copyright (c) 2004 Xilinx, Inc. All rights reserved. */`
8			`/* */`
9			`/* Description : PowerPC405 Linker Script */`
10			`/* */`
11			`/*******************************************************************/`
12
13			`_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;`
14			`_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x100;`
15
16			`/* Define Memories in the system */`
17
18			`MEMORY`
19			`{`
20			`SRAM_C_MEM0_BASEADDR : ORIGIN = 0xFFF00000, LENGTH = 0x000FFFEC`
21			`}`
22
23			`/* Specify the default entry point to the program */`
24
25			`ENTRY(_boot)`
26			`STARTUP(boot.o)`
27
28			`/* Define the sections, and where they are mapped in memory */`
29
30			`SECTIONS`
31			`{`
32			`.vectors : {`
33			`__vectors_start = .;`
34			`*(.vectors)`
35			`__vectors_end = .;`
36			`} > SRAM_C_MEM0_BASEADDR`
37
38			`.text : {`
39			`*(.text)`
40			`(.text.)`
41			`(.gnu.linkonce.t.)`
42			`} > SRAM_C_MEM0_BASEADDR`
43
44			`.init : {`
45			`KEEP (*(.init))`
46			`} > SRAM_C_MEM0_BASEADDR`
47
48			`.fini : {`
49			`KEEP (*(.fini))`
50			`} > SRAM_C_MEM0_BASEADDR`
51
52			`.rodata : {`
53			`__rodata_start = .;`
54			`*(.rodata)`
55			`(.rodata.)`
56			`(.gnu.linkonce.r.)`
57			`__rodata_end = .;`
58			`} > SRAM_C_MEM0_BASEADDR`
59
60			`.sdata2 : {`
61			`__sdata2_start = .;`
62			`*(.sdata2)`
63			`(.sdata2.)`
64			`(.gnu.linkonce.s2.)`
65			`__sdata2_end = .;`
66			`} > SRAM_C_MEM0_BASEADDR`
67
68			`.sbss2 : {`
69			`__sbss2_start = .;`
70			`*(.sbss2)`
71			`(.sbss2.)`
72			`(.gnu.linkonce.sb2.)`
73			`__sbss2_end = .;`
74			`} > SRAM_C_MEM0_BASEADDR`
75
76			`.data : {`
77			`__data_start = .;`
78			`*(.data)`
79			`(.data.)`
80			`(.gnu.linkonce.d.)`
81			`__data_end = .;`
82			`} > SRAM_C_MEM0_BASEADDR`
83
84			`.got : {`
85			`*(.got)`
86			`} > SRAM_C_MEM0_BASEADDR`
87
88			`.got1 : {`
89			`*(.got1)`
90			`} > SRAM_C_MEM0_BASEADDR`
91
92			`.got2 : {`
93			`*(.got2)`
94			`} > SRAM_C_MEM0_BASEADDR`
95
96			`.ctors : {`
97			`__CTOR_LIST__ = .;`
98			`___CTORS_LIST___ = .;`
99			`KEEP (*crtbegin.o(.ctors))`
100			`KEEP ((EXCLUDE_FILE(crtend.o) .ctors))`
101			`KEEP ((SORT(.ctors.)))`
102			`KEEP (*(.ctors))`
103			`__CTOR_END__ = .;`
104			`___CTORS_END___ = .;`
105			`} > SRAM_C_MEM0_BASEADDR`
106
107			`.dtors : {`
108			`__DTOR_LIST__ = .;`
109			`___DTORS_LIST___ = .;`
110			`KEEP (*crtbegin.o(.dtors))`
111			`KEEP ((EXCLUDE_FILE(crtend.o) .dtors))`
112			`KEEP ((SORT(.dtors.)))`
113			`KEEP (*(.dtors))`
114			`__DTOR_END__ = .;`
115			`___DTORS_END___ = .;`
116			`} > SRAM_C_MEM0_BASEADDR`
117
118			`.fixup : {`
119			`__fixup_start = .;`
120			`*(.fixup)`
121			`__fixup_end = .;`
122			`} > SRAM_C_MEM0_BASEADDR`
123
124			`.eh_frame : {`
125			`*(.eh_frame)`
126			`} > SRAM_C_MEM0_BASEADDR`
127
128			`.jcr : {`
129			`*(.jcr)`
130			`} > SRAM_C_MEM0_BASEADDR`
131
132			`.gcc_except_table : {`
133			`*(.gcc_except_table)`
134			`} > SRAM_C_MEM0_BASEADDR`
135
136			`.sdata : {`
137			`__sdata_start = .;`
138			`*(.sdata)`
139			`(.sdata.)`
140			`(.gnu.linkonce.s.)`
141			`__sdata_end = .;`
142			`} > SRAM_C_MEM0_BASEADDR`
143
144			`.sbss : {`
145			`__sbss_start = .;`
146			`*(.sbss)`
147			`(.sbss.)`
148			`(.gnu.linkonce.sb.)`
149			`__sbss_end = .;`
150			`} > SRAM_C_MEM0_BASEADDR`
151
152			`.tdata : {`
153			`__tdata_start = .;`
154			`*(.tdata)`
155			`(.tdata.)`
156			`(.gnu.linkonce.td.)`
157			`__tdata_end = .;`
158			`} > SRAM_C_MEM0_BASEADDR`
159
160			`.tbss : {`
161			`__tbss_start = .;`
162			`*(.tbss)`
163			`(.tbss.)`
164			`(.gnu.linkonce.tb.)`
165			`__tbss_end = .;`
166			`} > SRAM_C_MEM0_BASEADDR`
167
168			`.bss : {`
169			`__bss_start = .;`
170			`*(.bss)`
171			`(.bss.)`
172			`(.gnu.linkonce.b.)`
173			`*(COMMON)`
174			`. = ALIGN(4);`
175			`__bss_end = .;`
176			`} > SRAM_C_MEM0_BASEADDR`
177
178			`.boot0 0xFFFFFFEC : {`
179			`__boot0_start = .;`
180			`*(.boot0)`
181			`__boot0_end = .;`
182			`}`
183
184			`.boot 0xFFFFFFFC : {`
185			`__boot_start = .;`
186			`*(.boot)`
187			`__boot_end = .;`
188			`}`
189
190			`/* Generate Stack and Heap Sections */`
191
192			`.stack : {`
193			`_stack_end = .;`
194			`. += _STACK_SIZE;`
195			`. = ALIGN(16);`
196			`__stack = .;`
197			`} > SRAM_C_MEM0_BASEADDR`
198
199			`.heap : {`
200			`. = ALIGN(16);`
201			`_heap_start = .;`
202			`. += _HEAP_SIZE;`
203			`. = ALIGN(16);`
204			`_heap_end = .;`
205			`_end = .;`
206			`} > SRAM_C_MEM0_BASEADDR`
207
208			`}`
209