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jeremybenn |
#################################################################
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# Makefile generated by Xilinx Platform Studio
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# Project:C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_FPU_Xilinx_Virtex4_GCC\system.xmp
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#
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# WARNING : This file will be re-generated every time a command
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# to run a make target is invoked. So, any changes made to this
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# file manually, will be lost when make is invoked next.
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#################################################################
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# Name of the Microprocessor system
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# The hardware specification of the system is in file :
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# C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_FPU_Xilinx_Virtex4_GCC\system.mhs
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# The software specification of the system is in file :
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# C:\E\Dev\FreeRTOS\WorkingCopy2\Demo\PPC405_FPU_Xilinx_Virtex4_GCC\system.mss
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include system_incl.make
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#################################################################
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# PHONY TARGETS
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#################################################################
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.PHONY: dummy
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.PHONY: netlistclean
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.PHONY: bitsclean
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.PHONY: simclean
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.PHONY: vpclean
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#################################################################
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# EXTERNAL TARGETS
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#################################################################
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all:
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@echo "Makefile to build a Microprocessor system :"
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@echo "Run make with any of the following targets"
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@echo " "
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@echo " netlist : Generates the netlist for the given MHS "
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@echo " bits : Runs Implementation tools to generate the bitstream"
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@echo " "
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@echo " libs : Configures the sw libraries for this system"
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@echo " program : Compiles the program sources for all the processor instances"
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@echo " "
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@echo " init_bram: Initializes bitstream with BRAM data"
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@echo " ace : Generate ace file from bitstream and elf"
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@echo " download : Downloads the bitstream onto the board"
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@echo " "
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@echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode"
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@echo " simmodel : Generates HDL simulation models for chosen simulation mode"
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@echo " behavioral_model : Generates behavioral HDL models with BRAM initialization"
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@echo " structural_model : Generates structural simulation HDL models with BRAM initialization"
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@echo " timing : Generates timing simulation HDL models with BRAM initialization"
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@echo " vp : Generates virtual platform model"
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@echo " "
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@echo " netlistclean: Deletes netlist"
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@echo " bitsclean: Deletes bit, ncd, bmm files"
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@echo " hwclean : Deletes implementation dir"
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@echo " libsclean: Deletes sw libraries"
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@echo " programclean: Deletes compiled ELF files"
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@echo " swclean : Deletes sw libraries and ELF files"
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@echo " simclean : Deletes simulation dir"
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@echo " vpclean : Deletes virtualplatform dir"
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@echo " clean : Deletes all generated files/directories"
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@echo " "
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@echo " make : (Default)"
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@echo " Creates a Microprocessor system using default initializations"
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@echo " specified for each processor in MSS file"
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bits: $(SYSTEM_BIT)
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ace: $(SYSTEM_ACE)
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netlist: $(POSTSYN_NETLIST)
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libs: $(LIBRARIES)
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program: $(ALL_USER_ELF_FILES)
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download: $(DOWNLOAD_BIT) dummy
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@echo "*********************************************"
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@echo "Downloading Bitstream onto the target board"
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@echo "*********************************************"
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impact -batch etc/download.cmd
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init_bram: $(DOWNLOAD_BIT)
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sim: $(DEFAULT_SIM_SCRIPT)
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cd simulation/behavioral; \
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$(SIM_CMD) &
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simmodel: $(DEFAULT_SIM_SCRIPT)
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behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)
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structural_model: $(STRUCTURAL_SIM_SCRIPT)
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vp: $(VPEXEC)
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clean: hwclean libsclean programclean simclean vpclean
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rm -f _impact.cmd
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rm -f *.log
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hwclean: netlistclean bitsclean
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rm -rf implementation synthesis xst hdl
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rm -rf xst.srp $(SYSTEM).srp
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netlistclean:
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rm -f $(POSTSYN_NETLIST)
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rm -f platgen.log
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rm -f $(BMM_FILE)
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bitsclean:
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rm -f $(SYSTEM_BIT)
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rm -f implementation/$(SYSTEM).ncd
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rm -f implementation/$(SYSTEM)_bd.bmm
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rm -f implementation/$(SYSTEM)_map.ncd
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simclean:
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rm -rf simulation/behavioral
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rm -f simgen.log
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swclean: libsclean programclean
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@echo ""
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libsclean: $(LIBSCLEAN_TARGETS)
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rm -f libgen.log
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programclean: $(PROGRAMCLEAN_TARGETS)
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vpclean:
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rm -rf virtualplatform
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rm -f vpgen.log
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#################################################################
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# SOFTWARE PLATFORM FLOW
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#################################################################
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$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt
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@echo "*********************************************"
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@echo "Creating software libraries..."
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@echo "*********************************************"
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libgen $(LIBGEN_OPTIONS) $(MSSFILE)
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ppc405_0_libsclean:
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rm -rf ppc405_0/
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#################################################################
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# SOFTWARE APPLICATION RTOSDEMO
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#################################################################
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RTOSDemo_program: $(RTOSDEMO_OUTPUT)
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$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \
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$(LIBRARIES) __xps/rtosdemo_compiler.opt
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@mkdir -p $(RTOSDEMO_OUTPUT_DIR)
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$(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \
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$(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \
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$(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS)
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$(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT)
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@echo ""
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RTOSDemo_programclean:
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rm -f $(RTOSDEMO_OUTPUT)
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#################################################################
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# BOOTLOOP ELF FILES
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#################################################################
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$(PPC405_0_BOOTLOOP): $(PPC405_BOOTLOOP)
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@mkdir -p $(BOOTLOOP_DIR)
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cp -f $(PPC405_BOOTLOOP) $(PPC405_0_BOOTLOOP)
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#################################################################
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# HARDWARE IMPLEMENTATION FLOW
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#################################################################
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$(BMM_FILE) \
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$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
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$(CORE_STATE_DEVELOPMENT_FILES)
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@echo "****************************************************"
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@echo "Creating system netlist for hardware specification.."
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@echo "****************************************************"
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platgen $(PLATGEN_OPTIONS) $(MHSFILE)
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$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)
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@echo "Running synthesis..."
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bash -c "cd synthesis; ./synthesis.sh"
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__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY)
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@echo "*********************************************"
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@echo "Running Xilinx Implementation tools.."
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@echo "*********************************************"
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@cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf
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xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/manage_fastruntime_opt.pl $(MANAGE_FASTRT_OPTIONS)
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xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc
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touch __xps/$(SYSTEM)_routed
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$(SYSTEM_BIT): __xps/$(SYSTEM)_routed
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xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par
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@echo "*********************************************"
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@echo "Running Bitgen.."
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@echo "*********************************************"
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@cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut
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cd implementation; bitgen -w -f bitgen.ut $(SYSTEM)
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$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt
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# @cp -f implementation/$(SYSTEM)_bd.bmm .
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@echo "*********************************************"
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@echo "Initializing BRAM contents of the bitstream"
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@echo "*********************************************"
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bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \
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-bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)
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@rm -f $(SYSTEM)_bd.bmm
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$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT)
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@echo "*********************************************"
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@echo "Creating system ace file"
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@echo "*********************************************"
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xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT) -target ppc_hw -ace $(SYSTEM_ACE)
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#################################################################
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# SIMULATION FLOW
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#################################################################
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################## BEHAVIORAL SIMULATION ##################
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$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \
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$(BRAMINIT_ELF_FILES)
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@echo "*********************************************"
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@echo "Creating behavioral simulation models..."
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@echo "*********************************************"
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simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)
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################## STRUCTURAL SIMULATION ##################
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$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \
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$(BRAMINIT_ELF_FILES)
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@echo "*********************************************"
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@echo "Creating structural simulation models..."
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@echo "*********************************************"
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simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)
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################## TIMING SIMULATION ##################
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$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \
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$(BRAMINIT_ELF_FILES)
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@echo "*********************************************"
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@echo "Creating timing simulation models..."
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@echo "*********************************************"
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simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)
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#################################################################
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# VIRTUAL PLATFORM FLOW
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#################################################################
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$(VPEXEC): $(MHSFILE) __xps/vpgen.opt
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@echo "****************************************************"
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@echo "Creating virtual platform for hardware specification.."
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@echo "****************************************************"
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vpgen $(VPGEN_OPTIONS) $(MHSFILE)
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dummy:
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@echo ""
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