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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC405_FPU_Xilinx_Virtex4_GCC/] [system.mhs] - Blame information for rev 620

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Line No. Rev Author Line
1 586 jeremybenn 
 
2 
# ##############################################################################
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# Created by Base System Builder Wizard for Xilinx EDK 10.1.01 Build EDK_K_SP1.3
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# Fri May 09 11:01:33 2008
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# Target Board:  Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
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# Family:    virtex4
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# Device:    xc4vfx12
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# Package:   ff668
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# Speed Grade:  -10
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# Processor: ppc405_0
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# Processor clock frequency: 200.00 MHz
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# Bus clock frequency: 100.00 MHz
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# Total Off Chip Memory :   1 MB
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# - SRAM =   1 MB
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# ##############################################################################
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 PARAMETER VERSION = 2.1.0
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 PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I
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 PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O
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 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
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 PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4]
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 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
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 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]
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 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
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 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
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 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
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 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
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 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
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 PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [9:29]
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 PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:3]
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 PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O
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 PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:31]
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 PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O, VEC = [0:0]
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 PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O, VEC = [0:0]
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 PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN, DIR = O
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 PORT fpga_0_SRAM_CLOCK = sys_clk_s, DIR = O
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 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
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 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
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41 
 
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BEGIN ppc405_virtex4
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 PARAMETER INSTANCE = ppc405_0
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 PARAMETER HW_VER = 2.01.a
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 PARAMETER C_FASTEST_PLB_CLOCK = DPLB0
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 PARAMETER C_APU_CONTROL = 0b0000000000000001
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 PARAMETER C_IDCR_BASEADDR = 0b0100000000
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 PARAMETER C_IDCR_HIGHADDR = 0b0111111111
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 BUS_INTERFACE JTAGPPC = jtagppc_0_0
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 BUS_INTERFACE IPLB0 = plb
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 BUS_INTERFACE DPLB0 = plb
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 BUS_INTERFACE RESETPPC = ppc_reset_bus
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 BUS_INTERFACE MFCB = fcb_v10_0
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 PORT CPMC405CLOCK = proc_clk_s
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 PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
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END
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BEGIN jtagppc_cntlr
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 PARAMETER INSTANCE = jtagppc_0
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 PARAMETER HW_VER = 2.01.a
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 BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
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END
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BEGIN plb_v46
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 PARAMETER INSTANCE = plb
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 PARAMETER C_DCR_INTFCE = 0
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 PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
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 PARAMETER HW_VER = 1.02.a
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 PORT PLB_Clk = sys_clk_s
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 PORT SYS_Rst = sys_bus_reset
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END
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BEGIN xps_uartlite
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 PARAMETER INSTANCE = RS232_Uart
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER C_BAUDRATE = 9600
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 PARAMETER C_DATA_BITS = 8
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 PARAMETER C_ODD_PARITY = 0
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 PARAMETER C_USE_PARITY = 0
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 PARAMETER C_SPLB_CLK_FREQ_HZ = 100000000
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 PARAMETER C_BASEADDR = 0x84000000
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 PARAMETER C_HIGHADDR = 0x8400ffff
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 BUS_INTERFACE SPLB = plb
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 PORT RX = fpga_0_RS232_Uart_RX
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 PORT TX = fpga_0_RS232_Uart_TX
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 PORT Interrupt = RS232_Uart_Interrupt
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END
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BEGIN xps_gpio
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 PARAMETER INSTANCE = LEDs_4Bit
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER C_GPIO_WIDTH = 4
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 PARAMETER C_IS_DUAL = 0
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 PARAMETER C_IS_BIDIR = 1
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 PARAMETER C_ALL_INPUTS = 0
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 PARAMETER C_BASEADDR = 0x81400000
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 PARAMETER C_HIGHADDR = 0x8140ffff
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 BUS_INTERFACE SPLB = plb
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 PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
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END
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BEGIN xps_gpio
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 PARAMETER INSTANCE = LEDs_Positions
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER C_GPIO_WIDTH = 5
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 PARAMETER C_IS_DUAL = 0
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 PARAMETER C_IS_BIDIR = 1
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 PARAMETER C_ALL_INPUTS = 0
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 PARAMETER C_BASEADDR = 0x81420000
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 PARAMETER C_HIGHADDR = 0x8142ffff
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 BUS_INTERFACE SPLB = plb
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 PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO
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END
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BEGIN xps_sysace
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 PARAMETER INSTANCE = SysACE_CompactFlash
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER C_MEM_WIDTH = 16
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 PARAMETER C_BASEADDR = 0x83600000
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 PARAMETER C_HIGHADDR = 0x8360ffff
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 BUS_INTERFACE SPLB = plb
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 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
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 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA & SysACE_CompactFlash_SysACE_MPA
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 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
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 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
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 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
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 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
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 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
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END
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BEGIN xps_mch_emc
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 PARAMETER INSTANCE = SRAM
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 PARAMETER HW_VER = 1.01.a
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 PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 10000
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 PARAMETER C_NUM_BANKS_MEM = 1
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 PARAMETER C_MAX_MEM_WIDTH = 32
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 PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1
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 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
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 PARAMETER C_MEM0_WIDTH = 32
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 PARAMETER C_SYNCH_MEM_0 = 1
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 PARAMETER C_TCEDV_PS_MEM_0 = 0
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 PARAMETER C_TWC_PS_MEM_0 = 0
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 PARAMETER C_TAVDV_PS_MEM_0 = 0
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 PARAMETER C_TWP_PS_MEM_0 = 0
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 PARAMETER C_THZCE_PS_MEM_0 = 0
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 PARAMETER C_TLZWE_PS_MEM_0 = 0
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 PARAMETER C_MEM0_BASEADDR = 0xfff00000
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 PARAMETER C_MEM0_HIGHADDR = 0xffffffff
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 BUS_INTERFACE SPLB = plb
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 PORT Mem_A = fpga_0_SRAM_Mem_A_split
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 PORT Mem_BEN = fpga_0_SRAM_Mem_BEN
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 PORT Mem_WEN = fpga_0_SRAM_Mem_WEN
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 PORT Mem_DQ = fpga_0_SRAM_Mem_DQ
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 PORT Mem_OEN = fpga_0_SRAM_Mem_OEN
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 PORT Mem_CEN = fpga_0_SRAM_Mem_CEN
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 PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN
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 PORT RdClk = sys_clk_s
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END
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BEGIN util_bus_split
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 PARAMETER INSTANCE = SRAM_util_bus_split_0
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER C_SIZE_IN = 32
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 PARAMETER C_LEFT_POS = 9
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 PARAMETER C_SPLIT = 30
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 PORT Sig = fpga_0_SRAM_Mem_A_split
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 PORT Out1 = fpga_0_SRAM_Mem_A
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END
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BEGIN clock_generator
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 PARAMETER INSTANCE = clock_generator_0
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 PARAMETER HW_VER = 2.01.a
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 PARAMETER C_EXT_RESET_HIGH = 1
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 PARAMETER C_CLKIN_FREQ = 100000000
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 PARAMETER C_CLKOUT0_FREQ = 200000000
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 PARAMETER C_CLKOUT0_BUF = TRUE
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 PARAMETER C_CLKOUT0_PHASE = 0
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 PARAMETER C_CLKOUT0_GROUP = NONE
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 PARAMETER C_CLKOUT1_FREQ = 100000000
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 PARAMETER C_CLKOUT1_BUF = TRUE
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 PARAMETER C_CLKOUT1_PHASE = 0
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 PARAMETER C_CLKOUT1_GROUP = NONE
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 PORT CLKOUT0 = proc_clk_s
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 PORT CLKOUT1 = sys_clk_s
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 PORT CLKIN = dcm_clk_s
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 PORT LOCKED = Dcm_all_locked
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 PORT RST = net_gnd
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END
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BEGIN proc_sys_reset
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 PARAMETER INSTANCE = proc_sys_reset_0
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 PARAMETER HW_VER = 2.00.a
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 PARAMETER C_EXT_RESET_HIGH = 0
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 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
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 PORT Slowest_sync_clk = sys_clk_s
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 PORT Dcm_locked = Dcm_all_locked
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 PORT Ext_Reset_In = sys_rst_s
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 PORT Bus_Struct_Reset = sys_bus_reset
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 PORT Peripheral_Reset = sys_periph_reset
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END
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BEGIN xps_intc
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 PARAMETER INSTANCE = xps_intc_0
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 PARAMETER HW_VER = 1.00.a
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 PARAMETER C_BASEADDR = 0x81800000
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 PARAMETER C_HIGHADDR = 0x8180ffff
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 BUS_INTERFACE SPLB = plb
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 PORT Irq = EICC405EXTINPUTIRQ
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 PORT Intr = RS232_Uart_Interrupt
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END
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BEGIN fcb_v10
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 PARAMETER INSTANCE = fcb_v10_0
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 PARAMETER HW_VER = 1.00.a
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 PORT FCB_CLK = proc_clk_s
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 PORT SYS_RST = sys_bus_reset
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END
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BEGIN apu_fpu
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 PARAMETER INSTANCE = apu_fpu_0
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 PARAMETER HW_VER = 3.10.a
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 BUS_INTERFACE SFCB = fcb_v10_0
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 PORT FPU_CLK = sys_clk_s
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END
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