Subversion Repositories openrisc

      PowerPC 405 Virtex-4

      A wrapper to instantiate the PowerPC 405 Processor Block primitive

      PowerPC JTAG Controller

      JTAGPPC wrapper allows the PowerPC to connect to the JTAG chain of the FPGA.

      Processor Local Bus (PLB) 4.6

      'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'

      XPS UART (Lite)

      Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.

        Serial Data In

        Serial Data Out

      XPS General Purpose IO

      General Purpose Input/Output (GPIO) core for the PLBV46 bus.

        GPIO1 Data IO

      XPS General Purpose IO

      General Purpose Input/Output (GPIO) core for the PLBV46 bus.

        GPIO1 Data IO

      XPS System ACE Interface Controller(Compact Flash)

      Interface between the PLBV46 and the Microprocessor Interface (MPU) of the System ACE Compact Flash solution peripheral

        Clock Input

        Address Input

        Data Input/Output

        Active LOW Chip Enable

        Active LOW Output Enable

        Active LOW Write Enable

        Active high Interrupt Output