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586 |
jeremybenn |
############################################################################
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## This system.ucf file is generated by Base System Builder based on the
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## settings in the selected Xilinx Board Definition file. Please add other
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## user constraints to this file based on customer design specifications.
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############################################################################
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Net sys_clk_pin LOC=AE14;
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Net sys_clk_pin IOSTANDARD = LVCMOS33;
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Net sys_rst_pin LOC=D6;
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| 10 |
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Net sys_rst_pin PULLUP;
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## System level constraints
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Net sys_clk_pin TNM_NET = sys_clk_pin;
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TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
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Net sys_rst_pin TIG;
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NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP";
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| 16 |
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NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP";
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NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP";
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TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG;
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Net fpga_0_SRAM_CLOCK LOC=AF7;
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Net fpga_0_SRAM_CLOCK SLEW = FAST;
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Net fpga_0_SRAM_CLOCK IOSTANDARD = LVCMOS33;
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Net fpga_0_SRAM_CLOCK DRIVE = 16;
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## IO Devices constraints
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#### Module RS232_Uart constraints
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Net fpga_0_RS232_Uart_RX_pin LOC=W2;
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Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33;
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| 30 |
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Net fpga_0_RS232_Uart_TX_pin LOC=W1;
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| 31 |
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Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33;
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| 33 |
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#### Module LEDs_4Bit constraints
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP;
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| 38 |
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2;
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| 40 |
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP;
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| 50 |
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW;
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| 51 |
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2;
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| 52 |
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2;
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Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG;
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#### Module LEDs_Positions constraints
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2;
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| 67 |
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG;
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| 68 |
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9;
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| 69 |
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
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| 70 |
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP;
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| 71 |
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2;
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| 73 |
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2;
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| 79 |
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG;
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| 80 |
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP;
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| 83 |
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2;
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| 85 |
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2;
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;
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| 88 |
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP;
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| 89 |
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW;
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| 90 |
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2;
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| 91 |
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Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG;
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| 92 |
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| 93 |
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#### Module SysACE_CompactFlash constraints
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| 95 |
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Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AF11;
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| 96 |
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Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin IOSTANDARD = LVCMOS33;
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| 97 |
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Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 30000 ps;
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| 98 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=Y10;
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| 99 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS33;
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| 100 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AA10;
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| 101 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS33;
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| 102 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AC7;
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| 103 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS33;
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| 104 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=Y7;
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| 105 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS33;
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| 106 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AA9;
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| 107 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS33;
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| 108 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=Y9;
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| 109 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS33;
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| 110 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AB7;
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| 111 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS33;
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| 112 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AC9;
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| 113 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS33;
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| 114 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AB9;
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| 115 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS33;
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| 116 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AE6;
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| 117 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS33;
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| 118 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AD6;
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| 119 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS33;
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| 120 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AF9;
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| 121 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS33;
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| 122 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AE9;
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| 123 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS33;
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| 124 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AD8;
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| 125 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS33;
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| 126 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AC8;
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| 127 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS33;
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| 128 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AF4;
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| 129 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS33;
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| 130 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AE4;
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| 131 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS33;
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| 132 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AD3;
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| 133 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS33;
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| 134 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AC3;
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| 135 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS33;
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| 136 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AF6;
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| 137 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS33;
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| 138 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AF5;
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| 139 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS33;
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| 140 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AA7;
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| 141 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS33;
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| 142 |
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Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AD5;
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| 143 |
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Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS33;
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| 144 |
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Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AA8;
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| 145 |
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Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS33;
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| 146 |
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Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=Y8;
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| 147 |
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Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS33;
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| 148 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AD4;
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| 149 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS33;
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| 150 |
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Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin TIG;
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| 151 |
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| 152 |
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#### Module SRAM constraints
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| 153 |
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| 154 |
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Net fpga_0_SRAM_Mem_A_pin<29> LOC=Y1;
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| 155 |
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Net fpga_0_SRAM_Mem_A_pin<29> IOSTANDARD = LVCMOS33;
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| 156 |
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Net fpga_0_SRAM_Mem_A_pin<29> SLEW = FAST;
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| 157 |
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Net fpga_0_SRAM_Mem_A_pin<29> DRIVE = 8;
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| 158 |
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Net fpga_0_SRAM_Mem_A_pin<28> LOC=Y2;
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| 159 |
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Net fpga_0_SRAM_Mem_A_pin<28> IOSTANDARD = LVCMOS33;
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| 160 |
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Net fpga_0_SRAM_Mem_A_pin<28> SLEW = FAST;
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| 161 |
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Net fpga_0_SRAM_Mem_A_pin<28> DRIVE = 8;
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| 162 |
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Net fpga_0_SRAM_Mem_A_pin<27> LOC=AA1;
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| 163 |
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Net fpga_0_SRAM_Mem_A_pin<27> IOSTANDARD = LVCMOS33;
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| 164 |
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Net fpga_0_SRAM_Mem_A_pin<27> SLEW = FAST;
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| 165 |
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Net fpga_0_SRAM_Mem_A_pin<27> DRIVE = 8;
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| 166 |
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Net fpga_0_SRAM_Mem_A_pin<26> LOC=AB1;
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| 167 |
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Net fpga_0_SRAM_Mem_A_pin<26> IOSTANDARD = LVCMOS33;
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| 168 |
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Net fpga_0_SRAM_Mem_A_pin<26> SLEW = FAST;
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| 169 |
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Net fpga_0_SRAM_Mem_A_pin<26> DRIVE = 8;
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| 170 |
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Net fpga_0_SRAM_Mem_A_pin<25> LOC=AB2;
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| 171 |
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Net fpga_0_SRAM_Mem_A_pin<25> IOSTANDARD = LVCMOS33;
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| 172 |
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Net fpga_0_SRAM_Mem_A_pin<25> SLEW = FAST;
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| 173 |
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Net fpga_0_SRAM_Mem_A_pin<25> DRIVE = 8;
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| 174 |
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Net fpga_0_SRAM_Mem_A_pin<24> LOC=AC1;
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| 175 |
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Net fpga_0_SRAM_Mem_A_pin<24> IOSTANDARD = LVCMOS33;
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| 176 |
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Net fpga_0_SRAM_Mem_A_pin<24> SLEW = FAST;
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| 177 |
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Net fpga_0_SRAM_Mem_A_pin<24> DRIVE = 8;
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| 178 |
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Net fpga_0_SRAM_Mem_A_pin<23> LOC=AC2;
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| 179 |
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Net fpga_0_SRAM_Mem_A_pin<23> IOSTANDARD = LVCMOS33;
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| 180 |
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Net fpga_0_SRAM_Mem_A_pin<23> SLEW = FAST;
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| 181 |
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Net fpga_0_SRAM_Mem_A_pin<23> DRIVE = 8;
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| 182 |
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Net fpga_0_SRAM_Mem_A_pin<22> LOC=AD1;
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| 183 |
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Net fpga_0_SRAM_Mem_A_pin<22> IOSTANDARD = LVCMOS33;
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| 184 |
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Net fpga_0_SRAM_Mem_A_pin<22> SLEW = FAST;
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| 185 |
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Net fpga_0_SRAM_Mem_A_pin<22> DRIVE = 8;
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| 186 |
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Net fpga_0_SRAM_Mem_A_pin<21> LOC=AD2;
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| 187 |
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Net fpga_0_SRAM_Mem_A_pin<21> IOSTANDARD = LVCMOS33;
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| 188 |
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Net fpga_0_SRAM_Mem_A_pin<21> SLEW = FAST;
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| 189 |
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Net fpga_0_SRAM_Mem_A_pin<21> DRIVE = 8;
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| 190 |
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Net fpga_0_SRAM_Mem_A_pin<20> LOC=AE3;
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| 191 |
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Net fpga_0_SRAM_Mem_A_pin<20> IOSTANDARD = LVCMOS33;
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| 192 |
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Net fpga_0_SRAM_Mem_A_pin<20> SLEW = FAST;
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| 193 |
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Net fpga_0_SRAM_Mem_A_pin<20> DRIVE = 8;
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| 194 |
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Net fpga_0_SRAM_Mem_A_pin<19> LOC=AF3;
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| 195 |
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Net fpga_0_SRAM_Mem_A_pin<19> IOSTANDARD = LVCMOS33;
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| 196 |
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Net fpga_0_SRAM_Mem_A_pin<19> SLEW = FAST;
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| 197 |
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Net fpga_0_SRAM_Mem_A_pin<19> DRIVE = 8;
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| 198 |
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Net fpga_0_SRAM_Mem_A_pin<18> LOC=W3;
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| 199 |
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Net fpga_0_SRAM_Mem_A_pin<18> IOSTANDARD = LVCMOS33;
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| 200 |
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Net fpga_0_SRAM_Mem_A_pin<18> SLEW = FAST;
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| 201 |
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Net fpga_0_SRAM_Mem_A_pin<18> DRIVE = 8;
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| 202 |
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Net fpga_0_SRAM_Mem_A_pin<17> LOC=W6;
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| 203 |
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Net fpga_0_SRAM_Mem_A_pin<17> IOSTANDARD = LVCMOS33;
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| 204 |
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Net fpga_0_SRAM_Mem_A_pin<17> SLEW = FAST;
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| 205 |
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Net fpga_0_SRAM_Mem_A_pin<17> DRIVE = 8;
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| 206 |
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Net fpga_0_SRAM_Mem_A_pin<16> LOC=W5;
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| 207 |
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Net fpga_0_SRAM_Mem_A_pin<16> IOSTANDARD = LVCMOS33;
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| 208 |
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Net fpga_0_SRAM_Mem_A_pin<16> SLEW = FAST;
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| 209 |
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Net fpga_0_SRAM_Mem_A_pin<16> DRIVE = 8;
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| 210 |
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Net fpga_0_SRAM_Mem_A_pin<15> LOC=AA3;
|
| 211 |
|
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Net fpga_0_SRAM_Mem_A_pin<15> IOSTANDARD = LVCMOS33;
|
| 212 |
|
|
Net fpga_0_SRAM_Mem_A_pin<15> SLEW = FAST;
|
| 213 |
|
|
Net fpga_0_SRAM_Mem_A_pin<15> DRIVE = 8;
|
| 214 |
|
|
Net fpga_0_SRAM_Mem_A_pin<14> LOC=AA4;
|
| 215 |
|
|
Net fpga_0_SRAM_Mem_A_pin<14> IOSTANDARD = LVCMOS33;
|
| 216 |
|
|
Net fpga_0_SRAM_Mem_A_pin<14> SLEW = FAST;
|
| 217 |
|
|
Net fpga_0_SRAM_Mem_A_pin<14> DRIVE = 8;
|
| 218 |
|
|
Net fpga_0_SRAM_Mem_A_pin<13> LOC=AB3;
|
| 219 |
|
|
Net fpga_0_SRAM_Mem_A_pin<13> IOSTANDARD = LVCMOS33;
|
| 220 |
|
|
Net fpga_0_SRAM_Mem_A_pin<13> SLEW = FAST;
|
| 221 |
|
|
Net fpga_0_SRAM_Mem_A_pin<13> DRIVE = 8;
|
| 222 |
|
|
Net fpga_0_SRAM_Mem_A_pin<12> LOC=AB4;
|
| 223 |
|
|
Net fpga_0_SRAM_Mem_A_pin<12> IOSTANDARD = LVCMOS33;
|
| 224 |
|
|
Net fpga_0_SRAM_Mem_A_pin<12> SLEW = FAST;
|
| 225 |
|
|
Net fpga_0_SRAM_Mem_A_pin<12> DRIVE = 8;
|
| 226 |
|
|
Net fpga_0_SRAM_Mem_A_pin<11> LOC=AC4;
|
| 227 |
|
|
Net fpga_0_SRAM_Mem_A_pin<11> IOSTANDARD = LVCMOS33;
|
| 228 |
|
|
Net fpga_0_SRAM_Mem_A_pin<11> SLEW = FAST;
|
| 229 |
|
|
Net fpga_0_SRAM_Mem_A_pin<11> DRIVE = 8;
|
| 230 |
|
|
Net fpga_0_SRAM_Mem_A_pin<10> LOC=AB5;
|
| 231 |
|
|
Net fpga_0_SRAM_Mem_A_pin<10> IOSTANDARD = LVCMOS33;
|
| 232 |
|
|
Net fpga_0_SRAM_Mem_A_pin<10> SLEW = FAST;
|
| 233 |
|
|
Net fpga_0_SRAM_Mem_A_pin<10> DRIVE = 8;
|
| 234 |
|
|
Net fpga_0_SRAM_Mem_A_pin<9> LOC=AC5;
|
| 235 |
|
|
Net fpga_0_SRAM_Mem_A_pin<9> IOSTANDARD = LVCMOS33;
|
| 236 |
|
|
Net fpga_0_SRAM_Mem_A_pin<9> SLEW = FAST;
|
| 237 |
|
|
Net fpga_0_SRAM_Mem_A_pin<9> DRIVE = 8;
|
| 238 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=Y6;
|
| 239 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<3> IOSTANDARD = LVCMOS33;
|
| 240 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<3> SLEW = FAST;
|
| 241 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<3> DRIVE = 8;
|
| 242 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=Y5;
|
| 243 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<2> IOSTANDARD = LVCMOS33;
|
| 244 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<2> SLEW = FAST;
|
| 245 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<2> DRIVE = 8;
|
| 246 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=Y4;
|
| 247 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<1> IOSTANDARD = LVCMOS33;
|
| 248 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<1> SLEW = FAST;
|
| 249 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<1> DRIVE = 8;
|
| 250 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=Y3;
|
| 251 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<0> IOSTANDARD = LVCMOS33;
|
| 252 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<0> SLEW = FAST;
|
| 253 |
|
|
Net fpga_0_SRAM_Mem_BEN_pin<0> DRIVE = 8;
|
| 254 |
|
|
Net fpga_0_SRAM_Mem_WEN_pin LOC=AB6;
|
| 255 |
|
|
Net fpga_0_SRAM_Mem_WEN_pin IOSTANDARD = LVCMOS33;
|
| 256 |
|
|
Net fpga_0_SRAM_Mem_WEN_pin SLEW = FAST;
|
| 257 |
|
|
Net fpga_0_SRAM_Mem_WEN_pin DRIVE = 8;
|
| 258 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=AD13;
|
| 259 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<31> SLEW = FAST;
|
| 260 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVCMOS33;
|
| 261 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<31> DRIVE = 12;
|
| 262 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=AC13;
|
| 263 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<30> SLEW = FAST;
|
| 264 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVCMOS33;
|
| 265 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<30> DRIVE = 12;
|
| 266 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=AC15;
|
| 267 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<29> SLEW = FAST;
|
| 268 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVCMOS33;
|
| 269 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<29> DRIVE = 12;
|
| 270 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=AC16;
|
| 271 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<28> SLEW = FAST;
|
| 272 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVCMOS33;
|
| 273 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<28> DRIVE = 12;
|
| 274 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=AA11;
|
| 275 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<27> SLEW = FAST;
|
| 276 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVCMOS33;
|
| 277 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<27> DRIVE = 12;
|
| 278 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=AA12;
|
| 279 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<26> SLEW = FAST;
|
| 280 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVCMOS33;
|
| 281 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<26> DRIVE = 12;
|
| 282 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=AD14;
|
| 283 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<25> SLEW = FAST;
|
| 284 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVCMOS33;
|
| 285 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<25> DRIVE = 12;
|
| 286 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=AC14;
|
| 287 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<24> SLEW = FAST;
|
| 288 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVCMOS33;
|
| 289 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<24> DRIVE = 12;
|
| 290 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=AA13;
|
| 291 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<23> SLEW = FAST;
|
| 292 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVCMOS33;
|
| 293 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<23> DRIVE = 12;
|
| 294 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=AB13;
|
| 295 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<22> SLEW = FAST;
|
| 296 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVCMOS33;
|
| 297 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<22> DRIVE = 12;
|
| 298 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=AA15;
|
| 299 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<21> SLEW = FAST;
|
| 300 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVCMOS33;
|
| 301 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<21> DRIVE = 12;
|
| 302 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=AA16;
|
| 303 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<20> SLEW = FAST;
|
| 304 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVCMOS33;
|
| 305 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<20> DRIVE = 12;
|
| 306 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=AC11;
|
| 307 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<19> SLEW = FAST;
|
| 308 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVCMOS33;
|
| 309 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<19> DRIVE = 12;
|
| 310 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=AC12;
|
| 311 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<18> SLEW = FAST;
|
| 312 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVCMOS33;
|
| 313 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<18> DRIVE = 12;
|
| 314 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=AB14;
|
| 315 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<17> SLEW = FAST;
|
| 316 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVCMOS33;
|
| 317 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<17> DRIVE = 12;
|
| 318 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=AA14;
|
| 319 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<16> SLEW = FAST;
|
| 320 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVCMOS33;
|
| 321 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<16> DRIVE = 12;
|
| 322 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=D12;
|
| 323 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<15> SLEW = FAST;
|
| 324 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33;
|
| 325 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<15> DRIVE = 12;
|
| 326 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=E13;
|
| 327 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<14> SLEW = FAST;
|
| 328 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33;
|
| 329 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<14> DRIVE = 12;
|
| 330 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=C16;
|
| 331 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<13> SLEW = FAST;
|
| 332 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33;
|
| 333 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<13> DRIVE = 12;
|
| 334 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=D16;
|
| 335 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<12> SLEW = FAST;
|
| 336 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33;
|
| 337 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<12> DRIVE = 12;
|
| 338 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=D11;
|
| 339 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<11> SLEW = FAST;
|
| 340 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33;
|
| 341 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<11> DRIVE = 12;
|
| 342 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=C11;
|
| 343 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<10> SLEW = FAST;
|
| 344 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33;
|
| 345 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<10> DRIVE = 12;
|
| 346 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=E14;
|
| 347 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<9> SLEW = FAST;
|
| 348 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33;
|
| 349 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<9> DRIVE = 12;
|
| 350 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=D15;
|
| 351 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<8> SLEW = FAST;
|
| 352 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33;
|
| 353 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<8> DRIVE = 12;
|
| 354 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=D13;
|
| 355 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<7> SLEW = FAST;
|
| 356 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33;
|
| 357 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<7> DRIVE = 12;
|
| 358 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=D14;
|
| 359 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<6> SLEW = FAST;
|
| 360 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33;
|
| 361 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<6> DRIVE = 12;
|
| 362 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=F15;
|
| 363 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<5> SLEW = FAST;
|
| 364 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33;
|
| 365 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<5> DRIVE = 12;
|
| 366 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=F16;
|
| 367 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<4> SLEW = FAST;
|
| 368 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33;
|
| 369 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<4> DRIVE = 12;
|
| 370 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=F11;
|
| 371 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<3> SLEW = FAST;
|
| 372 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33;
|
| 373 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<3> DRIVE = 12;
|
| 374 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=F12;
|
| 375 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<2> SLEW = FAST;
|
| 376 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33;
|
| 377 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<2> DRIVE = 12;
|
| 378 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=F13;
|
| 379 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<1> SLEW = FAST;
|
| 380 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33;
|
| 381 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<1> DRIVE = 12;
|
| 382 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=F14;
|
| 383 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<0> SLEW = FAST;
|
| 384 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33;
|
| 385 |
|
|
Net fpga_0_SRAM_Mem_DQ_pin<0> DRIVE = 12;
|
| 386 |
|
|
Net fpga_0_SRAM_Mem_OEN_pin<0> LOC=AC6;
|
| 387 |
|
|
Net fpga_0_SRAM_Mem_OEN_pin<0> IOSTANDARD = LVCMOS33;
|
| 388 |
|
|
Net fpga_0_SRAM_Mem_OEN_pin<0> SLEW = FAST;
|
| 389 |
|
|
Net fpga_0_SRAM_Mem_OEN_pin<0> DRIVE = 8;
|
| 390 |
|
|
Net fpga_0_SRAM_Mem_CEN_pin<0> LOC=V7;
|
| 391 |
|
|
Net fpga_0_SRAM_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33;
|
| 392 |
|
|
Net fpga_0_SRAM_Mem_CEN_pin<0> SLEW = FAST;
|
| 393 |
|
|
Net fpga_0_SRAM_Mem_CEN_pin<0> DRIVE = 8;
|
| 394 |
|
|
Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=W4;
|
| 395 |
|
|
Net fpga_0_SRAM_Mem_ADV_LDN_pin IOSTANDARD = LVCMOS33;
|
| 396 |
|
|
Net fpga_0_SRAM_Mem_ADV_LDN_pin SLEW = FAST;
|
| 397 |
|
|
Net fpga_0_SRAM_Mem_ADV_LDN_pin DRIVE = 8;
|
| 398 |
|
|
|
