OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC405_Xilinx_Virtex4_GCC/] [system.make] - Blame information for rev 612

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 586 jeremybenn
#################################################################
2
# Makefile generated by Xilinx Platform Studio
3
# Project:C:\E\temp\rc\3\V5.0.2\FreeRTOS\Demo\PPC405_Xilinx_Virtex4_GCC\system.xmp
4
#
5
# WARNING : This file will be re-generated every time a command
6
# to run a make target is invoked. So, any changes made to this
7
# file manually, will be lost when make is invoked next.
8
#################################################################
9
 
10
# Name of the Microprocessor system
11
# The hardware specification of the system is in file :
12
# C:\E\temp\rc\3\V5.0.2\FreeRTOS\Demo\PPC405_Xilinx_Virtex4_GCC\system.mhs
13
# The software specification of the system is in file :
14
# C:\E\temp\rc\3\V5.0.2\FreeRTOS\Demo\PPC405_Xilinx_Virtex4_GCC\system.mss
15
 
16
include system_incl.make
17
 
18
#################################################################
19
# PHONY TARGETS
20
#################################################################
21
.PHONY: dummy
22
.PHONY: netlistclean
23
.PHONY: bitsclean
24
.PHONY: simclean
25
.PHONY: vpclean
26
 
27
#################################################################
28
# EXTERNAL TARGETS
29
#################################################################
30
all:
31
        @echo "Makefile to build a Microprocessor system :"
32
        @echo "Run make with any of the following targets"
33
        @echo " "
34
        @echo "  netlist  : Generates the netlist for the given MHS "
35
        @echo "  bits     : Runs Implementation tools to generate the bitstream"
36
        @echo " "
37
        @echo "  libs     : Configures the sw libraries for this system"
38
        @echo "  program  : Compiles the program sources for all the processor instances"
39
        @echo " "
40
        @echo "  init_bram: Initializes bitstream with BRAM data"
41
        @echo "  ace      : Generate ace file from bitstream and elf"
42
        @echo "  download : Downloads the bitstream onto the board"
43
        @echo " "
44
        @echo "  sim      : Generates HDL simulation models and runs simulator for chosen simulation mode"
45
        @echo "  simmodel : Generates HDL simulation models for chosen simulation mode"
46
        @echo "  behavioral_model : Generates behavioral HDL models with BRAM initialization"
47
        @echo "  structural_model : Generates structural simulation HDL models with BRAM initialization"
48
        @echo "  timing   : Generates timing simulation HDL models with BRAM initialization"
49
        @echo "  vp       : Generates virtual platform model"
50
        @echo " "
51
        @echo "  netlistclean: Deletes netlist"
52
        @echo "  bitsclean: Deletes bit, ncd, bmm files"
53
        @echo "  hwclean  : Deletes implementation dir"
54
        @echo "  libsclean: Deletes sw libraries"
55
        @echo "  programclean: Deletes compiled ELF files"
56
        @echo "  swclean  : Deletes sw libraries and ELF files"
57
        @echo "  simclean : Deletes simulation dir"
58
        @echo "  vpclean  : Deletes virtualplatform dir"
59
        @echo "  clean    : Deletes all generated files/directories"
60
        @echo " "
61
        @echo "  make  : (Default)"
62
        @echo "      Creates a Microprocessor system using default initializations"
63
        @echo "      specified for each processor in MSS file"
64
 
65
 
66
bits: $(SYSTEM_BIT)
67
 
68
ace: $(SYSTEM_ACE)
69
 
70
netlist: $(POSTSYN_NETLIST)
71
 
72
libs: $(LIBRARIES)
73
 
74
program: $(ALL_USER_ELF_FILES)
75
 
76
download: $(DOWNLOAD_BIT) dummy
77
        @echo "*********************************************"
78
        @echo "Downloading Bitstream onto the target board"
79
        @echo "*********************************************"
80
        impact -batch etc/download.cmd
81
 
82
init_bram: $(DOWNLOAD_BIT)
83
 
84
sim: $(DEFAULT_SIM_SCRIPT)
85
        cd simulation/behavioral; \
86
        $(SIM_CMD)  &
87
 
88
simmodel: $(DEFAULT_SIM_SCRIPT)
89
 
90
behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)
91
 
92
structural_model: $(STRUCTURAL_SIM_SCRIPT)
93
 
94
vp: $(VPEXEC)
95
 
96
clean: hwclean libsclean programclean simclean vpclean
97
        rm -f _impact.cmd
98
        rm -f *.log
99
 
100
hwclean: netlistclean bitsclean
101
        rm -rf implementation synthesis xst hdl
102
        rm -rf xst.srp $(SYSTEM).srp
103
 
104
netlistclean:
105
        rm -f $(POSTSYN_NETLIST)
106
        rm -f platgen.log
107
        rm -f $(BMM_FILE)
108
 
109
bitsclean:
110
        rm -f $(SYSTEM_BIT)
111
        rm -f implementation/$(SYSTEM).ncd
112
        rm -f implementation/$(SYSTEM)_bd.bmm
113
        rm -f implementation/$(SYSTEM)_map.ncd
114
 
115
simclean:
116
        rm -rf simulation/behavioral
117
        rm -f simgen.log
118
 
119
swclean: libsclean programclean
120
        @echo ""
121
 
122
libsclean: $(LIBSCLEAN_TARGETS)
123
        rm -f libgen.log
124
 
125
programclean: $(PROGRAMCLEAN_TARGETS)
126
 
127
vpclean:
128
        rm -rf virtualplatform
129
        rm -f vpgen.log
130
 
131
#################################################################
132
# SOFTWARE PLATFORM FLOW
133
#################################################################
134
 
135
 
136
$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt
137
        @echo "*********************************************"
138
        @echo "Creating software libraries..."
139
        @echo "*********************************************"
140
        libgen $(LIBGEN_OPTIONS) $(MSSFILE)
141
 
142
 
143
ppc405_0_libsclean:
144
        rm -rf ppc405_0/
145
 
146
#################################################################
147
# SOFTWARE APPLICATION RTOSDEMO
148
#################################################################
149
 
150
RTOSDemo_program: $(RTOSDEMO_OUTPUT)
151
 
152
$(RTOSDEMO_OUTPUT) : $(RTOSDEMO_SOURCES) $(RTOSDEMO_HEADERS) $(RTOSDEMO_LINKER_SCRIPT) \
153
                    $(LIBRARIES) __xps/rtosdemo_compiler.opt
154
        @mkdir -p $(RTOSDEMO_OUTPUT_DIR)
155
        $(RTOSDEMO_CC) $(RTOSDEMO_CC_OPT) $(RTOSDEMO_SOURCES) -o $(RTOSDEMO_OUTPUT) \
156
        $(RTOSDEMO_OTHER_CC_FLAGS) $(RTOSDEMO_INCLUDES) $(RTOSDEMO_LIBPATH) \
157
        $(RTOSDEMO_CFLAGS) $(RTOSDEMO_LFLAGS)
158
        $(RTOSDEMO_CC_SIZE) $(RTOSDEMO_OUTPUT)
159
        @echo ""
160
 
161
RTOSDemo_programclean:
162
        rm -f $(RTOSDEMO_OUTPUT)
163
 
164
#################################################################
165
# BOOTLOOP ELF FILES
166
#################################################################
167
 
168
 
169
 
170
$(PPC405_0_BOOTLOOP): $(PPC405_BOOTLOOP)
171
        @mkdir -p $(BOOTLOOP_DIR)
172
        cp -f $(PPC405_BOOTLOOP) $(PPC405_0_BOOTLOOP)
173
 
174
#################################################################
175
# HARDWARE IMPLEMENTATION FLOW
176
#################################################################
177
 
178
 
179
$(BMM_FILE) \
180
$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
181
                      $(CORE_STATE_DEVELOPMENT_FILES)
182
        @echo "****************************************************"
183
        @echo "Creating system netlist for hardware specification.."
184
        @echo "****************************************************"
185
        platgen $(PLATGEN_OPTIONS) $(MHSFILE)
186
 
187
$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)
188
        @echo "Running synthesis..."
189
        bash -c "cd synthesis; ./synthesis.sh"
190
 
191
__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY)
192
        @echo "*********************************************"
193
        @echo "Running Xilinx Implementation tools.."
194
        @echo "*********************************************"
195
        @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf
196
        xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/manage_fastruntime_opt.pl $(MANAGE_FASTRT_OPTIONS)
197
        xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc
198
        touch __xps/$(SYSTEM)_routed
199
 
200
$(SYSTEM_BIT): __xps/$(SYSTEM)_routed
201
        xilperl $(NON_CYG_XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par
202
        @echo "*********************************************"
203
        @echo "Running Bitgen.."
204
        @echo "*********************************************"
205
        @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut
206
        cd implementation; bitgen -w -f bitgen.ut $(SYSTEM)
207
 
208
$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt
209
        # @cp -f implementation/$(SYSTEM)_bd.bmm .
210
        @echo "*********************************************"
211
        @echo "Initializing BRAM contents of the bitstream"
212
        @echo "*********************************************"
213
        bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \
214
        -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)
215
        @rm -f $(SYSTEM)_bd.bmm
216
 
217
$(SYSTEM_ACE): $(DOWNLOAD_BIT) $(RTOSDEMO_OUTPUT)
218
        @echo "*********************************************"
219
        @echo "Creating system ace file"
220
        @echo "*********************************************"
221
        xmd -tcl genace.tcl -jprog -hw $(DOWNLOAD_BIT) -elf $(RTOSDEMO_OUTPUT)  -target ppc_hw  -ace $(SYSTEM_ACE)
222
 
223
#################################################################
224
# SIMULATION FLOW
225
#################################################################
226
 
227
 
228
################## BEHAVIORAL SIMULATION ##################
229
 
230
$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \
231
                          $(BRAMINIT_ELF_FILES)
232
        @echo "*********************************************"
233
        @echo "Creating behavioral simulation models..."
234
        @echo "*********************************************"
235
        simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)
236
 
237
################## STRUCTURAL SIMULATION ##################
238
 
239
$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \
240
                          $(BRAMINIT_ELF_FILES)
241
        @echo "*********************************************"
242
        @echo "Creating structural simulation models..."
243
        @echo "*********************************************"
244
        simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)
245
 
246
 
247
################## TIMING SIMULATION ##################
248
 
249
$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \
250
                      $(BRAMINIT_ELF_FILES)
251
        @echo "*********************************************"
252
        @echo "Creating timing simulation models..."
253
        @echo "*********************************************"
254
        simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)
255
 
256
#################################################################
257
# VIRTUAL PLATFORM FLOW
258
#################################################################
259
 
260
 
261
$(VPEXEC): $(MHSFILE) __xps/vpgen.opt
262
        @echo "****************************************************"
263
        @echo "Creating virtual platform for hardware specification.."
264
        @echo "****************************************************"
265
        vpgen $(VPGEN_OPTIONS) $(MHSFILE)
266
 
267
dummy:
268
        @echo ""
269
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.