OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC405_Xilinx_Virtex4_GCC/] [system.mhs] - Blame information for rev 649

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 586 jeremybenn 
 
2 
# ##############################################################################
3 
# Created by Base System Builder Wizard for Xilinx EDK 10.1.01 Build EDK_K_SP1.3
4 
# Fri May 09 11:01:33 2008
5 
# Target Board:  Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
6 
# Family:    virtex4
7 
# Device:    xc4vfx12
8 
# Package:   ff668
9 
# Speed Grade:  -10
10 
# Processor: ppc405_0
11 
# Processor clock frequency: 200.00 MHz
12 
# Bus clock frequency: 100.00 MHz
13 
# Total Off Chip Memory :   1 MB
14 
# - SRAM =   1 MB
15 
# ##############################################################################
16 
 PARAMETER VERSION = 2.1.0
17 
 
18 
 
19 
 PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I
20 
 PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O
21 
 PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
22 
 PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4]
23 
 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
24 
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]
25 
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
26 
 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
27 
 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
28 
 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
29 
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
30 
 PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [9:29]
31 
 PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:3]
32 
 PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O
33 
 PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:31]
34 
 PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O, VEC = [0:0]
35 
 PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O, VEC = [0:0]
36 
 PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN, DIR = O
37 
 PORT fpga_0_SRAM_CLOCK = sys_clk_s, DIR = O
38 
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
39 
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
40 
 
41 
 
42 
BEGIN ppc405_virtex4
43 
 PARAMETER INSTANCE = ppc405_0
44 
 PARAMETER HW_VER = 2.01.a
45 
 PARAMETER C_FASTEST_PLB_CLOCK = DPLB0
46 
 PARAMETER C_APU_CONTROL = 0b0000000000000001
47 
 PARAMETER C_IDCR_BASEADDR = 0b0100000000
48 
 PARAMETER C_IDCR_HIGHADDR = 0b0111111111
49 
 BUS_INTERFACE JTAGPPC = jtagppc_0_0
50 
 BUS_INTERFACE IPLB0 = plb
51 
 BUS_INTERFACE DPLB0 = plb
52 
 BUS_INTERFACE RESETPPC = ppc_reset_bus
53 
 PORT CPMC405CLOCK = proc_clk_s
54 
 PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
55 
END
56 
 
57 
BEGIN jtagppc_cntlr
58 
 PARAMETER INSTANCE = jtagppc_0
59 
 PARAMETER HW_VER = 2.01.a
60 
 BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
61 
END
62 
 
63 
BEGIN plb_v46
64 
 PARAMETER INSTANCE = plb
65 
 PARAMETER C_DCR_INTFCE = 0
66 
 PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
67 
 PARAMETER HW_VER = 1.02.a
68 
 PORT PLB_Clk = sys_clk_s
69 
 PORT SYS_Rst = sys_bus_reset
70 
END
71 
 
72 
BEGIN xps_uartlite
73 
 PARAMETER INSTANCE = RS232_Uart
74 
 PARAMETER HW_VER = 1.00.a
75 
 PARAMETER C_BAUDRATE = 9600
76 
 PARAMETER C_DATA_BITS = 8
77 
 PARAMETER C_ODD_PARITY = 0
78 
 PARAMETER C_USE_PARITY = 0
79 
 PARAMETER C_SPLB_CLK_FREQ_HZ = 100000000
80 
 PARAMETER C_BASEADDR = 0x84000000
81 
 PARAMETER C_HIGHADDR = 0x8400ffff
82 
 BUS_INTERFACE SPLB = plb
83 
 PORT RX = fpga_0_RS232_Uart_RX
84 
 PORT TX = fpga_0_RS232_Uart_TX
85 
 PORT Interrupt = RS232_Uart_Interrupt
86 
END
87 
 
88 
BEGIN xps_gpio
89 
 PARAMETER INSTANCE = LEDs_4Bit
90 
 PARAMETER HW_VER = 1.00.a
91 
 PARAMETER C_GPIO_WIDTH = 4
92 
 PARAMETER C_IS_DUAL = 0
93 
 PARAMETER C_IS_BIDIR = 1
94 
 PARAMETER C_ALL_INPUTS = 0
95 
 PARAMETER C_BASEADDR = 0x81400000
96 
 PARAMETER C_HIGHADDR = 0x8140ffff
97 
 BUS_INTERFACE SPLB = plb
98 
 PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
99 
END
100 
 
101 
BEGIN xps_gpio
102 
 PARAMETER INSTANCE = LEDs_Positions
103 
 PARAMETER HW_VER = 1.00.a
104 
 PARAMETER C_GPIO_WIDTH = 5
105 
 PARAMETER C_IS_DUAL = 0
106 
 PARAMETER C_IS_BIDIR = 1
107 
 PARAMETER C_ALL_INPUTS = 0
108 
 PARAMETER C_BASEADDR = 0x81420000
109 
 PARAMETER C_HIGHADDR = 0x8142ffff
110 
 BUS_INTERFACE SPLB = plb
111 
 PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO
112 
END
113 
 
114 
BEGIN xps_sysace
115 
 PARAMETER INSTANCE = SysACE_CompactFlash
116 
 PARAMETER HW_VER = 1.00.a
117 
 PARAMETER C_MEM_WIDTH = 16
118 
 PARAMETER C_BASEADDR = 0x83600000
119 
 PARAMETER C_HIGHADDR = 0x8360ffff
120 
 BUS_INTERFACE SPLB = plb
121 
 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
122 
 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA & SysACE_CompactFlash_SysACE_MPA
123 
 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
124 
 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
125 
 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
126 
 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
127 
 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
128 
END
129 
 
130 
BEGIN xps_mch_emc
131 
 PARAMETER INSTANCE = SRAM
132 
 PARAMETER HW_VER = 1.01.a
133 
 PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 10000
134 
 PARAMETER C_NUM_BANKS_MEM = 1
135 
 PARAMETER C_MAX_MEM_WIDTH = 32
136 
 PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1
137 
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
138 
 PARAMETER C_MEM0_WIDTH = 32
139 
 PARAMETER C_SYNCH_MEM_0 = 1
140 
 PARAMETER C_TCEDV_PS_MEM_0 = 0
141 
 PARAMETER C_TWC_PS_MEM_0 = 0
142 
 PARAMETER C_TAVDV_PS_MEM_0 = 0
143 
 PARAMETER C_TWP_PS_MEM_0 = 0
144 
 PARAMETER C_THZCE_PS_MEM_0 = 0
145 
 PARAMETER C_TLZWE_PS_MEM_0 = 0
146 
 PARAMETER C_MEM0_BASEADDR = 0xfff00000
147 
 PARAMETER C_MEM0_HIGHADDR = 0xffffffff
148 
 BUS_INTERFACE SPLB = plb
149 
 PORT Mem_A = fpga_0_SRAM_Mem_A_split
150 
 PORT Mem_BEN = fpga_0_SRAM_Mem_BEN
151 
 PORT Mem_WEN = fpga_0_SRAM_Mem_WEN
152 
 PORT Mem_DQ = fpga_0_SRAM_Mem_DQ
153 
 PORT Mem_OEN = fpga_0_SRAM_Mem_OEN
154 
 PORT Mem_CEN = fpga_0_SRAM_Mem_CEN
155 
 PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN
156 
 PORT RdClk = sys_clk_s
157 
END
158 
 
159 
BEGIN util_bus_split
160 
 PARAMETER INSTANCE = SRAM_util_bus_split_0
161 
 PARAMETER HW_VER = 1.00.a
162 
 PARAMETER C_SIZE_IN = 32
163 
 PARAMETER C_LEFT_POS = 9
164 
 PARAMETER C_SPLIT = 30
165 
 PORT Sig = fpga_0_SRAM_Mem_A_split
166 
 PORT Out1 = fpga_0_SRAM_Mem_A
167 
END
168 
 
169 
BEGIN clock_generator
170 
 PARAMETER INSTANCE = clock_generator_0
171 
 PARAMETER HW_VER = 2.01.a
172 
 PARAMETER C_EXT_RESET_HIGH = 1
173 
 PARAMETER C_CLKIN_FREQ = 100000000
174 
 PARAMETER C_CLKOUT0_FREQ = 200000000
175 
 PARAMETER C_CLKOUT0_BUF = TRUE
176 
 PARAMETER C_CLKOUT0_PHASE = 0
177 
 PARAMETER C_CLKOUT0_GROUP = NONE
178 
 PARAMETER C_CLKOUT1_FREQ = 100000000
179 
 PARAMETER C_CLKOUT1_BUF = TRUE
180 
 PARAMETER C_CLKOUT1_PHASE = 0
181 
 PARAMETER C_CLKOUT1_GROUP = NONE
182 
 PORT CLKOUT0 = proc_clk_s
183 
 PORT CLKOUT1 = sys_clk_s
184 
 PORT CLKIN = dcm_clk_s
185 
 PORT LOCKED = Dcm_all_locked
186 
 PORT RST = net_gnd
187 
END
188 
 
189 
BEGIN proc_sys_reset
190 
 PARAMETER INSTANCE = proc_sys_reset_0
191 
 PARAMETER HW_VER = 2.00.a
192 
 PARAMETER C_EXT_RESET_HIGH = 0
193 
 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
194 
 PORT Slowest_sync_clk = sys_clk_s
195 
 PORT Dcm_locked = Dcm_all_locked
196 
 PORT Ext_Reset_In = sys_rst_s
197 
 PORT Bus_Struct_Reset = sys_bus_reset
198 
 PORT Peripheral_Reset = sys_periph_reset
199 
END
200 
 
201 
BEGIN xps_intc
202 
 PARAMETER INSTANCE = xps_intc_0
203 
 PARAMETER HW_VER = 1.00.a
204 
 PARAMETER C_BASEADDR = 0x81800000
205 
 PARAMETER C_HIGHADDR = 0x8180ffff
206 
 BUS_INTERFACE SPLB = plb
207 
 PORT Irq = EICC405EXTINPUTIRQ
208 
 PORT Intr = RS232_Uart_Interrupt
209 
END
210 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.