URL https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC440_DP_FPU_Xilinx_Virtex5_GCC/] [system.log] - Blame information for rev 590

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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
 
Generating Block Diagram to Buffer
 
Generated Block Diagram SVG
 
The project file (XMP) has changed on disk.
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
 
At Local date and time: Tue Jun 30 18:36:00 2009
 make -f system.make netlistclean started...
 
rm -f implementation/system.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
 
 
Done!
 
At Local date and time: Tue Jun 30 18:36:05 2009
 make -f system.make bitsclean started...
 
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f __xps/system_routed
 
 
Done!
 
At Local date and time: Tue Jun 30 18:36:10 2009
 make -f system.make hwclean started...
 
rm -f implementation/system.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f __xps/system_routed
rm -rf implementation synthesis xst hdl
rm -rf xst.srp system.srp
rm -f __xps/ise/_xmsgs/bitinit.xmsgs
 
 
Done!
 
At Local date and time: Tue Jun 30 18:36:16 2009
 make -f system.make libsclean started...
 
rm -rf ppc440_0/
rm -f libgen.log
rm -f __xps/ise/_xmsgs/libgen.xmsgs
 
 
Done!
 
At Local date and time: Tue Jun 30 18:36:20 2009
 make -f system.make programclean started...
 
rm -f RTOSDemo/executable.elf
 
 
Done!
 
At Local date and time: Tue Jun 30 18:36:25 2009
 make -f system.make swclean started...
 
rm -rf ppc440_0/
rm -f libgen.log
rm -f __xps/ise/_xmsgs/libgen.xmsgs
rm -f RTOSDemo/executable.elf
 
 
Done!
 
Writing filter settings....
 
Done writing filter settings to:
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
 
Done writing Tab View settings to:
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
 
Generating Block Diagram to Buffer
 
Generated Block Diagram SVG
 
At Local date and time: Tue Jun 30 22:00:27 2009
 make -f system.make bits started...
 
****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc5vfx70tff1136-1 -lang vhdl   -msg __xps/ise/xmsgprops.lst system.mhs
 
 
 (nt)
 

 
Command Line: platgen -p xc5vfx70tff1136-1 -lang vhdl -msg
 
 
 
 
 

 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
 
 
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
 
   hs line 253 - deprecated core for architecture 'virtex5fx'!
 
 
 

 

 

 
Address Map for Processor ppc440_0
 
  (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC
 
  (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0
 
  (0x81440000-0x8144ffff) LEDs_8Bit     plb_v46_0
 
  (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0
 
  (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0
 
  (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0
 
  (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0
 
  (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
 
 
 
Computing clock values...
 
 
 
   through the clock generator IP.
 
 
 
   performed for IPs connected to that clock port, unless they are connected
 

 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_SLAVES value to 12
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   value to 0x2000
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   C_PORT_DWIDTH value to 64
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   value to 8
 
 
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
 
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
 
 
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
 
   C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_MPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_MPLB_SMALLEST_SLAVE value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_SLAVES value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
 
   PARAMETER C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
 
   value to 128
 
Checking platform address map ...
 
Checking platform configuration ...
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m
 
   performance.
 
   The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs
 
   operation.
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
 
line 290 - 1 master(s) : 1 slave(s)
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 

 
WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
 
   hs line 461 - floating connection!
 
Performing Clock DRCs...
 
Performing Reset DRCs...
 
Overriding system level properties...
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
 
   C_PPC440MC_ADDR_BASE value to 0x00000000
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
 
   C_PPC440MC_ADDR_HIGH value to 0x0fffffff
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_0
 
   C_NUM_PPC_USED value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
 
   value to 0b00000000000000000000000000000001
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
 
   value to 0b00000000000000000000000000000001
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
 
   value to 0b00000000000000000000000000000000
 
Running system level update procedures...
 
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
 
Running system level DRCs...
 
Performing System level DRCs on properties...
 
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
 
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
 
implementation/pcie_bridge_wrapper/pcie_bridge_wrapper.ucf.
 

 

 
implementation/ethernet_mac_wrapper/ethernet_mac_wrapper.ucf.
 

 

 
implementation/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ucf.
 

 

 
Modify defaults ...
 
Creating stub ...
 
Processing licensed instances ...
 

 

 
IPNAME:plbv46_pcie INSTANCE:pcie_bridge -
 
line 253 - Copying (BBD-specified) netlist files.
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
IPNAME:apu_fpu_virtex5 INSTANCE:ppc440_0_apu_fpu_virtex5 -
 
line 401 - Copying (BBD-specified) netlist files.
 
Managing cache ...
 
Elaborating instances ...
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 

 

 
Completion time: 0.00 seconds
 
Constructing platform-level connectivity ...
 

 

 

 

 

 
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
 
INSTANCE:ppc440_0 -
 
line 78 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:xps_bram_if_cntlr_1 -
 
line 118 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:rs232_uart_1 -
 
line 138 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:leds_positions -
 
line 168 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:dip_switches_8bit -
 
line 196 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:sram -
 
line 223 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:ppc440_0_splb0 -
 
line 290 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:ddr2_sdram -
 
line 317 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:ppc440_0_fcb_v20 -
 
line 394 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:clock_generator_0 -
 
line 407 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:proc_sys_reset_0 -
 
line 452 - Running XST synthesis
 
 
 

 
 
 
line 78 - Running NGCBUILD
 
 with local file
 

 
xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..
 

 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa
 

 

 
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
NGCBUILD Design Results Summary:
 
  Number of warnings:   0
 
Writing NGC file "../ppc440_0_wrapper.ngc" ...
 
Total CPU time to NGCBUILD completion:   6 sec
 
Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...
 
NGCBUILD done.
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
 
 

 
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
 
../rs232_uart_1_wrapper.ngc
 
Reading NGO file
 
 
 
Partition Implementation Status
 
 
 

 
 
 
  Number of errors:     0
 

 
Total REAL time to NGCBUILD completion:  2 sec
 

 

 
IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -
 
line 253 - Running NGCBUILD
 
 with local file
 

 
xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..
 

 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa
 
Executing edif2ngd -noa
 
tion\pcie_bridge_wrapper_fifo_generator_v4_3.edn"
 
Release 11.2 - edif2ngd L.46 (nt)
 
INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)
 
PMSPEC -- Overriding Xilinx file 
 
Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...
 
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa
 
Loading design module
 
Loading design module
 
tion\pcie_bridge_wrapper/dpram_70_512.ngc"...
 
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa
 

 

 
 
 
  No Partitions were found in this design.
 
 
 
NGCBUILD Design Results Summary:
 
 
 
Writing NGC file "../pcie_bridge_wrapper.ngc" ...
 
 
 
Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...
 
 
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
 
 

 
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
 
ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc
 
 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa
 
 
 
 
 
 
 
 
 
Writing module to "ethernetlite_v1_01_b_dmem_v2.ngo"...
 
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa
 
 
Applying constraints in "ethernet_mac_wrapper.ucf" to the design...
 
 
 
 
 
 
 
 
 
  Number of errors:     0
 

 
 
Total CPU time to NGCBUILD completion:   6 sec
 
 
 
 
 
 
 
 
 
 
 
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
 
 
 
Reading NGO file
 
 
 
Applying constraints in "ddr2_sdram_wrapper.ucf" to the design...
 
Partition Implementation Status
 
 
 

 
 
 
  Number of errors:     0
 

 
Total REAL time to NGCBUILD completion:  7 sec
 

 

 
IPNAME:ppc440_0_apu_fpu_virtex5_wrapper INSTANCE:ppc440_0_apu_fpu_virtex5 -
 
line 401 - Running NGCBUILD
 
 with local file
 

 
xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_apu_fpu_virtex5_wrapper.ucf -sd
 
 
 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa
 
 
 
tion\ppc440_0_apu_fpu_virtex5_wrapper/apu_fpu_dp_lo.ngc"...
 
Applying constraints in "ppc440_0_apu_fpu_virtex5_wrapper.ucf" to the design...
 
Partition Implementation Status
 

 
 
 

 
 
 

 
Total REAL time to NGCBUILD completion:  7 sec
 
 
 

 
IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 -
 
 
 
 with local file
 
 
 
xc5vfx70tff1136-1 -intstyle silent -sd .. xps_intc_0_wrapper.ngc
 
 
 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa
 
 
 
-------------------------------
 
 
 
-------------------------------
 
NGCBUILD Design Results Summary:
 
  Number of warnings:   0
 
Writing NGC file "../xps_intc_0_wrapper.ngc" ...
 
Total CPU time to NGCBUILD completion:   2 sec
 
Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...
 
NGCBUILD done.
 
Rebuilding cache ...
 
Total run time: 1120.00 seconds
 
bash -c "cd synthesis; ./synthesis.sh"
 
Running XST synthesis ...
 
Release 11.2 - ngcbuild L.46 (nt)
 
Overriding Xilinx file  with local file
 

 
./system.ngc ../implementation/system.ngc -sd ../implementation -i -ise
 

 
"c:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/synthesis/
 
Loading design module "../implementation/ppc440_0_wrapper.ngc"...
 
Loading design module "../implementation/xps_bram_if_cntlr_1_wrapper.ngc"...
 
"../implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc"...
 
Loading design module "../implementation/leds_8bit_wrapper.ngc"...
 
Loading design module "../implementation/push_buttons_5bit_wrapper.ngc"...
 
Loading design module "../implementation/iic_eeprom_wrapper.ngc"...
 
Loading design module "../implementation/pcie_bridge_wrapper.ngc"...
 
Loading design module "../implementation/ethernet_mac_wrapper.ngc"...
 
Loading design module "../implementation/sysace_compactflash_wrapper.ngc"...
 
Loading design module
 
Loading design module "../implementation/clock_generator_0_wrapper.ngc"...
 
Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...
 

 
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
NGCBUILD Design Results Summary:
 
  Number of warnings:   0
 
Writing NGC file "../implementation/system.ngc" ...
 
Total CPU time to NGCBUILD completion:   11 sec
 
Writing NGCBUILD log file "../implementation/system.blc"...
 
NGCBUILD done.
 
Running Xilinx Implementation tools..
 
xflow -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise ../__xps/ise/system.ise system.ngc
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
../__xps/ise/system.ise system.ngc
 
 with local file
 
.... Copying flowfile c:/devtools/Xilinx/11.1/ISE/xilinx/data/fpga.flw into
 
C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementat
 

 
C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementat
 
Using Option File(s):
 
tion/xflow.opt
 
Creating Script File ...
 
#----------------------------------------------#
 
# ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm
 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa
 
#----------------------------------------------#
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
 with local file
 

 
timestamp -bm system.bmm
 
ion/system.ngc -uc system.ucf system.ngd
 
Reading NGO file
 
tion/system.ngc" ...
 
Done.
 
Applying constraints in "system.ucf" to the design...
 
   'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_
 
   'VIRTEX5' to correct post-ngdbuild and timing simulation for this primitive.
 
   should be changed in this same manner in the source netlist or constraint
 
Resolving constraint associations...
 
WARNING:ConstraintSystem:3 - Constraint 
 
 
 
   found.
 
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
 
   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
 
   PLL_ADV output(s):
 
   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *
 

 
   'TS_sys_clk_pin', was traced into PLL_ADV instance
 
 
 
   CLKOUT1: 
 
   1.25 HIGH 50%>
 
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
 
 
 
   PLL_ADV output(s):
 
   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *
 

 
 
 
   The following new TNM groups and period specifications were generated at the
 
 
 
   2 HIGH 50%>
 
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
 
 
 
   PLL_ADV output(s):
 
 
 

 
 
 
Processing BMM file ...
 
WARNING:NgdBuild:1212 - User specified non-default attribute value
 
   "clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".
 
 
 
Checking expanded design ...
 
   'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_
 
   has unconnected output pin
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   RE_I' has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
 
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   ' has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
 
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   ' has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
 
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   has unconnected output pin
 
 
 
   ' has unconnected output pin
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   _H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected
   output pin
WARNING:NgdBuild:443 - SFF primitive
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
 
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
 
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
 
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
 
WARNING:NgdBuild:443 - SFF primitive
 
   SIZE2_REG1' has unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
 
WARNING:NgdBuild:443 - SFF primitive
 
   unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'
 
WARNING:NgdBuild:440 - FF primitive
 
   /gen_rden[1].u_calib_rden_r' has unconnected output pin
 
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
 
WARNING:NgdBuild:440 - FF primitive
 
   /gen_rden[3].u_calib_rden_r' has unconnected output pin
 
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
 
WARNING:NgdBuild:440 - FF primitive
 
   /gen_rden[5].u_calib_rden_r' has unconnected output pin
 
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
 
WARNING:NgdBuild:440 - FF primitive
 
   /gen_rden[7].u_calib_rden_r' has unconnected output pin
 
   'ppc440_0_apu_fpu_virtex5/ppc440_0_apu_fpu_virtex5/gen_apu_fpu_dp_lo.netlist/
 
   no_rlocs.fast_del.carry_fd' has unconnected output pin
 
   "clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"
 
WARNING:NgdBuild:452 - logical net 'N194' has no driver
 
WARNING:NgdBuild:452 - logical net 'N196' has no driver
 
WARNING:NgdBuild:452 - logical net 'N198' has no driver
 
WARNING:NgdBuild:452 - logical net 'N200' has no driver
 
WARNING:NgdBuild:452 - logical net 'N202' has no driver
 
WARNING:NgdBuild:452 - logical net 'N204' has no driver
 
WARNING:NgdBuild:452 - logical net 'N206' has no driver
 
WARNING:NgdBuild:452 - logical net 'N208' has no driver
 
WARNING:NgdBuild:452 - logical net 'N210' has no driver
 
WARNING:NgdBuild:452 - logical net 'N212' has no driver
 
WARNING:NgdBuild:452 - logical net 'N214' has no driver
 
WARNING:NgdBuild:452 - logical net 'N216' has no driver
 
WARNING:NgdBuild:452 - logical net 'N218' has no driver
 
WARNING:NgdBuild:452 - logical net 'N220' has no driver
 
WARNING:NgdBuild:452 - logical net 'N222' has no driver
 
WARNING:NgdBuild:452 - logical net 'N224' has no driver
 
WARNING:NgdBuild:452 - logical net 'N226' has no driver
 
WARNING:NgdBuild:452 - logical net 'N228' has no driver
 
WARNING:NgdBuild:452 - logical net 'N230' has no driver
 
WARNING:NgdBuild:452 - logical net 'N232' has no driver
 
WARNING:NgdBuild:452 - logical net 'N234' has no driver
 
WARNING:NgdBuild:452 - logical net 'N236' has no driver
 
WARNING:NgdBuild:452 - logical net 'N238' has no driver
 
WARNING:NgdBuild:452 - logical net 'N240' has no driver
 
WARNING:NgdBuild:452 - logical net 'N242' has no driver
 
WARNING:NgdBuild:452 - logical net 'N244' has no driver
 
WARNING:NgdBuild:452 - logical net 'N246' has no driver
 
WARNING:NgdBuild:452 - logical net 'N248' has no driver
 
WARNING:NgdBuild:452 - logical net 'N250' has no driver
 
WARNING:NgdBuild:452 - logical net 'N252' has no driver
 
WARNING:NgdBuild:452 - logical net 'N254' has no driver
 
WARNING:NgdBuild:452 - logical net 'N256' has no driver
 
WARNING:NgdBuild:452 - logical net 'N266' has no driver
 
WARNING:NgdBuild:452 - logical net 'N268' has no driver
 
WARNING:NgdBuild:452 - logical net 'N270' has no driver
 
WARNING:NgdBuild:452 - logical net 'N272' has no driver
 
WARNING:NgdBuild:452 - logical net 'N306' has no driver
 
WARNING:NgdBuild:452 - logical net 'N308' has no driver
 
WARNING:NgdBuild:452 - logical net 'N310' has no driver
 
WARNING:NgdBuild:452 - logical net 'N312' has no driver
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'
 

 
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
NGDBUILD Design Results Summary:
 
  Number of warnings: 349
 
Writing NGD file "system.ngd" ...
 
Total CPU time to NGDBUILD completion:  1 min  50 sec
 
Writing NGDBUILD log file "system.bld"...
 
NGDBUILD done.
 

 
#----------------------------------------------#
 
# map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing
 
#----------------------------------------------#
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
 with local file
 
Using target part "5vfx70tff1136-1".
 
WARNING:LIT:395 - The above warning message is repeated 1028 more times for the
 
   N195,
 
   N197,
 
   N199
 
Mapping design into LUTs...
 
   connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has
 
WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top
 
WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been
 
Writing file system_map.ngm...
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
 
   of frag REGCLKAU connected to power/ground net
 
   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
 
   of frag REGCLKAL connected to power/ground net
 
   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
 
   of frag REGCLKAU connected to power/ground net
 
   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
 
   of frag REGCLKAL connected to power/ground net
 
   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
 
   of frag RDRCLKU connected to power/ground net
 
   x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
 
   of frag RDRCLKL connected to power/ground net
 
   x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
 
   noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
 
   noeccerr.SDP_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
 
   noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
 
   noeccerr.SDP_RDRCLKL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
 
   ram/SDP.WIDE_PRIM36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
 
   ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
 
   ram/SDP.WIDE_PRIM36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
 
   ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
 
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
 
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
 
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
 
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
 
   36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
 
   36.noeccerr.SDP_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
 
   36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
 
   36.noeccerr.SDP_RDRCLKL_tiesig
 
Running delay-based LUT packing...
 
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM
 
   timing analysis.
 
   (.mrp).
 
Total REAL time at the beginning of Placer: 2 mins 24 secs
 

 
Phase 1.1  Initial Placement Analysis (Checksum:3a0b7697) REAL time: 2 mins 44 secs
 
Phase 2.7  Design Feasibility Check
 
   Components associated with this bus are as follows:
 
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6>   IOSTANDARD = LVCMOS25
 
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4>   IOSTANDARD = LVCMOS18
 
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2>   IOSTANDARD = LVCMOS18
 
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0>   IOSTANDARD = LVCMOS18
 

 
   Components associated with this bus are as follows:
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<30>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<28>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<26>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<24>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<22>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<20>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<18>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<16>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<14>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<12>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<10>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<8>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<6>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<4>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<2>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<0>   IOSTANDARD = LVCMOS33
 

 

 
Phase 3.31  Local Placement Optimization (Checksum:c9fd22c3) REAL time: 2 mins 45 secs
 
Phase 4.37  Local Placement Optimization
 

 
Phase 5.33  Local Placement Optimization (Checksum:c9fd22c3) REAL time: 10 mins 47 secs
 
Phase 6.32  Local Placement Optimization
 

 

 

 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
 
|                                          |                                          |
 
| CLOCKREGION_X0Y6:                        | CLOCKREGION_X1Y6:                        |
 
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
 
|   0 center BUFIOs available, 0 in use    |                                          |
 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
 
|                                          |                                          |
 
| CLOCKREGION_X0Y4:                        | CLOCKREGION_X1Y4:                        |
 
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
 
|   2 center BUFIOs available, 0 in use    |                                          |
 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
 
|                                          |                                          |
 
| CLOCKREGION_X0Y2:                        | CLOCKREGION_X1Y2:                        |
 
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
 
|   2 center BUFIOs available, 0 in use    |                                          |
 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
      |
 
|   0 center BUFIOs available, 0 in use    |                                          |
 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
 
|                                          |                                          |
 

 
Clock-Region: 
 
|-----------------------------------------------------------------------------------------------------------------------------------------------------------
 
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
 
|       | Upper Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region
 
|       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region
 
|       | Lower Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region
 
| clock |    region   |                                                                                      -----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 

 
  key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4
 
|       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|-------
 
|       | Lower Region|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region
 
| clock |    region   |                                                                                      -----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 

 
  key resource utilizations (used/available): edge-bufios - 3/4; bufrs - 0/2; regional-clock-spines - 0/4
 
|       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|  type |  expansion  |                                                                                      | 
 
| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 

 

 
# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:
 
# Number of Regional Clocking Regions in the device: 16  (4 clock spines in each)
 
# composed of up to 3 clock spines and cover up to 3 regional clock regions)
 
######################################################################################
 
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" driven by "BUFIO_X0Y27"
 
"BUFIO_X0Y27" ;
 
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;
 
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;
 
CLOCKREGION_X0Y6;
 

 
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_bufio_dqs" LOC =
 
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" TNM_NET =
 
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" AREA_GROUP =
 
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" RANGE =
 

 
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" driven by "BUFIO_X0Y11"
 
"BUFIO_X0Y11" ;
 
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;
 
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;
 
CLOCKREGION_X0Y2;
 

 
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_bufio_dqs" LOC =
 
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" TNM_NET =
 
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" AREA_GROUP =
 
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" RANGE =
 

 
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" driven by "BUFIO_X0Y25"
 
"BUFIO_X0Y25" ;
 
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;
 
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;
 
CLOCKREGION_X0Y6;
 

 
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_bufio_dqs" LOC =
 
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" TNM_NET =
 
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" AREA_GROUP =
 
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" RANGE =
 

 
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" driven by "BUFIO_X0Y26"
 
"BUFIO_X0Y26" ;
 
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;
 
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;
 
CLOCKREGION_X0Y6;
 

 
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_bufio_dqs" LOC =
 
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" TNM_NET =
 
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" AREA_GROUP =
 
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" RANGE =
 

 
Phase 7.2  Initial Clock and IO Placement (Checksum:b5943100) REAL time: 11 mins 10 secs
 
Phase 8.36  Local Placement Optimization
 

 
..............
 
....
 
......
 
......
 
.......
 
......
 
......
 
.......
 
........
 
Phase 9.30  Global Clock Region Assignment
 

 
# GLOBAL CLOCK NET DISTRIBUTION UCF REPORT:
 
# Number of Global Clock Regions : 16
 
#
 

 
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT1.CLKOUT1_BUFG_INST" LOC = "BUFGCTRL_X0Y1" ;
 
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.gtxclk_pll_bufg" LOC = "BUFGCTRL_X0Y29" ;
 
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT2.CLKOUT2_BUFG_INST" LOC = "BUFGCTRL_X0Y2" ;
 
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/notsame.usrclk_pll_bufg" LOC = "BUFGCTRL_X0Y28" ;
 
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.clkfbin_pll_bufg" LOC = "BUFGCTRL_X0Y26" ;
 
INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/Using_BUFG_for_CLK0.CLK0_BUFG_INST" LOC = "BUFGCTRL_X0Y7" ;
 
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT0.CLKOUT0_BUFG_INST" LOC = "BUFGCTRL_X0Y5" ;
 
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/bufg2" LOC = "BUFGCTRL_X0Y0" ;
 
INST "fpga_0_SRAM_ZBT_CLK_FB_pin" LOC = "IOB_X1Y111" ;
 
INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" LOC = "IOB_X1Y219" ;
 
INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" LOC = "IOB_X1Y105" ;
 
INST "fpga_0_PCIe_Bridge_RXP_pin" LOC = "IPAD_X1Y13" ;
 
INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" LOC = "IPAD_X1Y17" ;
 
INST "fpga_0_PCIe_Bridge_TXP_pin" LOC = "OPAD_X0Y9" ;
 
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y0" ;
 
INST "ibufgds_76" LOC = "BUFDS_X0Y2" ;
 
# clk_125_0000MHzPLL0 driven by BUFGCTRL_X0Y1
 
TIMEGRP "TN_clk_125_0000MHzPLL0" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0" ;
 

 
NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;
 
AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
 
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk driven by BUFGCTRL_X0Y29
 
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;
 

 
NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;
 
AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
 
# clk_125_0000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y2
 
TIMEGRP "TN_clk_125_0000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0_ADJUST" ;
 

 
NET "clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" TNM_NET = "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;
 
AREA_GROUP "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y3 ;
 
# PCIe_Bridge/Bridge_Clk driven by BUFGCTRL_X0Y28
 
TIMEGRP "TN_PCIe_Bridge/Bridge_Clk" AREA_GROUP = "CLKAG_PCIe_Bridge/Bridge_Clk" ;
 

 
NET "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" TNM_NET = "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;
 
AREA_GROUP "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" RANGE =   CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;
 
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin driven by BUFGCTRL_X0Y26
 
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;
 

 
NET "clk_200_0000MHz" TNM_NET = "TN_clk_200_0000MHz" ;
 
AREA_GROUP "CLKAG_clk_200_0000MHz" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
 
# fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF driven by BUFGCTRL_X0Y7
 
TIMEGRP "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" AREA_GROUP = "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;
 

 
NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;
 
AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X1Y2, CLOCKREGION_X1Y3, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;
 
# clk_125_0000MHz90PLL0_ADJUST driven by BUFGCTRL_X0Y5
 
TIMEGRP "TN_clk_125_0000MHz90PLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHz90PLL0_ADJUST" ;
 

 
NET "clk_62_5000MHzPLL0_ADJUST" TNM_NET = "TN_clk_62_5000MHzPLL0_ADJUST" ;
 
AREA_GROUP "CLKAG_clk_62_5000MHzPLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
 
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg driven by BUFGCTRL_X0Y0
 
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;
 

 
# This report is provided to help reproduce successful clock-region
 
# clock networks, in a format that is directly usable in ucf files.
 
#END of Global Clock Net Distribution UCF Constraints
 

 
######################################################################################
 

 
Number of Global Clock Networks: 15
 
Clock Region Assignment: SUCCESSFUL
 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
     12 |      0 |      0 |      0 |     80 |     80 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     38 |    676 |PCIe_Bridge/Bridge_Clk
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 3/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      4 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |     24 |     52 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 6/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      0 |      0 |      0 |     18 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |clk_125_0000MHz90PLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz
 
      0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>
 
      4 |      1 |      1 |      0 |      0 |     35 |      0 |      0 |      0 |      0 |      1 |      0 |     51 |   1110 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    104 |    750 |PCIe_Bridge/Bridge_Clk
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    312 |clk_125_0000MHzPLL0_ADJUST
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 5/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |clk_125_0000MHz90PLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 4/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     59 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
 
      0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     28 |    407 |clk_125_0000MHzPLL0_ADJUST
 
      1 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |    178 |   1153 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
      4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     79 |clk_125_0000MHz90PLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      3 |clk_200_0000MHz
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 3/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     27 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 4/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      4 |      0 |      0 |      0 |      1 |     20 |      0 |      0 |      0 |      0 |      0 |      0 |     51 |    262 |clk_125_0000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |      6 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP
 
      6 |      0 |      0 |      0 |      7 |     20 |      0 |      0 |      0 |      0 |      0 |      0 |     51 |    329 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
     10 |      0 |      0 |      0 |     40 |     40 |     16 |      1 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |PCIe_Bridge/Bridge_Clk
 
      0 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     23 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP
 
      3 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |     76 |   1089 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
     12 |      2 |      1 |      0 |     60 |     60 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     49 |clk_125_0000MHz90PLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     99 |clk_62_5000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |     72 |    749 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
     10 |      0 |      0 |      0 |     40 |     40 |     16 |      1 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     28 |PCIe_Bridge/Bridge_Clk
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 7/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin
 
      0 |      0 |      0 |      0 |      0 |      8 |      0 |      0 |      0 |      0 |      0 |      0 |     91 |    751 |clk_125_0000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    249 |clk_62_5000MHzPLL0_ADJUST
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 2/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      4 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP
 
      0 |      0 |      0 |      0 |     19 |     23 |      0 |      0 |      0 |      0 |      0 |      0 |     97 |    800 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
     12 |      0 |      0 |      0 |     80 |     80 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    106 |    471 |clk_125_0000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    116 |    782 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    146 |    674 |clk_125_0000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    146 |    674 | Total
 

 
The above detailed report is the initial placement of the logic after the clock region assignment. The final placement
 
maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.
 

 
######################################################################################
 

 

 
Phase 10.3  Local Placement Optimization (Checksum:b5943100) REAL time: 12 mins 46 secs
 
Phase 11.5  Local Placement Optimization
 

 
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Phase 12.8  Global Placement (Checksum:64c223c7) REAL time: 20 mins 44 secs
 
Phase 13.29  Local Placement Optimization
 

 
Phase 14.5  Local Placement Optimization (Checksum:64c223c7) REAL time: 20 mins 49 secs
 
Phase 15.18  Placement Optimization
 

 
Phase 16.5  Local Placement Optimization (Checksum:d0a37aa3) REAL time: 23 mins 28 secs
 
Phase 17.34  Placement Validation
 

 
Total CPU  time to Placer completion: 22 mins 30 secs
 
Writing output files...
 
Design Summary:
 
Number of warnings:   52
 
  Number of Slice Registers:                14,755 out of  44,800   32%
 
    Number used as Latches:                      1
 
    Number used as logic:                   15,565 out of  44,800   34%
 
      Number using O5 output only:             371
 
    Number used as Memory:                     724 out of  13,120    5%
 
        Number using O6 output only:            12
 
        Number using O5 and O6:                184
 
        Number using O6 output only:             4
 
        Number using O6 output only:           492
 
  Number of route-thrus:                       581
 
    Number using O5 output only:                81
 

 
  Number of occupied Slices:                 7,735 out of  11,200   69%
 
    Number with an unused Flip Flop:         6,649 out of  21,404   31%
 
    Number of fully used LUT-FF pairs:       9,770 out of  21,404   45%
 
    Number of slice register sites lost
 

 
  one Flip Flop within a slice.  A control set is a unique combination of
 
  The Slice Logic Distribution report is not meaningful if the design is
 
  OVERMAPPING of BRAM resources should be ignored if the design is
 

 
  Number of bonded IOBs:                       255 out of     640   39%
 
    IOB Flip Flops:                            494
 
    Number of bonded OPADs:                      2 out of      32    6%
 
Specific Feature Utilization:
 
    Number using BlockRAM only:                 20
 
    Total primitives used:
 
      Number of 18k BlockRAM used:               6
 
    Total Memory used (KB):                    756 out of   5,328   14%
 
    Number used as BUFGs:                       15
 
  Number of BUFDSs:                              1 out of       8   12%
 
  Number of DCM_ADVs:                            1 out of      12    8%
 
  Number of GTX_DUALs:                           1 out of       8   12%
 
    Number of LOCed PCIEs:                       1 out of       1  100%
 
  Number of PPC440s:                             1 out of       1  100%
 
  Number of RPM macros:           64
 

 
Total REAL time to MAP completion:  24 mins 23 secs
 

 
See MAP report file "system_map.mrp" for details.
 

 
#----------------------------------------------#
 
# par -ise ../__xps/ise/system.ise -w -ol high system_map.ncd system.ncd
 
#----------------------------------------------#
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 

 

 
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
 

 
   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
 
   overrides constraint  [system.pcf(90241)].
 

 
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
 
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP
 
INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please
 

 

 

 

 
   Number of BUFGs                          15 out of 32     46%
 
   Number of DCM_ADVs                        1 out of 12      8%
 
   Number of FIFO36_72_EXPs                  2 out of 148     1%
 

 
   Number of IDELAYCTRLs                     3 out of 22     13%
 

 
      Number of LOCed ILOGICs                8 out of 131     6%
 
   Number of External IOBs                 255 out of 640    39%
 

 
      Number of LOCed IODELAYs               8 out of 80     10%
 
   Number of External IPADs                  4 out of 690     1%
 

 
   Number of OLOGICs                       236 out of 800    29%
 
      Number of LOCed OPADs                  2 out of 2     100%
 
   Number of PCIEs                           1 out of 3      33%
 

 
   Number of PPC440s                         1 out of 1     100%
 
   Number of RAMB36SDP_EXPs                  6 out of 148     4%
 

 
      Number of LOCed RAMB36_EXPs            6 out of 10     60%
 
   Number of Slice Registers             14755 out of 44800  32%
 
      Number used as Latches                 1
 

 
   Number of Slice LUT-Flip Flop pairs   21404 out of 44800  47%
 

 
Router effort level (-rl):    High
 
Starting initial Timing Analysis.  REAL time: 1 mins 25 secs
 

 
   signal.
 
   signal.
 
   signal.
 
   signal.
 
   signal.
 

 
   that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail,
 

 

 

 

 

 

 

 

 

 

 

 
Total REAL time to Router completion: 9 mins 7 secs
 

 
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
Generating "PAR" statistics.
 
**************************
 
**************************
 
+---------------------+--------------+------+------+------------+-------------+
 
+---------------------+--------------+------+------+------------+-------------+
 
|              ADJUST | BUFGCTRL_X0Y2| No   | 4263 |  0.532     |  2.076      |
 
|PCIe_Bridge/Bridge_C |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|               DJUST | BUFGCTRL_X0Y6| No   |  490 |  0.318     |  2.057      |
 
|clk_125_0000MHz90PLL |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|tFlash_SysACE_CLK_pi |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|dge/comp_block_plus/ |              |      |      |            |             |
 
|                  lk |BUFGCTRL_X0Y27| No   |   94 |  0.260     |  2.085      |
 
|fpga_0_Ethernet_MAC_ |              |      |      |            |             |
 
|                     |BUFGCTRL_X0Y30| No   |   12 |  0.093     |  1.934      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
 
|f_top/u_phy_top/u_ph |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
 
| y_io/delayed_dqs<1> |        IO Clk| No   |   18 |  0.083     |  0.380      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
 
|f_top/u_phy_top/u_ph |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
 
| y_io/delayed_dqs<3> |        IO Clk| No   |   18 |  0.107     |  0.404      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
 
      |            |             |
 
| y_io/delayed_dqs<5> |        IO Clk| No   |   18 |  0.101     |  0.425      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
 
|f_top/u_phy_top/u_ph |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
 
| y_io/delayed_dqs<6> |        IO Clk| No   |   18 |  0.096     |  0.393      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
 
|f_top/u_phy_top/u_ph |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|PHY_tx_clk_pin_BUFGP |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
+---------------------+--------------+------+------+------------+-------------+
 
|dge/comp_block_plus/ |              |      |      |            |             |
 
|        lk/gt_usrclk |BUFGCTRL_X0Y29| No   |    6 |  0.096     |  1.916      |
 
|     clk_200_0000MHz | BUFGCTRL_X0Y4| No   |    4 |  0.128     |  1.879      |
 
|RS232_Uart_1_Interru |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|  t_MAC/phy_tx_clk_i |         Local|      |    9 |  2.410     |  3.454      |
 
|ppc440_0_jtagppc_bus |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|dge/comp_block_plus/ |              |      |      |            |             |
 
|lk/SIO/.pcie_gt_wrap |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
* Net Skew is the difference between the minimum and maximum routing
 
is reported in TRCE timing report. Clock Skew is the difference between
 

 

 

 
   This may be due to a setup or hold violation.
 
----------------------------------------------------------------------------------------------------------
 
                                            |             |    Slack   | Achievable | Errors |    Score
 
  NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | SETUP       |     0.030ns|     7.970ns|       0|           0
 
                                            | MINPERIOD   |     0.000ns|     8.000ns|       0|           0
 
  NET "PCIe_Bridge/PCIe_Bridge/comp_block_p | SETUP       |     0.075ns|     3.925ns|       0|           0
 
      4 ns HIGH 50%                         | MINPERIOD   |     0.000ns|     4.000ns|       0|           0
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.012ns|     0.838ns|       0|           0
 
  dqs[2].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS"       | HOLD        |     1.026ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  L0_CLK_OUT_2_ = PERIOD TIMEGRP         "c | HOLD        |     0.079ns|            |       0|           0
 
  LK_OUT_2_" TS_sys_clk_pin *         1.25  |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
 
  DELAY = 0.85 ns                           |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0
 
  dqs[1].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
 
  DELAY = 0.85 ns                           |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0
 
  dqs[3].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
 
  DELAY = 0.85 ns                           |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0
 
  dqs[6].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
 
  DELAY = 0.85 ns                           |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.068ns|     0.532ns|       0|           0
 
  qs<0>"         MAXDELAY = 0.6 ns          |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0
 
  qs<1>"         MAXDELAY = 0.6 ns          |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0
 
  qs<2>"         MAXDELAY = 0.6 ns          |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0
 
  qs<3>"         MAXDELAY = 0.6 ns          |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0
 
  qs<4>"         MAXDELAY = 0.6 ns          |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0
 
  qs<5>"         MAXDELAY = 0.6 ns          |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0
 
  qs<6>"         MAXDELAY = 0.6 ns          |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0
 
  qs<7>"         MAXDELAY = 0.6 ns          |             |            |            |        |
 
  TS_PLB_PCIe = MAXDELAY FROM TIMEGRP "SPLB | SETUP       |     0.449ns|     7.551ns|       0|           0
 
    DATAPATHONLY                            |             |            |            |        |
 
  TS_PCIe_PLB = MAXDELAY FROM TIMEGRP "Brid | SETUP       |     0.639ns|     7.361ns|       0|           0
 
    DATAPATHONLY                            |             |            |            |        |
 
  TS_MC_CLK = PERIOD TIMEGRP "mc_clk" 5 ns  | MINPERIOD   |     1.010ns|     3.990ns|       0|           0
 
------------------------------------------------------------------------------------------------------
 
  RP "PADS" TO TIMEGRP         "RXCLK_GRP_E | HOLD        |     1.060ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  L0_CLK_OUT_0_ = PERIOD TIMEGRP         "c | HOLD        |     0.476ns|            |       0|           0
 
  LK_OUT_0_" TS_sys_clk_pin *         1.25  |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  pin" 100 MHz HIGH 50%                     |             |            |            |        |
 
  TS_clock_generator_0_clock_generator_0_PL | SETUP       |     3.644ns|     1.356ns|       0|           0
 
  lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |
 
  H 50%                                     |             |            |            |        |
 
  TS_clock_generator_0_clock_generator_0_PL | SETUP       |     4.149ns|     8.008ns|       0|           0
 
  lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |
 
   HIGH 50%                                 |             |            |            |        |
 
  NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | NETSKEW     |     4.422ns|     0.578ns|       0|           0
 
------------------------------------------------------------------------------------------------------
 
  UFGP" MAXSKEW = 5 ns                      |             |            |            |        |
 
  TS_clock_generator_0_clock_generator_0_PL | MINPERIOD   |     4.900ns|     3.100ns|       0|           0
 
  lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |
 
  HIGH 50%                                  |             |            |            |        |
 
  TSTXOUT_Ethernet_MAC = MAXDELAY FROM TIME | MAXDELAY    |     7.423ns|     2.577ns|       0|           0
 
  IMEGRP "PADS" 10 ns                       |             |            |            |        |
 
  NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | SETUP       |     9.210ns|    13.685ns|       0|           0
 
------------------------------------------------------------------------------------------------------
 
  M TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO      | HOLD        |     0.290ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
   TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO       | HOLD        |     0.915ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  NM_GATE_DLY" TO TIMEGRP "TNM_CLK0"        | HOLD        |     0.003ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  P "TNM_CAL_RDEN_DLY" TO TIMEGRP         " | HOLD        |     0.001ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  NM_RDEN_DLY" TO TIMEGRP "TNM_CLK0"        | HOLD        |     0.023ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  K_pin_BUFGP/IBUFG" PERIOD = 30 ns         | HOLD        |     0.465ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  UFGP" PERIOD = 40 ns HIGH 14 ns           | HOLD        |     0.357ns|            |       0|           0
 
  Pin to Pin Skew Constraint                | MAXDELAY    | 2106523.523ns| 2106523.837ns|       0|           0
 
  TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGR | N/A         |         N/A|         N/A|     N/A|         N/A
 
  TNM_CLK0" TS_MC_CLK * 4                   |             |            |            |        |
 
  NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | N/A         |         N/A|         N/A|     N/A|         N/A
 
------------------------------------------------------------------------------------------------------
 

 
Derived Constraints for TS_MC_CLK
 
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
 
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
 
|TS_MC_CLK                      |      5.000ns|      3.990ns|      1.584ns|            0|            0|            0|          345|
 
| TS_MC_PHY_INIT_DATA_SEL_90    |     20.000ns|      6.337ns|          N/A|            0|            0|          274|            0|
 
| TS_MC_RDEN_DLY                |     20.000ns|      1.868ns|          N/A|            0|            0|            5|            0|
 
| TS_MC_RDEN_SEL_MUX            |     20.000ns|          N/A|          N/A|            0|            0|            0|            0|
 

 
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
 
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 
| TS_clock_generator_0_clock_gen|      8.000ns|      4.973ns|          N/A|            0|            0|          626|            0|
 
| TS_clock_generator_0_clock_gen|      8.000ns|      3.100ns|          N/A|            0|            0|            0|            0|
 
| TS_clock_generator_0_clock_gen|      8.000ns|      7.974ns|          N/A|            0|            0|      4031781|            0|
 
| TS_clock_generator_0_clock_gen|      5.000ns|      1.356ns|          N/A|            0|            0|            2|            0|
 
| TS_clock_generator_0_clock_gen|     16.000ns|      8.008ns|          N/A|            0|            0|        11042|            0|
 
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 
All constraints were met.
 
   constraint does not cover any paths or that it has no requested value.
 

 

 

 

 
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
 
INFO:ParHelpers:199 - All "EXACT" mode Directed Routing constrained nets successfully routed. The number of constraints
 
Total REAL time to PAR completion: 10 mins 4 secs
 

 

 
Routing: Completed - No errors found.
 

 
Number of warning messages: 9
 

 

 

 

 

 
# Starting program post_par_trce
 
#----------------------------------------------#
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 

 
 with local file
 
Loading device for application Rf_Device from file '5vfx70t.nph' in environment
 
   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
 
   8 ns HIGH 50%;> [system.pcf(90242)] overrides constraint 
 

 
   TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP        "TNM_CLK0" TS_MC_CLK * 4;
 
INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more
 
   Tools User Guide for information on generating a TSI report.
 
Release 11.2 Trace  (nt)
 

 

 
Design file:              system.ncd
 
Device,speed:             xc5vfx70t,-1 (PRODUCTION 1.65 2009-06-01, STEPPING
 
Report level:             error report
 

 
   option. All paths that are not constrained will be reported in the
 
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a
 
   for more information on accounting for different loading conditions, please
 

 
Timing summary:
 

 

 

 
   Minimum period:  13.685ns (Maximum frequency:  73.073MHz)
 
   Maximum net delay:   0.838ns
 

 
Analysis completed Tue Jun 30 23:01:07 2009
 

 

 
Number of info messages: 3
 

 
xflow done!
 
xilperl C:/devtools/Xilinx/11.1/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par
 
*********************************************
 
*********************************************
 
Release 11.2 - Bitgen L.46 (nt)
 
PMSPEC -- Overriding Xilinx file
 

 
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
 
Opened constraints file system.pcf.
 
Tue Jun 30 23:01:40 2009
 
Running DRC.
 
   Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX
 
   guidelines to minimize the impact on GTX performance.
 
   Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.
 
   data into the flip-flop.
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_w
 
   design practice. Use the CE pin to control the loading of data into the
 
WARNING:PhysDesignRules:367 - The signal
 
   not drive any load pins in the design.
 
   > is incomplete. The signal does not
 
WARNING:PhysDesignRules:367 - The signal
 
   drive any load pins in the design.
 
   > is incomplete. The signal does not
 
WARNING:PhysDesignRules:367 - The signal 
 
WARNING:PhysDesignRules:1269 - Dangling pins on
 
   qs[1].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
 
WARNING:PhysDesignRules:1273 - Dangling pins on
 
   qs[1].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
 
WARNING:PhysDesignRules:1269 - Dangling pins on
 
   qs[4].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
 
WARNING:PhysDesignRules:1273 - Dangling pins on
 
   qs[4].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
 
WARNING:PhysDesignRules:1269 - Dangling pins on
 
   qs[7].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
 
WARNING:PhysDesignRules:1273 - Dangling pins on
 
   qs[7].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
 
WARNING:PhysDesignRules:1269 - Dangling pins on
 
   qs[2].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
 
WARNING:PhysDesignRules:1273 - Dangling pins on
 
   qs[2].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
 
WARNING:PhysDesignRules:1269 - Dangling pins on
 
   qs[5].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
 
WARNING:PhysDesignRules:1273 - Dangling pins on
 
   qs[5].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
 
WARNING:PhysDesignRules:1269 - Dangling pins on
 
   qs[0].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
 
WARNING:PhysDesignRules:1273 - Dangling pins on
 
   qs[0].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
 
WARNING:PhysDesignRules:1269 - Dangling pins on
 
   qs[3].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
 
WARNING:PhysDesignRules:1273 - Dangling pins on
 
   qs[3].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
 
WARNING:PhysDesignRules:1269 - Dangling pins on
 
   qs[6].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
 
WARNING:PhysDesignRules:1273 - Dangling pins on
 
   qs[6].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
 
WARNING:PhysDesignRules:367 - The signal
 
   fpu_is_full.sqrt_sqrt_flt_pt_op_sqrt_op.spd.op_exp_exp_sig_del_delay_55_2/Pro
 
   in the design.
 
   
 
   toComp7000.C6LUT.O6> is incomplete. The signal does not drive any load pins
 
DRC detected 0 errors and 26 warnings.  Please see the previously displayed
 
Creating bit map...
 
Bitstream generation is complete.
 

 

 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
 
Done writing Tab View settings to:
 

 
Xilinx EDK 11.2 Build EDK_LS3.47
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
 
Generating Block Diagram to Buffer
 
Generated Block Diagram SVG
 
At Local date and time: Wed Jul 01 10:06:56 2009
 

 
*********************************************
 
*********************************************
 
-bt implementation/system.bit -o implementation/download.bit
 
bitinit version Xilinx EDK 11.2 Build EDK_LS3.47
 

 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
 
   hs line 253 - deprecated core for architecture 'virtex5fx'!
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m
 

 

 

 
Address Map for Processor ppc440_0
 
  (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC
 
  (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0
 
 
 
  (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0
 
  (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0
 
 
 
  (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0
 
 
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
 
 
 
Computing clock values...
 
   'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be
 
   through the clock generator IP.
 
 
 
   performed for IPs connected to that clock port, unless they are connected
 

 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
 
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
 
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
 
 
 
 
 
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   value to 0x2000
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   C_PORT_DWIDTH value to 64
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   value to 8
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
 
   C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_MPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_MPLB_SMALLEST_SLAVE value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_SLAVES value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
 
   PARAMETER C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
 
   value to 128
 
Checking platform address map ...
 
Initializing Memory...
 
data2mem -bm "implementation/system_bd" -bt "implementation/system.bit"  -bd
 
Memory Initialization completed successfully.
 
*********************************************
 
*********************************************
 
Release 11.2 - iMPACT L.46 (nt)
 
Preference Table
 
StartupClock         Auto_Correction
 
KeepSVF              False
 
UseHighz             False
 
UserLevel            Novice
 
svfUseTime           false
 
AutoDetecting cable. Please wait.
 
Checking cable driver.
 
 Driver version: src=2301, dest=2301.
 
13:58:07, version = 900.
 
 Max current requested during enumeration is 300 mA.
 
write (count, cmdBuffer, dataBuffer) failed C0000004.
 
 Setting cable speed to 6 MHz.
 
Firmware version = 2301.
 
Firmware hex file version = 2401.
 
Downloaded firmware version = 2401.
 
 PLD version = 200Dh.
 
INFO:iMPACT:1777 -
 

 
----------------------------------------------------------------------
 
INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.
 
   Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...
 
----------------------------------------------------------------------
 
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
 

 
   Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...
 
----------------------------------------------------------------------
 
'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15
 

 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
done.
 
Elapsed time =      0 sec.
 
INFO:iMPACT:1777 -
 
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
 

 
UserID read from the bitstream file = 0xFFFFFFFF.
 
----------------------------------------------------------------------
 
Maximum TCK operating frequency for this device chain: 10000000.
 
Boundary-scan chain validated successfully.
 

 
Reading:   41.02 C
 
Reading:   1.002 V
 
Reading:   2.508 V
 
 Match_cycle = 2.
 
'5': Reading status register contents...
 
Decryptor security set                            :         0
 
DCI matched                                       :         1
 
status of GTS_CFG_B                               :         1
 
status of GHIGH                                   :         1
 
value of MODE pin M1                              :         0
 
Internal signal indicates when housecleaning is completed:         1
 
Internal signal indicates that chip is configured :         1
 
Indicates when ID value written does not match chip ID:         0
 
System Monitor Over-Temperature Alarm             :         0
 
startup_state[19] CFG startup state machine       :         0
 
E-fuse program voltage available                  :         0
 
SPI Flash Type[23] Select                         :         1
 
CFG bus width auto detection result               :         0
 
Reserved                                          :         0
 
IPROG pulsed                                      :         0
 
Indicates that efuse logic is busy                :         0
 
'5': Programmed successfully.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
INFO:iMPACT:2219 - Status register values:
 
INFO:iMPACT:579 - '5': Completed downloading bit file to device.
 
INFO:iMPACT - '5': Checking done pin....done.
 

 
Done!
 
At Local date and time: Wed Jul 01 10:07:40 2009
 

 
Creating software libraries...
 
libgen -mhs system.mhs -p xc5vfx70tff1136-1  -msg __xps/ise/xmsgprops.lst system.mss
 
Xilinx EDK 11.2 Build EDK_LS3.47
 

 
__xps/ise/xmsgprops.lst system.mss
 
Release 11.2 - psf2Edward EDK_LS3.47 (nt)
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
 
   hs line 253 - deprecated core for architecture 'virtex5fx'!
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
 
   hs line 253 - deprecated core for architecture 'virtex5fx'!
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m
 

 
IPNAME:plb_v46 INSTANCE:plb_v46_0 -
 
line 109 - 1 master(s) : 12 slave(s)
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
IPNAME:fcb_v20 INSTANCE:ppc440_0_fcb_v20 -
 
 
 
Checking port drivers...
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m
 
 
 

 

 

 

 

 

 

 
WARNING:EDK:411 - pcie -
 
   ss line 77 - deprecated driver!
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m
 
INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0:
 
 
 
 
 
  - LEDs_Positions
 
  - Push_Buttons_5Bit
 
  - SRAM
 
  - ppc440_0_apu_fpu_virtex5
 
  - xps_intc_0
 
-- Generating libraries for processor: ppc440_0 --
 

 
Running DRCs.
 
Running post_generate.
 
"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mfpu=dp_full -mcpu=440  -O2 -c"
 

 
"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mfpu=dp_full -mcpu=440  -O2 -c"
 
Compiling common
 

 
Compiling standalone
 
Compiling emaclite
 
Compiling pci
 
Compiling sysace
 
Compiling cpu_ppc440
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
   text    data     bss     dec     hex filename
 

 
Done!
 
At Local date and time: Wed Jul 01 11:26:01 2009
 

 
Downloading Bitstream onto the target board
 
impact -batch etc/download.cmd
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
Name                 Setting
 
AutoSignature        False
 
ConcurrentMode       False
 
ConfigOnFailure      Stop
 
MessageLevel         Detailed
 
 
 
 
 
 Driver file xusb_xp2.sys found.
 
 
 
 Cable PID = 0008.
 
Type = 0x0005.
 
 
 
Firmware version = 2401.
 
Firmware hex file version = 2401.
 
 
 
INFO:iMPACT:1777 -
 

 
 
 
----------------------------------------------------------------------
 
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
 
 
 
INFO:iMPACT:501 - '1': Added Device xccace successfully.
 
 
 
 
 
 
 
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
 
----------------------------------------------------------------------
 
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
 
----------------------------------------------------------------------
 
Elapsed time =      1 sec.
 
'5': Loading file 'implementation/download.bit' ...
 
   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
 
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
 
done.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
Validating chain...
 
5: Device Temperature: Current Reading:   33.15 C, Min. Reading:   30.69 C, Max.
 
5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.
 
5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.502 V, Max.
 
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
 
'5': Programming device...
 
done.
 
CRC error                                         :         0
 
DCM locked                                        :         1
 
End of startup signal from Startup block          :         1
 
status of GWE                                     :         1
 
value of MODE pin M0                              :         1
 
Value of MODE pin M2                              :         1
 
Value driver in from INIT pad                     :         1
 
Value of DONE pin                                 :         1
 
Decryptor error Signal                            :         0
 
startup_state[18] CFG startup state machine       :         0
 
startup_state[20] CFG startup state machine       :         1
 
SPI Flash Type[22] Select                         :         1
 
SPI Flash Type[24] Select                         :         1
 
CFG bus width auto detection result               :         0
 
BPI address wrap around error                     :         0
 
read back crc error                               :         0
 
 Match_cycle = 2.
 
Elapsed time =     11 sec.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
 
INFO:iMPACT - '5': Programing completed successfully.
 

 

 

 

 

WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
 
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
 
Done.
 
Done.
 
Done.
 
Done.
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
 
 
 
 
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
 
Done.
 
Done.
 
Done.
 
Writing filter settings....
 
Done writing filter settings to:
 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
 
Xilinx Platform Studio (XPS)
 

 

 

 
 
 
 
 

 

 

 

 

 

 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
 
Done writing Tab View settings to:
 

Xilinx Platform Studio (XPS)
 

 

 

 

 

 

 

 

 

 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
 
 
 
 
 
Xilinx EDK 11.2 Build EDK_LS3.47
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
 
Generating Block Diagram to Buffer
 
Generated Block Diagram SVG
 
At Local date and time: Wed Jul 01 17:11:24 2009
 

 
Downloading Bitstream onto the target board
 
impact -batch etc/download.cmd
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
Name                 Setting
 
AutoSignature        False
 
ConcurrentMode       False
 
ConfigOnFailure      Stop
 
MessageLevel         Detailed
 
 
AutoDetecting cable. Please wait.
 
Checking cable driver.
 
 Driver version: src=2301, dest=2301.
 
13:58:07, version = 900.
 
 Max current requested during enumeration is 150 mA.
 
 
 
 
 
 
 
 
 
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6
 
   Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...
 
----------------------------------------------------------------------
 
'1': : Manufacturer's ID = Xilinx xccace, Version : 0
 
INFO:iMPACT:1777 -
 

 
----------------------------------------------------------------------
 
INFO:iMPACT:501 - '1': Added Device xccace successfully.
 
 
 

 
----------------------------------------------------------------------
 
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
 
INFO:iMPACT:1777 -
 

 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
done.
 
Elapsed time =      0 sec.
 
 
 
 
 
UserID read from the bitstream file = 0xFFFFFFFF.
 
----------------------------------------------------------------------
 
Maximum TCK operating frequency for this device chain: 10000000.
 
Boundary-scan chain validated successfully.
 
Reading:   42.99 C
 
Reading:   1.002 V
 
Reading:   2.505 V
 

 
 Match_cycle = 2.
 
 
 
 
 
DCI matched                                       :         1
 
status of GTS_CFG_B                               :         1
 
status of GHIGH                                   :         1
 
value of MODE pin M1                              :         0
 
Internal signal indicates when housecleaning is completed:         1
 
Internal signal indicates that chip is configured :         1
 
Indicates when ID value written does not match chip ID:         0
 
System Monitor Over-Temperature Alarm             :         0
 
startup_state[19] CFG startup state machine       :         0
 
 
 
 
 
CFG bus width auto detection result               :         0
 
Reserved                                          :         0
 
IPROG pulsed                                      :         0
 
Indicates that efuse logic is busy                :         0
 
'5': Programmed successfully.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
INFO:iMPACT:2219 - Status register values:
 
 
 
 
 
----------------------------------------------------------------------
 

 
Done!
 
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
 
Done.
 
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
 
Done.
 
At Local date and time: Wed Jul 01 17:17:34 2009
 

 
 
 
 
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
Name                 Setting
 
AutoSignature        False
 
ConcurrentMode       False
 
ConfigOnFailure      Stop
 
MessageLevel         Detailed
 
SpiByteSwap          Auto_Correction
 
Connecting to cable (Usb Port - USB21).
 
 Driver file xusb_xp2.sys found.
 
 
 
 
 
Type = 0x0005.
 
 Setting cable speed to 6 MHz.
 
Firmware version = 2401.
 
Firmware hex file version = 2401.
 
 PLD version = 200Dh.
 
INFO:iMPACT:1777 -
 

 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
 
 
 
 
INFO:iMPACT:501 - '1': Added Device xccace successfully.
 
----------------------------------------------------------------------
 
'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
done.
 
Elapsed time =      0 sec.
 
INFO:iMPACT:1777 -
 
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
 
 
 
 
 
done.
 
 
 
----------------------------------------------------------------------
 
Validating chain...
 
 
 
5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.996 V, Max.
Reading:   0.999 V
5: VCCAUX Supply: Current Reading:   2.502 V, Min. Reading:   2.502 V, Max.
 
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.

'5': Programming device...
 Match_cycle = 2.
done.
'5': Reading status register contents...
CRC error                                         :         0
Decryptor security set                            :         0
DCM locked                                        :         1
DCI matched                                       :         1
End of startup signal from Startup block          :         1
status of GTS_CFG_B                               :         1
status of GWE                                     :         1
status of GHIGH                                   :         1
value of MODE pin M0                              :         1
value of MODE pin M1                              :         0
 
Internal signal indicates when housecleaning is completed:         1
 
 
 
 
 
System Monitor Over-Temperature Alarm             :         0
 
startup_state[19] CFG startup state machine       :         0
 
E-fuse program voltage available                  :         0
 
SPI Flash Type[23] Select                         :         1
 
CFG bus width auto detection result               :         0
 
Reserved                                          :         0
 
IPROG pulsed                                      :         0
 
 
 
'5': Programmed successfully.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
INFO:iMPACT:2219 - Status register values:
 
INFO:iMPACT:579 - '5': Completed downloading bit file to device.
 
INFO:iMPACT - '5': Checking done pin....done.
 

 
Done!
 
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
 
Done.
 
Done.
 
Done.
 
Done.
 
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
 
Writing filter settings....
 
Done writing filter settings to:
 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
 
Xilinx Platform Studio (XPS)
 

 

 

 

 

 

 

 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
 
Done writing Tab View settings to:
 

 
 
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
 
Generating Block Diagram to Buffer
 
 
 
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
 
At Local date and time: Wed Jul 01 18:45:58 2009
 

 
Downloading Bitstream onto the target board
 
 
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
Name                 Setting
 
AutoSignature        False
 
ConcurrentMode       False
 
 
 
MessageLevel         Detailed
 
SpiByteSwap          Auto_Correction
 
Connecting to cable (Usb Port - USB21).
 
 Driver file xusb_xp2.sys found.
 
 
 
 Cable PID = 0008.
 
Type = 0x0005.
 
 Setting cable speed to 6 MHz.
 
Firmware version = 2401.
 
 
 
 PLD version = 200Dh.
 
INFO:iMPACT:1777 -
 

 
----------------------------------------------------------------------
 
 
 
INFO:iMPACT:1777 -
 

 
----------------------------------------------------------------------
 
INFO:iMPACT:501 - '1': Added Device xccace successfully.
 
 
 

 
----------------------------------------------------------------------
 
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
 
INFO:iMPACT:1777 -
 
 
 
----------------------------------------------------------------------
 
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
 
----------------------------------------------------------------------
 
done.
 
 
 
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
 
done.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
 
 
Validating chain...
 
5: Device Temperature: Current Reading:   42.99 C, Min. Reading:   37.58 C, Max.
 
5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.
 
5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.502 V, Max.
 
 
 
done.
 
CRC error                                         :         0
 
DCM locked                                        :         1
 
End of startup signal from Startup block          :         1
 
 
 
value of MODE pin M0                              :         1
 
Value of MODE pin M2                              :         1
 
Value driver in from INIT pad                     :         1
 
Value of DONE pin                                 :         1
 
 
 
startup_state[18] CFG startup state machine       :         0
 
startup_state[20] CFG startup state machine       :         1
 
SPI Flash Type[22] Select                         :         1
 
SPI Flash Type[24] Select                         :         1
 
 
 
BPI address wrap around error                     :         0
 
read back crc error                               :         0
 
 Match_cycle = 2.
 
Elapsed time =     11 sec.
 
 
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
 
INFO:iMPACT - '5': Programing completed successfully.
 

 

 
 
 
 
 

 

 
 
 
Done writing Tab View settings to:
 

 
 
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
 
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
 
Generating Block Diagram to Buffer
 
Generated Block Diagram SVG
 
At Local date and time: Thu Jul 02 09:58:07 2009
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  51202     372   87844  139418   2209a RTOSDemo/executable.elf
 

 

 
 
 
 
 
*********************************************
 
 
 
Preference Table
 
 
 
 
 
UseHighz             False
 
UserLevel            Novice
 
svfUseTime           false
 
AutoDetecting cable. Please wait.
 
Checking cable driver.
 
 Driver version: src=2301, dest=2301.
 
13:58:07, version = 900.
 
 Max current requested during enumeration is 300 mA.
 
write (count, cmdBuffer, dataBuffer) failed C0000004.
 
 Setting cable speed to 6 MHz.
 
Firmware version = 2301.
 
Firmware hex file version = 2401.
 
 
 
 PLD version = 200Dh.
 
INFO:iMPACT:1777 -
 

 
 
 
 
 
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
 
INFO:iMPACT:1777 -
 
INFO:iMPACT:501 - '1': Added Device xccace successfully.
 
----------------------------------------------------------------------
 
'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15
 
   Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...
 

 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
done.
 
Elapsed time =      0 sec.
 
 
 
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
 
 
 
 
 
 
 
Maximum TCK operating frequency for this device chain: 10000000.
 
Boundary-scan chain validated successfully.
 
Reading:   32.66 C
 
 
 
 
 

 
 Match_cycle = 2.
 
'5': Reading status register contents...
 
Decryptor security set                            :         0
 
DCI matched                                       :         1
 
status of GTS_CFG_B                               :         1
 
status of GHIGH                                   :         1
 
value of MODE pin M1                              :         0
 
Internal signal indicates when housecleaning is completed:         1
 
Internal signal indicates that chip is configured :         1
 
 
 
System Monitor Over-Temperature Alarm             :         0
 
 
 
 
 
SPI Flash Type[23] Select                         :         1
 
CFG bus width auto detection result               :         0
 
Reserved                                          :         0
 
 
 
 
 
'5': Programmed successfully.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
INFO:iMPACT:2219 - Status register values:
 
INFO:iMPACT:579 - '5': Completed downloading bit file to device.
 
INFO:iMPACT - '5': Checking done pin....done.
 

 
Done!
 
 
 
 
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
 
 
 
 
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
 
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
 
At Local date and time: Thu Jul 02 10:23:31 2009
 
 
 
 
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  50962     372   87844  139178   21faa RTOSDemo/executable.elf
 

 

 

 

 
 make -f system.make download started...
 
*********************************************
 
*********************************************
 
Release 11.2 - iMPACT L.46 (nt)
 
Preference Table
 
 
 
 
 
 
 
UserLevel            Novice
 
svfUseTime           false
 
AutoDetecting cable. Please wait.
 
 
 
 
 
13:58:07, version = 900.
 
 Max current requested during enumeration is 300 mA.
 
 Cable Type = 3, Revision = 0.
 
Cable connection established.
 
File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.
 
PLD file version = 200Dh.
 
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6
 
   Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...
 
----------------------------------------------------------------------
 
'1': : Manufacturer's ID = Xilinx xccace, Version : 0
 
 
 
 
 
 
 
 
 
INFO:iMPACT:1777 -
 
 
 
----------------------------------------------------------------------
 
 
 
 
 
----------------------------------------------------------------------
 
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
 
----------------------------------------------------------------------
 
Elapsed time =      1 sec.
 
'5': Loading file 'implementation/download.bit' ...
 
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
 
done.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
Validating chain...
 
5: Device Temperature: Current Reading:   41.02 C, Min. Reading:   36.10 C, Max.
 
 
 
5: VCCAUX Supply: Current Reading:   2.502 V, Min. Reading:   2.502 V, Max.
 
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
 
'5': Programming device...
 
done.
 
 
 
 
 
End of startup signal from Startup block          :         1
 
status of GWE                                     :         1
 
value of MODE pin M0                              :         1
 
Value of MODE pin M2                              :         1
 
Value driver in from INIT pad                     :         1
 
Value of DONE pin                                 :         1
 
Decryptor error Signal                            :         0
 
startup_state[18] CFG startup state machine       :         0
 
startup_state[20] CFG startup state machine       :         1
 
SPI Flash Type[22] Select                         :         1
 
SPI Flash Type[24] Select                         :         1
 
CFG bus width auto detection result               :         0
 
 
 
 
 
 Match_cycle = 2.
 
Elapsed time =     11 sec.
 
----------------------------------------------------------------------
 
 
 
 
 
----------------------------------------------------------------------
 
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
 
INFO:iMPACT - '5': Programing completed successfully.
 

 

 

 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
 
 
   text    data     bss     dec     hex filename
 
 
 
Done!
 
Done.
 
At Local date and time: Thu Jul 02 11:19:46 2009
 
 
 
 
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  50970     372   87852  139194   21fba RTOSDemo/executable.elf
 

 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
   text    data     bss     dec     hex filename
 

 
 
 
 
 
 
 

 
 
 
powerpc-eabi-size RTOSDemo/executable.elf
 
 
 
 
 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
   text    data     bss     dec     hex filename
 

 
Done!
 
Done.
 
At Local date and time: Thu Jul 02 11:55:33 2009
 
 
 
 
 
 
 
 
 

 
 
 

 
 
 
 
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
   text    data     bss     dec     hex filename
 

 
Done!
 
Done.
 
At Local date and time: Thu Jul 02 13:29:26 2009
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  51242     372   87852  139466   220ca RTOSDemo/executable.elf
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Preference Table
 
 
 
KeepSVF              False
 
 
 
 
 
svfUseTime           false
 
AutoDetecting cable. Please wait.
 
Checking cable driver.
 
 Driver version: src=2301, dest=2301.
 
13:58:07, version = 900.
 
 Max current requested during enumeration is 300 mA.
 
 Cable Type = 3, Revision = 0.
 
Cable connection established.
 
File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.
 
PLD file version = 200Dh.
 
 
 
 
 
----------------------------------------------------------------------
 
 
 

 
 
 
 
 
INFO:iMPACT:501 - '1': Added Device xccace successfully.
 
INFO:iMPACT:1777 -
 

 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
 
INFO:iMPACT:1777 -
 
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
 
----------------------------------------------------------------------
 
done.
 
 
 
 
 
 
 
----------------------------------------------------------------------
 
 
 
Validating chain...
 
 
 
 
 
5: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.493 V, Max.
 
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
 
'5': Programming device...
 
done.
 
CRC error                                         :         0
 
DCM locked                                        :         1
 
End of startup signal from Startup block          :         1
 
status of GWE                                     :         1
 
value of MODE pin M0                              :         1
 
Value of MODE pin M2                              :         1
 
 
 
Value of DONE pin                                 :         1
 
 
 
startup_state[18] CFG startup state machine       :         0
 
 
 
SPI Flash Type[22] Select                         :         1
 
SPI Flash Type[24] Select                         :         1
 
CFG bus width auto detection result               :         0
 
BPI address wrap around error                     :         0
 
 
 
 
 
Elapsed time =     11 sec.
 
----------------------------------------------------------------------
 
 
 
 
 
----------------------------------------------------------------------
 
 
 
INFO:iMPACT - '5': Programing completed successfully.
 

 
 
 

 

 
 
 

 
 make -f system.make download started...

*********************************************
Downloading Bitstream onto the target board
 
impact -batch etc/download.cmd
Release 11.2 - iMPACT L.46 (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
Preference Table
Name                 Setting
StartupClock         Auto_Correction
AutoSignature        False
KeepSVF              False
ConcurrentMode       False
UseHighz             False
ConfigOnFailure      Stop
UserLevel            Novice
MessageLevel         Detailed
svfUseTime           false
SpiByteSwap          Auto_Correction
AutoDetecting cable. Please wait.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
 Driver file xusb_xp2.sys found.
 Driver version: src=2301, dest=2301.
 Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS
13:58:07, version = 900.
 Cable PID = 0008.
 
Type = 0x0005.
 Cable Type = 3, Revision = 0.
 Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 2401.
File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.
Firmware hex file version = 2401.
PLD file version = 200Dh.
 PLD version = 200Dh.
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6
INFO:iMPACT:1777 -
 

----------------------------------------------------------------------
----------------------------------------------------------------------
'1': : Manufacturer's ID = Xilinx xccace, Version : 0
INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.

----------------------------------------------------------------------
----------------------------------------------------------------------
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
INFO:iMPACT:1777 -
   Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...
INFO:iMPACT:501 - '1': Added Device xccace successfully.

----------------------------------------------------------------------
----------------------------------------------------------------------
'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15
INFO:iMPACT:1777 -
   Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.

----------------------------------------------------------------------
----------------------------------------------------------------------
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
----------------------------------------------------------------------
----------------------------------------------------------------------
done.
Elapsed time =      1 sec.
Elapsed time =      0 sec.
'5': Loading file 'implementation/download.bit' ...
INFO:iMPACT:1777 -
   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.

done.
UserID read from the bitstream file = 0xFFFFFFFF.
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
Maximum TCK operating frequency for this device chain: 10000000.
Validating chain...
Boundary-scan chain validated successfully.
5: Device Temperature: Current Reading:   73.02 C, Min. Reading:   70.06 C, Max.
 
5: VCCINT Supply: Current Reading:   0.993 V, Min. Reading:   0.993 V, Max.
Reading:   0.999 V
5: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.493 V, Max.
Reading:   2.502 V
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.

'5': Programming device...
 Match_cycle = 2.
done.
'5': Reading status register contents...
CRC error                                         :         0
Decryptor security set                            :         0
DCM locked                                        :         1
DCI matched                                       :         1
End of startup signal from Startup block          :         1
status of GTS_CFG_B                               :         1
status of GWE                                     :         1
status of GHIGH                                   :         1
value of MODE pin M0                              :         1
value of MODE pin M1                              :         0
 
Internal signal indicates when housecleaning is completed:         1
Value driver in from INIT pad                     :         1
Internal signal indicates that chip is configured :         1
Value of DONE pin                                 :         1
Indicates when ID value written does not match chip ID:         0
Decryptor error Signal                            :         0
System Monitor Over-Temperature Alarm             :         0
startup_state[18] CFG startup state machine       :         0
startup_state[19] CFG startup state machine       :         0
startup_state[20] CFG startup state machine       :         1
E-fuse program voltage available                  :         0
SPI Flash Type[22] Select                         :         1
 
SPI Flash Type[24] Select                         :         1
CFG bus width auto detection result               :         0
CFG bus width auto detection result               :         0
Reserved                                          :         0
BPI address wrap around error                     :         0
IPROG pulsed                                      :         0
 
Indicates that efuse logic is busy                :         0
 Match_cycle = 2.
'5': Programmed successfully.
Elapsed time =     12 sec.
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
----------------------------------------------------------------------
 
INFO:iMPACT:2219 - Status register values:
 
 
 
INFO:iMPACT - '5': Checking done pin....done.
 

 
 
 
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
 
At Local date and time: Thu Jul 02 13:38:54 2009
 
 
 

 
Done!
 
 
 

 

 
 
 
At Local date and time: Thu Jul 02 13:39:21 2009
 

 
 
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  50774     372   87852  138998   21ef6 RTOSDemo/executable.elf
 

 

 
 
 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
   text    data     bss     dec     hex filename
 

 
Done!
 
At Local date and time: Thu Jul 02 13:53:08 2009
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  50542     372   87860  138774   21e16 RTOSDemo/executable.elf
 

 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
   text    data     bss     dec     hex filename
 

 
Done!
 
At Local date and time: Thu Jul 02 14:20:50 2009
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  50298     372   87852  138522   21d1a RTOSDemo/executable.elf
 

 
 
 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c:426: error: 'tskTCB' has no member named 'xEventTaskList'
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1543: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
 
 
 

 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c:426: error: 'tskTCB' has no member named 'xEventList'
 
 
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1543: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
 

 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:839: warning: assignment from incompatible pointer type
 
make: *** [RTOSDemo/executable.elf] Error 1
 
 
 
Done!
 
At Local date and time: Thu Jul 02 15:32:24 2009
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1543: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
 

 
   text    data     bss     dec     hex filename
 

 
Done!
 
At Local date and time: Thu Jul 02 15:38:48 2009
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1549: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: 'xSecondary' undeclared (first use in this function)
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: for each function it appears in.)
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
 
 
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
 

 
 
 

 

 
 make -f system.make program started...
 
 
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1548: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
 
 
 
 
 
 
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
 

 

 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
 
 
 
 

 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:348: warning: comparison of distinct pointer types lacks a cast
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:394: warning: comparison of distinct pointer types lacks a cast
 
 
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  51334     372   87852  139558   22126 RTOSDemo/executable.elf
 

 

 
 
 
 
 
*********************************************
 
Release 11.2 - iMPACT L.46 (nt)
 
 
 
StartupClock         Auto_Correction
 
KeepSVF              False
 
UseHighz             False
 
UserLevel            Novice
 
 
 
AutoDetecting cable. Please wait.
 
 
 
 
 
 
 
 Max current requested during enumeration is 300 mA.
 
 
 
Cable connection established.
 
File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.
 
PLD file version = 200Dh.
 
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6
 
   Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...
 
----------------------------------------------------------------------
 
'1': : Manufacturer's ID = Xilinx xccace, Version : 0
 
 
 
INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.
 
   Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...
 

 
 
 
----------------------------------------------------------------------
 
'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15
 
 
 
----------------------------------------------------------------------
 
done.
 
 
 
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
 
   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
 
 
 
done.
 
----------------------------------------------------------------------
 
 
 
Validating chain...
 
5: Device Temperature: Current Reading:   69.08 C, Min. Reading:   66.62 C, Max.
 
5: VCCINT Supply: Current Reading:   0.993 V, Min. Reading:   0.990 V, Max.
 
5: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.493 V, Max.
 
 
 
'5': Programming device...
 
done.
 
 
 
DCM locked                                        :         1
 
End of startup signal from Startup block          :         1
 
status of GWE                                     :         1
 
value of MODE pin M0                              :         1
 
Value of MODE pin M2                              :         1
 
 
 
Value of DONE pin                                 :         1
 
Decryptor error Signal                            :         0
 
 
 
startup_state[20] CFG startup state machine       :         1
 
SPI Flash Type[22] Select                         :         1
 
SPI Flash Type[24] Select                         :         1
 
CFG bus width auto detection result               :         0
 
 
 
read back crc error                               :         0
 
 Match_cycle = 2.
 
 
 
 
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
 
 
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
 
INFO:iMPACT - '5': Programing completed successfully.
 
 
 

 

 

 
 make -f system.make program started...
 
make: Nothing to be done for `program'.
 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c:426: warning: dereferencing 'void *' pointer
 
 
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:844: warning: dereferencing 'void *' pointer
 

 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1593: error: invalid operands to binary ==
 
 
 

 
 
 
At Local date and time: Thu Jul 02 15:55:43 2009
 
 
 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
 
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:844: error: request for member 'xEventListItem' in something not a structure or union
 
 
 

 
 
 

 
 
 
 make -f system.make program started...
 
 
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
 
 
make: *** [RTOSDemo/executable.elf] Error 1
 
 
 
Done!
 
 
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
powerpc-eabi-size RTOSDemo/executable.elf
 
 
 

 

 
 
 
 make -f system.make program started...
 
 
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
 
 

 
 
 
At Local date and time: Thu Jul 02 16:32:08 2009
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
 
 
  51878     372   87852  140102   22346 RTOSDemo/executable.elf
 

 

 

 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
 
Done writing Tab View settings to:
 

 
Xilinx EDK 11.2 Build EDK_LS3.47
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
 
Generating Block Diagram to Buffer
 
Generated Block Diagram SVG
 
At Local date and time: Thu Jul 02 17:37:11 2009
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  51910     372   87852  140134   22366 RTOSDemo/executable.elf
 

 

 
 make -f system.make download started...
 
*********************************************
 
*********************************************
 
Release 11.2 - iMPACT L.46 (nt)
 
Preference Table
 
StartupClock         Auto_Correction
 
KeepSVF              False
 
UseHighz             False
 
UserLevel            Novice
 
svfUseTime           false
 
AutoDetecting cable. Please wait.
 
Checking cable driver.
 
 Driver version: src=2301, dest=2301.
 
13:58:07, version = 900.
 
 Max current requested during enumeration is 300 mA.
 
write (count, cmdBuffer, dataBuffer) failed C0000004.
 
 Setting cable speed to 6 MHz.
 
Firmware version = 2301.
 
Firmware hex file version = 2401.
 
Downloaded firmware version = 2401.
 
 PLD version = 200Dh.
 
INFO:iMPACT:1777 -
 

 
----------------------------------------------------------------------
 
INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.
 
   Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...
 
----------------------------------------------------------------------
 
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
 

INFO:iMPACT:1777 -
 

 
----------------------------------------------------------------------
 
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
 
----------------------------------------------------------------------
 
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
 
----------------------------------------------------------------------
 
Elapsed time =      2 sec.
 
'5': Loading file 'implementation/download.bit' ...
 
   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
 
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
 
done.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
Validating chain...
 
5: Device Temperature: Current Reading:   42.99 C, Min. Reading:   37.58 C, Max.
 
5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.
 
5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.502 V, Max.
 
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
 
'5': Programming device...
 
done.
 
CRC error                                         :         0
 
DCM locked                                        :         1
 
End of startup signal from Startup block          :         1
 
status of GWE                                     :         1
 
value of MODE pin M0                              :         1
 
Value of MODE pin M2                              :         1
 
Value driver in from INIT pad                     :         1
 
Value of DONE pin                                 :         1
 
Decryptor error Signal                            :         0
 
startup_state[18] CFG startup state machine       :         0
 
startup_state[20] CFG startup state machine       :         1
 
SPI Flash Type[22] Select                         :         1
 
SPI Flash Type[24] Select                         :         1
 
CFG bus width auto detection result               :         0
 
BPI address wrap around error                     :         0
 
read back crc error                               :         0
 
 Match_cycle = 2.
 
Elapsed time =     11 sec.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
 
INFO:iMPACT - '5': Programing completed successfully.
 

 

 
 
 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
 
 
   text    data     bss     dec     hex filename
 
 
 
Done!
 
 
 
At Local date and time: Thu Jul 02 20:25:21 2009
 

 
 
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'xTaskCheckForTimeOut':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:71: error: (Each undeclared identifier is reported only once
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:77: error: 'pdTRUE' undeclared (first use in this function)
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: At top level:
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:83: warning: previous implicit declaration of 'vTaskSetTimeOutState' was here
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:97: error: 'xNumOfOverflows' undeclared (first use in this function)
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:109: warning: comparison is always true due to limited range of data type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:116: error: expected expression before 'xTimeOutType'
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:134: warning: incompatible implicit declaration of built-in function 'printf'
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:150: warning: incompatible implicit declaration of built-in function 'printf'
 
make: *** [RTOSDemo/executable.elf] Error 1
 

 
Done!
 
At Local date and time: Thu Jul 02 20:27:35 2009
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:53:19: error: conio.h: No such file or directory
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:113: warning: comparison is always true due to limited range of data type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:184: warning: incompatible implicit declaration of built-in function 'exit'
 
make: *** [RTOSDemo/executable.elf] Error 1
 

 
Done!
 
At Local date and time: Thu Jul 02 20:28:16 2009
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:113: warning: comparison is always true due to limited range of data type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:144: warning: incompatible implicit declaration of built-in function 'printf'
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:157: warning: incompatible implicit declaration of built-in function 'printf'
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:181: warning: incompatible implicit declaration of built-in function 'printf'
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:105: warning: return type of 'main' is not 'int'
 
/
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:71: multiple definition of `vTaskSetTimeOutState'
 
/cygdrive/c/devtools/Xilinx/11.1/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc/powerpc-eabi/4.1.1/../../../../powerpc-eabi/bin/ld: Warning: size of symbol `vTaskSetTimeOutState' changed from 68 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccwVIJA2.o to 72 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:77: multiple definition of `xTaskCheckForTimeOut'
 
/cygdrive/c/devtools/Xilinx/11.1/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc/powerpc-eabi/4.1.1/../../../../powerpc-eabi/bin/ld: Warning: size of symbol `xTaskCheckForTimeOut' changed from 388 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccwVIJA2.o to 276 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o
 
tasks.c:(.text+0x1798): undefined reference to `vApplicationStackOverflowHook'
 
/cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o: In function `main':
 
main.c:(.text+0x304): undefined reference to `getch'
 
make: *** [RTOSDemo/executable.elf] Error 1
 

 
Done!
 
At Local date and time: Thu Jul 02 20:31:20 2009
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:105: warning: return type of 'main' is not 'int'
 
/cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccZOTZW1.o: In function `vTaskSwitchContext':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1557: undefined reference to `vApplicationStackOverflowHook'
 
make: *** [RTOSDemo/executable.elf] Error 1
 

 
Done!
 
At Local date and time: Thu Jul 02 20:31:50 2009
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:123: warning: comparison is always true due to limited range of data type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  50578     368   87832  138778   21e1a RTOSDemo/executable.elf
 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:148: warning: incompatible implicit declaration of built-in function 'printf'
 

 
   text    data     bss     dec     hex filename
 

 
Done!
 
Done.
 
At Local date and time: Thu Jul 02 20:38:30 2009
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:123: warning: comparison is always true due to limited range of data type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  50706     368   87832  138906   21e9a RTOSDemo/executable.elf
 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:151: warning: incompatible implicit declaration of built-in function 'printf'
 

 
   text    data     bss     dec     hex filename
 

 
Done!
 
Done.
 
At Local date and time: Thu Jul 02 20:43:10 2009
 

 
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  50730     368   87840  138938   21eba RTOSDemo/executable.elf
 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  50694     368   87840  138902   21e96 RTOSDemo/executable.elf
 

 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  50730     368   87840  138938   21eba RTOSDemo/executable.elf
 

 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  50802     368   87832  139002   21efa RTOSDemo/executable.elf
 

 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  50846     368   87832  139046   21f26 RTOSDemo/executable.elf
 

 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
 
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  50866     368   87832  139066   21f3a RTOSDemo/executable.elf
 

 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D USE_DP_FPU -D GCC_PPC440 -mregnames
 
   text    data     bss     dec     hex filename
 

 
Done!
 
Done.
 
Done.
 
At Local date and time: Fri Jul 03 02:08:31 2009
 

 
Downloading Bitstream onto the target board
 
impact -batch etc/download.cmd
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
Name                 Setting
 
AutoSignature        False
 
ConcurrentMode       False
 
ConfigOnFailure      Stop
 
MessageLevel         Detailed
 
SpiByteSwap          Auto_Correction
 
Connecting to cable (Usb Port - USB21).
 
 Driver file xusb_xp2.sys found.
 
 Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS
 
 Cable PID = 0008.
 
Type = 0x0005.
 
 Setting cable speed to 6 MHz.
 
Firmware version = 2401.
 
Firmware hex file version = 2401.
 
 PLD version = 200Dh.
 
INFO:iMPACT:1777 -
 

 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
 
 
 
 
INFO:iMPACT:501 - '1': Added Device xccace successfully.
 
INFO:iMPACT:1777 -
 

 
----------------------------------------------------------------------
 
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
 
   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
 
----------------------------------------------------------------------
 
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
 
----------------------------------------------------------------------
 
Elapsed time =      1 sec.
 
'5': Loading file 'implementation/download.bit' ...
 
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
 
done.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
 
 
5: Device Temperature: Current Reading:   38.07 C, Min. Reading:   35.12 C, Max.
 
5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.
 
5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.502 V, Max.
 
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
 
'5': Programming device...
 
done.
 
CRC error                                         :         0
 
DCM locked                                        :         1
 
End of startup signal from Startup block          :         1
 
status of GWE                                     :         1
 
value of MODE pin M0                              :         1
 
Value of MODE pin M2                              :         1
 
Value driver in from INIT pad                     :         1
 
Value of DONE pin                                 :         1
 
Decryptor error Signal                            :         0
 
startup_state[18] CFG startup state machine       :         0
 
startup_state[20] CFG startup state machine       :         1
 
SPI Flash Type[22] Select                         :         1
 
 
 
CFG bus width auto detection result               :         0
 
BPI address wrap around error                     :         0
 
read back crc error                               :         0
 
 
 
 
 
----------------------------------------------------------------------
 
 
 
----------------------------------------------------------------------
 
 
 
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
 
 
 

 

 

 

 

 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
 
 
 

 
 
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
 
 
 
Generated Block Diagram SVG
 
At Local date and time: Fri Jul 03 18:19:28 2009
 

 
 
 
impact -batch etc/download.cmd
 
 
 
 
 
 
 
ConcurrentMode       False
 
 
 
 
 
 
 
Connecting to cable (Usb Port - USB21).
 
 Driver file xusb_xp2.sys found.
 
 Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS
 
 Cable PID = 0008.
 
Type = 0x0005.
 
 Setting cable speed to 6 MHz.
 
 
 
 
 
 PLD version = 200Dh.
 
INFO:iMPACT:1777 -
 

 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
 
INFO:iMPACT:1777 -
 
INFO:iMPACT:501 - '1': Added Device xccace successfully.
 
INFO:iMPACT:1777 -
 
 
 
----------------------------------------------------------------------
 
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
 
INFO:iMPACT:1777 -
 

 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
done.
 
Elapsed time =      0 sec.
 
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
 
 
 
UserID read from the bitstream file = 0xFFFFFFFF.
 
 
 
 
 
Boundary-scan chain validated successfully.
 
Reading:   74.99 C
 
Reading:   1.002 V
 
Reading:   2.505 V
 

 
 Match_cycle = 2.
 
 
 
Decryptor security set                            :         0
 
DCI matched                                       :         1
 
status of GTS_CFG_B                               :         1
 
status of GHIGH                                   :         1
 
value of MODE pin M1                              :         0
 
Internal signal indicates when housecleaning is completed:         1
 
Internal signal indicates that chip is configured :         1
 
 
 
 
 
startup_state[19] CFG startup state machine       :         0
 
E-fuse program voltage available                  :         0
 
 
 
CFG bus width auto detection result               :         0
 
 
 
IPROG pulsed                                      :         0
 
 
 
'5': Programmed successfully.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
 
 
 
 
INFO:iMPACT - '5': Checking done pin....done.
 

 
 
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
 
 
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
 
At Local date and time: Fri Jul 03 18:20:05 2009
 
 
 
 
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  44758     372   87852  132982   20776 RTOSDemo/executable.elf


 

start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"

WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!

 

 

 

 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
 
Done writing Tab View settings to:
 

 

 
 
 

 
 
 
 make -f system.make hwclean started...
 
rm -f implementation/system.ngc
 
rm -f __xps/ise/_xmsgs/platgen.xmsgs
 
rm -f implementation/system.bit
 
rm -f implementation/system_bd.bmm
 
rm -f __xps/system_routed
 
rm -rf xst.srp system.srp
 

 
Done!
 
At Local date and time: Sun Jul 05 09:37:10 2009
 

 
rm -f libgen.log
 
rm -f RTOSDemo/executable.elf
 

 

 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
 
Done writing Tab View settings to:
 

 
Line No.	Rev	Author	Line
1	586	jeremybenn	`No logfile was found.`
2
3			`WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!`
4
5			`WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!`
6
7			`Generating Block Diagram to Buffer`
8
9			`Generated Block Diagram SVG`
10
11			`The project file (XMP) has changed on disk.`
12
13			`WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!`
14
15			`WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!`
16
17			`WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!`
18
19			`WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!`
20
21			`At Local date and time: Tue Jun 30 18:36:00 2009`
22			`make -f system.make netlistclean started...`
23
24			`rm -f implementation/system.ngc`
25			`rm -f platgen.log`
26			`rm -f __xps/ise/_xmsgs/platgen.xmsgs`
27			`rm -f implementation/system.bmm`
28
29
30			`Done!`
31
32			`At Local date and time: Tue Jun 30 18:36:05 2009`
33			`make -f system.make bitsclean started...`
34
35			`rm -f implementation/system.bit`
36			`rm -f implementation/system.ncd`
37			`rm -f implementation/system_bd.bmm`
38			`rm -f implementation/system_map.ncd`
39			`rm -f __xps/system_routed`
40
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