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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC440_DP_FPU_Xilinx_Virtex5_GCC/] [system.log] - Blame information for rev 590

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Line No. Rev Author Line
1 586 jeremybenn
No logfile was found.
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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
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WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
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Generating Block Diagram to Buffer
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Generated Block Diagram SVG
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The project file (XMP) has changed on disk.
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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
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WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
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WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
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At Local date and time: Tue Jun 30 18:36:00 2009
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 make -f system.make netlistclean started...
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rm -f implementation/system.ngc
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rm -f platgen.log
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rm -f __xps/ise/_xmsgs/platgen.xmsgs
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rm -f implementation/system.bmm
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30
Done!
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32
At Local date and time: Tue Jun 30 18:36:05 2009
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 make -f system.make bitsclean started...
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35
rm -f implementation/system.bit
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rm -f implementation/system.ncd
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rm -f implementation/system_bd.bmm
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rm -f implementation/system_map.ncd
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rm -f __xps/system_routed
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41
 
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Done!
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At Local date and time: Tue Jun 30 18:36:10 2009
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 make -f system.make hwclean started...
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47
rm -f implementation/system.ngc
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rm -f platgen.log
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rm -f __xps/ise/_xmsgs/platgen.xmsgs
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rm -f implementation/system.bmm
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rm -f implementation/system.bit
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rm -f implementation/system.ncd
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rm -f implementation/system_bd.bmm
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rm -f implementation/system_map.ncd
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rm -f __xps/system_routed
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rm -rf implementation synthesis xst hdl
57
rm -rf xst.srp system.srp
58
rm -f __xps/ise/_xmsgs/bitinit.xmsgs
59
 
60
 
61
Done!
62
 
63
At Local date and time: Tue Jun 30 18:36:16 2009
64
 make -f system.make libsclean started...
65
 
66
rm -rf ppc440_0/
67
rm -f libgen.log
68
rm -f __xps/ise/_xmsgs/libgen.xmsgs
69
 
70
 
71
Done!
72
 
73
At Local date and time: Tue Jun 30 18:36:20 2009
74
 make -f system.make programclean started...
75
 
76
rm -f RTOSDemo/executable.elf
77
 
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79
Done!
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81
At Local date and time: Tue Jun 30 18:36:25 2009
82
 make -f system.make swclean started...
83
 
84
rm -rf ppc440_0/
85
rm -f libgen.log
86
rm -f __xps/ise/_xmsgs/libgen.xmsgs
87
rm -f RTOSDemo/executable.elf
88
 
89
 
90
Done!
91
 
92
Writing filter settings....
93
 
94
Done writing filter settings to:
95
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
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97
Done writing Tab View settings to:
98
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
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100
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
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102
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
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104
Generating Block Diagram to Buffer
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106
Generated Block Diagram SVG
107
 
108
At Local date and time: Tue Jun 30 22:00:27 2009
109
 make -f system.make bits started...
110
 
111
****************************************************
112
Creating system netlist for hardware specification..
113
****************************************************
114
platgen -p xc5vfx70tff1136-1 -lang vhdl   -msg __xps/ise/xmsgprops.lst system.mhs
115
 
116
 
117
 (nt)
118
 
119
120
 
121
Command Line: platgen -p xc5vfx70tff1136-1 -lang vhdl -msg
122
 
123
 
124
 
125
 
126
 
127
128
 
129
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
130
 
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133
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m
134
 
135
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
136
 
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   hs line 253 - deprecated core for architecture 'virtex5fx'!
138
 
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142
 
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144
 
145
146
 
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Address Map for Processor ppc440_0
148
 
149
  (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC
150
 
151
  (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0
152
 
153
  (0x81440000-0x8144ffff) LEDs_8Bit     plb_v46_0
154
 
155
  (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0
156
 
157
  (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0
158
 
159
  (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0
160
 
161
  (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0
162
 
163
  (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0
164
 
165
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
166
 
167
 
168
 
169
Computing clock values...
170
 
171
 
172
 
173
   through the clock generator IP.
174
 
175
 
176
 
177
   performed for IPs connected to that clock port, unless they are connected
178
 
179
180
 
181
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
182
 
183
   C_PLBV46_NUM_MASTERS value to 1
184
 
185
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
186
 
187
   C_PLBV46_NUM_SLAVES value to 12
188
 
189
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
190
 
191
   C_PLBV46_MID_WIDTH value to 1
192
 
193
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
194
 
195
   value to 128
196
 
197
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
198
 
199
   PARAMETER C_SPLB_DWIDTH value to 128
200
 
201
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
202
 
203
   PARAMETER C_SPLB_NUM_MASTERS value to 1
204
 
205
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
206
 
207
   PARAMETER C_SPLB_SMALLEST_MASTER value to 128
208
 
209
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
210
 
211
   value to 0x2000
212
 
213
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
214
 
215
   C_PORT_DWIDTH value to 64
216
 
217
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
218
 
219
   value to 8
220
 
221
 
222
 
223
   C_SPLB_DWIDTH value to 128
224
 
225
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
226
 
227
   value to 128
228
 
229
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
230
 
231
   value to 128
232
 
233
 
234
 
235
   value to 128
236
 
237
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
238
 
239
   value to 128
240
 
241
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
242
 
243
 
244
 
245
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
246
 
247
   C_SPLB_DWIDTH value to 128
248
 
249
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
250
 
251
   C_SPLB_SMALLEST_MASTER value to 128
252
 
253
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
254
 
255
   C_MPLB_DWIDTH value to 128
256
 
257
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
258
 
259
   C_MPLB_SMALLEST_SLAVE value to 128
260
 
261
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
262
 
263
   C_SPLB_MID_WIDTH value to 1
264
 
265
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
266
 
267
   C_SPLB_NUM_MASTERS value to 1
268
 
269
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
270
 
271
   C_SPLB_SMALLEST_MASTER value to 128
272
 
273
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
274
 
275
   C_SPLB_DWIDTH value to 128
276
 
277
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
278
 
279
   C_PLBV46_NUM_MASTERS value to 1
280
 
281
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
282
 
283
   C_PLBV46_NUM_SLAVES value to 1
284
 
285
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
286
 
287
   C_PLBV46_MID_WIDTH value to 1
288
 
289
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
290
 
291
   value to 128
292
 
293
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
294
 
295
   PARAMETER C_SPLB_DWIDTH value to 128
296
 
297
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
298
 
299
   C_SPLB_DWIDTH value to 128
300
 
301
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
302
 
303
   C_SPLB_MID_WIDTH value to 1
304
 
305
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
306
 
307
   C_SPLB_NUM_MASTERS value to 1
308
 
309
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
310
 
311
   value to 128
312
 
313
Checking platform address map ...
314
 
315
Checking platform configuration ...
316
 
317
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m
318
 
319
   performance.
320
 
321
   The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs
322
 
323
   operation.
324
 
325
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
326
 
327
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
328
 
329
line 290 - 1 master(s) : 1 slave(s)
330
 
331
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
332
 
333
334
 
335
WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
336
 
337
   hs line 461 - floating connection!
338
 
339
Performing Clock DRCs...
340
 
341
Performing Reset DRCs...
342
 
343
Overriding system level properties...
344
 
345
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
346
 
347
   C_PPC440MC_ADDR_BASE value to 0x00000000
348
 
349
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
350
 
351
   C_PPC440MC_ADDR_HIGH value to 0x0fffffff
352
 
353
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_0
354
 
355
   C_NUM_PPC_USED value to 1
356
 
357
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
358
 
359
   value to 0b00000000000000000000000000000001
360
 
361
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
362
 
363
   value to 0b00000000000000000000000000000001
364
 
365
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
366
 
367
   value to 0b00000000000000000000000000000000
368
 
369
Running system level update procedures...
370
 
371
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
372
 
373
Running system level DRCs...
374
 
375
Performing System level DRCs on properties...
376
 
377
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
378
 
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Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
380
 
381
implementation/pcie_bridge_wrapper/pcie_bridge_wrapper.ucf.
382
 
383
384
 
385
386
 
387
implementation/ethernet_mac_wrapper/ethernet_mac_wrapper.ucf.
388
 
389
390
 
391
392
 
393
implementation/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ucf.
394
 
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396
 
397
398
 
399
Modify defaults ...
400
 
401
Creating stub ...
402
 
403
Processing licensed instances ...
404
 
405
406
 
407
408
 
409
IPNAME:plbv46_pcie INSTANCE:pcie_bridge -
410
 
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line 253 - Copying (BBD-specified) netlist files.
412
 
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C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
414
 
415
IPNAME:apu_fpu_virtex5 INSTANCE:ppc440_0_apu_fpu_virtex5 -
416
 
417
line 401 - Copying (BBD-specified) netlist files.
418
 
419
Managing cache ...
420
 
421
Elaborating instances ...
422
 
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C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
424
 
425
426
 
427
428
 
429
Completion time: 0.00 seconds
430
 
431
Constructing platform-level connectivity ...
432
 
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443
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
444
 
445
INSTANCE:ppc440_0 -
446
 
447
line 78 - Running XST synthesis
448
 
449
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
450
 
451
INSTANCE:xps_bram_if_cntlr_1 -
452
 
453
line 118 - Running XST synthesis
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455
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
456
 
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INSTANCE:rs232_uart_1 -
458
 
459
line 138 - Running XST synthesis
460
 
461
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
462
 
463
INSTANCE:leds_positions -
464
 
465
line 168 - Running XST synthesis
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C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
468
 
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INSTANCE:dip_switches_8bit -
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line 196 - Running XST synthesis
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473
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
474
 
475
INSTANCE:sram -
476
 
477
line 223 - Running XST synthesis
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479
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
480
 
481
INSTANCE:ppc440_0_splb0 -
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483
line 290 - Running XST synthesis
484
 
485
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
486
 
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INSTANCE:ddr2_sdram -
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489
line 317 - Running XST synthesis
490
 
491
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
492
 
493
INSTANCE:ppc440_0_fcb_v20 -
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495
line 394 - Running XST synthesis
496
 
497
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
498
 
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INSTANCE:clock_generator_0 -
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501
line 407 - Running XST synthesis
502
 
503
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
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INSTANCE:proc_sys_reset_0 -
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507
line 452 - Running XST synthesis
508
 
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515
line 78 - Running NGCBUILD
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 with local file
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521
xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..
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525
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa
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531
-------------------------------
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533
  No Partitions were found in this design.
534
 
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-------------------------------
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NGCBUILD Design Results Summary:
538
 
539
  Number of warnings:   0
540
 
541
Writing NGC file "../ppc440_0_wrapper.ngc" ...
542
 
543
Total CPU time to NGCBUILD completion:   6 sec
544
 
545
Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...
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547
NGCBUILD done.
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C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
550
 
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Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
556
 
557
../rs232_uart_1_wrapper.ngc
558
 
559
Reading NGO file
560
 
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562
 
563
Partition Implementation Status
564
 
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570
 
571
  Number of errors:     0
572
 
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575
Total REAL time to NGCBUILD completion:  2 sec
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581
IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -
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583
line 253 - Running NGCBUILD
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 with local file
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xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..
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"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa
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Executing edif2ngd -noa
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597
tion\pcie_bridge_wrapper_fifo_generator_v4_3.edn"
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Release 11.2 - edif2ngd L.46 (nt)
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INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)
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PMSPEC -- Overriding Xilinx file 
604
 
605
Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...
606
 
607
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa
608
 
609
Loading design module
610
 
611
Loading design module
612
 
613
tion\pcie_bridge_wrapper/dpram_70_512.ngc"...
614
 
615
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa
616
 
617
618
 
619
620
 
621
 
622
 
623
  No Partitions were found in this design.
624
 
625
 
626
 
627
NGCBUILD Design Results Summary:
628
 
629
 
630
 
631
Writing NGC file "../pcie_bridge_wrapper.ngc" ...
632
 
633
 
634
 
635
Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...
636
 
637
 
638
 
639
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
640
 
641
 
642
 
643
644
 
645
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
646
 
647
ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc
648
 
649
 
650
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa
651
 
652
 
653
 
654
 
655
 
656
 
657
 
658
 
659
 
660
Writing module to "ethernetlite_v1_01_b_dmem_v2.ngo"...
661
 
662
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\implementa
663
 
664
 
665
Applying constraints in "ethernet_mac_wrapper.ucf" to the design...
666
 
667
 
668
 
669
 
670
 
671
 
672
 
673
 
674
 
675
  Number of errors:     0
676
 
677
678
 
679
 
680
Total CPU time to NGCBUILD completion:   6 sec
681
 
682
 
683
 
684
 
685
 
686
 
687
 
688
 
689
 
690
 
691
 
692
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
693
 
694
 
695
 
696
Reading NGO file
697
 
698
 
699
 
700
Applying constraints in "ddr2_sdram_wrapper.ucf" to the design...
701
 
702
Partition Implementation Status
703
 
704
 
705
 
706
707
 
708
 
709
 
710
  Number of errors:     0
711
 
712
713
 
714
Total REAL time to NGCBUILD completion:  7 sec
715
 
716
717
 
718
719
 
720
IPNAME:ppc440_0_apu_fpu_virtex5_wrapper INSTANCE:ppc440_0_apu_fpu_virtex5 -
721
 
722
line 401 - Running NGCBUILD
723
 
724
 with local file
725
 
726
727
 
728
xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_apu_fpu_virtex5_wrapper.ucf -sd
729
 
730
 
731
 
732
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa
733
 
734
 
735
 
736
tion\ppc440_0_apu_fpu_virtex5_wrapper/apu_fpu_dp_lo.ngc"...
737
 
738
Applying constraints in "ppc440_0_apu_fpu_virtex5_wrapper.ucf" to the design...
739
 
740
Partition Implementation Status
741
 
742
743
 
744
 
745
 
746
747
 
748
 
749
 
750
751
 
752
Total REAL time to NGCBUILD completion:  7 sec
753
 
754
 
755
 
756
757
 
758
IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 -
759
 
760
 
761
 
762
 with local file
763
 
764
 
765
 
766
xc5vfx70tff1136-1 -intstyle silent -sd .. xps_intc_0_wrapper.ngc
767
 
768
 
769
 
770
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa
771
 
772
 
773
 
774
-------------------------------
775
 
776
 
777
 
778
-------------------------------
779
 
780
NGCBUILD Design Results Summary:
781
 
782
  Number of warnings:   0
783
 
784
Writing NGC file "../xps_intc_0_wrapper.ngc" ...
785
 
786
Total CPU time to NGCBUILD completion:   2 sec
787
 
788
Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...
789
 
790
NGCBUILD done.
791
 
792
Rebuilding cache ...
793
 
794
Total run time: 1120.00 seconds
795
 
796
bash -c "cd synthesis; ./synthesis.sh"
797
 
798
Running XST synthesis ...
799
 
800
Release 11.2 - ngcbuild L.46 (nt)
801
 
802
Overriding Xilinx file  with local file
803
 
804
805
 
806
./system.ngc ../implementation/system.ngc -sd ../implementation -i -ise
807
 
808
809
 
810
"c:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/synthesis/
811
 
812
Loading design module "../implementation/ppc440_0_wrapper.ngc"...
813
 
814
Loading design module "../implementation/xps_bram_if_cntlr_1_wrapper.ngc"...
815
 
816
"../implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc"...
817
 
818
Loading design module "../implementation/leds_8bit_wrapper.ngc"...
819
 
820
Loading design module "../implementation/push_buttons_5bit_wrapper.ngc"...
821
 
822
Loading design module "../implementation/iic_eeprom_wrapper.ngc"...
823
 
824
Loading design module "../implementation/pcie_bridge_wrapper.ngc"...
825
 
826
Loading design module "../implementation/ethernet_mac_wrapper.ngc"...
827
 
828
Loading design module "../implementation/sysace_compactflash_wrapper.ngc"...
829
 
830
Loading design module
831
 
832
Loading design module "../implementation/clock_generator_0_wrapper.ngc"...
833
 
834
Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...
835
 
836
837
 
838
-------------------------------
839
 
840
  No Partitions were found in this design.
841
 
842
-------------------------------
843
 
844
NGCBUILD Design Results Summary:
845
 
846
  Number of warnings:   0
847
 
848
Writing NGC file "../implementation/system.ngc" ...
849
 
850
Total CPU time to NGCBUILD completion:   11 sec
851
 
852
Writing NGCBUILD log file "../implementation/system.blc"...
853
 
854
NGCBUILD done.
855
 
856
Running Xilinx Implementation tools..
857
 
858
xflow -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise ../__xps/ise/system.ise system.ngc
859
 
860
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
861
 
862
../__xps/ise/system.ise system.ngc
863
 
864
 with local file
865
 
866
.... Copying flowfile c:/devtools/Xilinx/11.1/ISE/xilinx/data/fpga.flw into
867
 
868
C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementat
869
 
870
871
 
872
C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementat
873
 
874
Using Option File(s):
875
 
876
tion/xflow.opt
877
 
878
Creating Script File ...
879
 
880
#----------------------------------------------#
881
 
882
# ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm
883
 
884
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/implementa
885
 
886
#----------------------------------------------#
887
 
888
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
889
 
890
 with local file
891
 
892
893
 
894
timestamp -bm system.bmm
895
 
896
ion/system.ngc -uc system.ucf system.ngd
897
 
898
Reading NGO file
899
 
900
tion/system.ngc" ...
901
 
902
Done.
903
 
904
Applying constraints in "system.ucf" to the design...
905
 
906
   'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_
907
 
908
   'VIRTEX5' to correct post-ngdbuild and timing simulation for this primitive.
909
 
910
   should be changed in this same manner in the source netlist or constraint
911
 
912
Resolving constraint associations...
913
 
914
WARNING:ConstraintSystem:3 - Constraint 
915
 
916
 
917
 
918
   found.
919
 
920
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
921
 
922
   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
923
 
924
   PLL_ADV output(s):
925
 
926
   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *
927
 
928
929
 
930
   'TS_sys_clk_pin', was traced into PLL_ADV instance
931
 
932
 
933
 
934
   CLKOUT1: 
935
 
936
   1.25 HIGH 50%>
937
 
938
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
939
 
940
 
941
 
942
   PLL_ADV output(s):
943
 
944
   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *
945
 
946
947
 
948
 
949
 
950
   The following new TNM groups and period specifications were generated at the
951
 
952
 
953
 
954
   2 HIGH 50%>
955
 
956
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
957
 
958
 
959
 
960
   PLL_ADV output(s):
961
 
962
 
963
 
964
965
 
966
 
967
 
968
Processing BMM file ...
969
 
970
WARNING:NgdBuild:1212 - User specified non-default attribute value
971
 
972
   "clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".
973
 
974
 
975
 
976
Checking expanded design ...
977
 
978
   'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_
979
 
980
   has unconnected output pin
981
 
982
 
983
 
984
WARNING:NgdBuild:443 - SFF primitive
985
 
986
 
987
 
988
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
989
 
990
   has unconnected output pin
991
 
992
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
993
 
994
   has unconnected output pin
995
 
996
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
997
 
998
   RE_I' has unconnected output pin
999
 
1000
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1001
 
1002
 
1003
 
1004
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1005
 
1006
   ' has unconnected output pin
1007
 
1008
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1009
 
1010
 
1011
 
1012
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1013
 
1014
   ' has unconnected output pin
1015
 
1016
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1017
 
1018
 
1019
 
1020
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1021
 
1022
   has unconnected output pin
1023
 
1024
 
1025
 
1026
   ' has unconnected output pin
1027
 
1028
 
1029
 
1030
WARNING:NgdBuild:443 - SFF primitive
1031
 
1032
 
1033
 
1034
WARNING:NgdBuild:443 - SFF primitive
1035
 
1036
   URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has
1037
 
1038
WARNING:NgdBuild:443 - SFF primitive
1039
 
1040
 
1041
 
1042
WARNING:NgdBuild:443 - SFF primitive
1043
 
1044
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
1045
 
1046
WARNING:NgdBuild:443 - SFF primitive
1047
 
1048
 
1049
 
1050
WARNING:NgdBuild:443 - SFF primitive
1051
 
1052
 
1053
 
1054
WARNING:NgdBuild:443 - SFF primitive
1055
 
1056
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B
1057
 
1058
WARNING:NgdBuild:443 - SFF primitive
1059
 
1060
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B
1061
 
1062
WARNING:NgdBuild:443 - SFF primitive
1063
 
1064
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B
1065
 
1066
WARNING:NgdBuild:443 - SFF primitive
1067
 
1068
 
1069
 
1070
WARNING:NgdBuild:443 - SFF primitive
1071
 
1072
   _H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin
1073
 
1074
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S
1075
 
1076
 
1077
 
1078
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected
1079
 
1080
WARNING:NgdBuild:443 - SFF primitive
1081
 
1082
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected
1083
 
1084
WARNING:NgdBuild:443 - SFF primitive
1085
 
1086
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected
1087
 
1088
WARNING:NgdBuild:443 - SFF primitive
1089
 
1090
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected
1091
 
1092
WARNING:NgdBuild:443 - SFF primitive
1093
 
1094
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected
1095
 
1096
WARNING:NgdBuild:443 - SFF primitive
1097
 
1098
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected
1099
 
1100
WARNING:NgdBuild:443 - SFF primitive
1101
 
1102
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected
1103
 
1104
WARNING:NgdBuild:443 - SFF primitive
1105
 
1106
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected
1107
 
1108
WARNING:NgdBuild:443 - SFF primitive
1109
 
1110
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected
1111
 
1112
WARNING:NgdBuild:443 - SFF primitive
1113
 
1114
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected
1115
 
1116
WARNING:NgdBuild:443 - SFF primitive
1117
 
1118
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected
1119
 
1120
WARNING:NgdBuild:443 - SFF primitive
1121
 
1122
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected
1123
 
1124
WARNING:NgdBuild:443 - SFF primitive
1125
 
1126
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected
1127
 
1128
 
1129
 
1130
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected
1131
 
1132
 
1133
 
1134
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected
1135
 
1136
WARNING:NgdBuild:443 - SFF primitive
1137
 
1138
 
1139
 
1140
WARNING:NgdBuild:443 - SFF primitive
1141
 
1142
 
1143
 
1144
WARNING:NgdBuild:443 - SFF primitive
1145
 
1146
 
1147
 
1148
WARNING:NgdBuild:443 - SFF primitive
1149
 
1150
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected
1151
 
1152
WARNING:NgdBuild:443 - SFF primitive
1153
 
1154
 
1155
 
1156
WARNING:NgdBuild:443 - SFF primitive
1157
 
1158
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected
1159
 
1160
WARNING:NgdBuild:443 - SFF primitive
1161
 
1162
 
1163
 
1164
WARNING:NgdBuild:443 - SFF primitive
1165
 
1166
 
1167
 
1168
WARNING:NgdBuild:443 - SFF primitive
1169
 
1170
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_WRCE_REG' has unconnected
1171
 
1172
WARNING:NgdBuild:443 - SFF primitive
1173
 
1174
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_CE_REG' has unconnected
1175
 
1176
WARNING:NgdBuild:443 - SFF primitive
1177
 
1178
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected
1179
 
1180
WARNING:NgdBuild:443 - SFF primitive
1181
 
1182
 
1183
 
1184
WARNING:NgdBuild:443 - SFF primitive
1185
 
1186
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected
1187
 
1188
WARNING:NgdBuild:443 - SFF primitive
1189
 
1190
 
1191
 
1192
WARNING:NgdBuild:443 - SFF primitive
1193
 
1194
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_WRCE_REG' has unconnected
1195
 
1196
WARNING:NgdBuild:443 - SFF primitive
1197
 
1198
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected
1199
 
1200
WARNING:NgdBuild:443 - SFF primitive
1201
 
1202
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has
1203
 
1204
WARNING:NgdBuild:443 - SFF primitive
1205
 
1206
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has
1207
 
1208
WARNING:NgdBuild:443 - SFF primitive
1209
 
1210
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_CE_REG' has unconnected
1211
 
1212
WARNING:NgdBuild:443 - SFF primitive
1213
 
1214
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has
1215
 
1216
WARNING:NgdBuild:443 - SFF primitive
1217
 
1218
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_WRCE_REG' has
1219
 
1220
WARNING:NgdBuild:443 - SFF primitive
1221
 
1222
 
1223
 
1224
WARNING:NgdBuild:443 - SFF primitive
1225
 
1226
 
1227
 
1228
WARNING:NgdBuild:443 - SFF primitive
1229
 
1230
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has
1231
 
1232
 
1233
 
1234
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected
1235
 
1236
 
1237
 
1238
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has
1239
 
1240
 
1241
 
1242
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has
1243
 
1244
WARNING:NgdBuild:443 - SFF primitive
1245
 
1246
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected
1247
 
1248
 
1249
 
1250
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has
1251
 
1252
WARNING:NgdBuild:443 - SFF primitive
1253
 
1254
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has
1255
 
1256
 
1257
 
1258
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected
1259
 
1260
 
1261
 
1262
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has
1263
 
1264
WARNING:NgdBuild:443 - SFF primitive
1265
 
1266
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has
1267
 
1268
WARNING:NgdBuild:443 - SFF primitive
1269
 
1270
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected
1271
 
1272
WARNING:NgdBuild:443 - SFF primitive
1273
 
1274
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has
1275
 
1276
 
1277
 
1278
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has
1279
 
1280
WARNING:NgdBuild:443 - SFF primitive
1281
 
1282
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected
1283
 
1284
 
1285
 
1286
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has
1287
 
1288
WARNING:NgdBuild:443 - SFF primitive
1289
 
1290
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has
1291
 
1292
 
1293
 
1294
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected
1295
 
1296
 
1297
 
1298
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has
1299
 
1300
WARNING:NgdBuild:443 - SFF primitive
1301
 
1302
 
1303
 
1304
WARNING:NgdBuild:443 - SFF primitive
1305
 
1306
 
1307
 
1308
WARNING:NgdBuild:443 - SFF primitive
1309
 
1310
 
1311
 
1312
WARNING:NgdBuild:443 - SFF primitive
1313
 
1314
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has
1315
 
1316
WARNING:NgdBuild:443 - SFF primitive
1317
 
1318
 
1319
 
1320
WARNING:NgdBuild:443 - SFF primitive
1321
 
1322
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has
1323
 
1324
WARNING:NgdBuild:443 - SFF primitive
1325
 
1326
 
1327
 
1328
WARNING:NgdBuild:443 - SFF primitive
1329
 
1330
 
1331
 
1332
WARNING:NgdBuild:443 - SFF primitive
1333
 
1334
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has
1335
 
1336
WARNING:NgdBuild:443 - SFF primitive
1337
 
1338
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has
1339
 
1340
WARNING:NgdBuild:443 - SFF primitive
1341
 
1342
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected
1343
 
1344
WARNING:NgdBuild:443 - SFF primitive
1345
 
1346
 
1347
 
1348
WARNING:NgdBuild:443 - SFF primitive
1349
 
1350
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_WRCE_REG' has
1351
 
1352
WARNING:NgdBuild:443 - SFF primitive
1353
 
1354
 
1355
 
1356
WARNING:NgdBuild:443 - SFF primitive
1357
 
1358
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has
1359
 
1360
WARNING:NgdBuild:443 - SFF primitive
1361
 
1362
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_WRCE_REG' has
1363
 
1364
WARNING:NgdBuild:443 - SFF primitive
1365
 
1366
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected
1367
 
1368
 
1369
 
1370
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_RDCE_REG' has
1371
 
1372
 
1373
 
1374
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_WRCE_REG' has
1375
 
1376
WARNING:NgdBuild:443 - SFF primitive
1377
 
1378
 
1379
 
1380
WARNING:NgdBuild:443 - SFF primitive
1381
 
1382
 
1383
 
1384
WARNING:NgdBuild:443 - SFF primitive
1385
 
1386
 
1387
 
1388
WARNING:NgdBuild:443 - SFF primitive
1389
 
1390
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_CE_REG' has unconnected
1391
 
1392
WARNING:NgdBuild:443 - SFF primitive
1393
 
1394
 
1395
 
1396
WARNING:NgdBuild:443 - SFF primitive
1397
 
1398
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_WRCE_REG' has
1399
 
1400
WARNING:NgdBuild:443 - SFF primitive
1401
 
1402
 
1403
 
1404
WARNING:NgdBuild:443 - SFF primitive
1405
 
1406
 
1407
 
1408
WARNING:NgdBuild:443 - SFF primitive
1409
 
1410
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has
1411
 
1412
WARNING:NgdBuild:443 - SFF primitive
1413
 
1414
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected
1415
 
1416
WARNING:NgdBuild:443 - SFF primitive
1417
 
1418
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has
1419
 
1420
WARNING:NgdBuild:443 - SFF primitive
1421
 
1422
 
1423
 
1424
WARNING:NgdBuild:443 - SFF primitive
1425
 
1426
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected
1427
 
1428
WARNING:NgdBuild:443 - SFF primitive
1429
 
1430
 
1431
 
1432
WARNING:NgdBuild:443 - SFF primitive
1433
 
1434
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_WRCE_REG' has
1435
 
1436
WARNING:NgdBuild:443 - SFF primitive
1437
 
1438
 
1439
 
1440
WARNING:NgdBuild:443 - SFF primitive
1441
 
1442
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has
1443
 
1444
 
1445
 
1446
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has
1447
 
1448
 
1449
 
1450
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected
1451
 
1452
 
1453
 
1454
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has
1455
 
1456
WARNING:NgdBuild:443 - SFF primitive
1457
 
1458
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has
1459
 
1460
 
1461
 
1462
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected
1463
 
1464
WARNING:NgdBuild:443 - SFF primitive
1465
 
1466
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected
1467
 
1468
 
1469
 
1470
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected
1471
 
1472
 
1473
 
1474
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected
1475
 
1476
 
1477
 
1478
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected
1479
 
1480
 
1481
 
1482
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected
1483
 
1484
WARNING:NgdBuild:443 - SFF primitive
1485
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1486
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected
1487
   output pin
1488
WARNING:NgdBuild:443 - SFF primitive
1489
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1490
 
1491
   output pin
1492
 
1493
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1494
 
1495
   output pin
1496
 
1497
 
1498
 
1499
   output pin
1500
 
1501
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1502
 
1503
   output pin
1504
 
1505
 
1506
 
1507
   output pin
1508
 
1509
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1510
 
1511
   output pin
1512
 
1513
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1514
 
1515
   unconnected output pin
1516
 
1517
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1518
 
1519
   unconnected output pin
1520
 
1521
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1522
 
1523
   output pin
1524
 
1525
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1526
 
1527
   unconnected output pin
1528
 
1529
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1530
 
1531
   unconnected output pin
1532
 
1533
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1534
 
1535
   output pin
1536
 
1537
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1538
 
1539
   unconnected output pin
1540
 
1541
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1542
 
1543
   unconnected output pin
1544
 
1545
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1546
 
1547
   output pin
1548
 
1549
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1550
 
1551
   unconnected output pin
1552
 
1553
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1554
 
1555
   unconnected output pin
1556
 
1557
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1558
 
1559
   output pin
1560
 
1561
 
1562
 
1563
   unconnected output pin
1564
 
1565
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1566
 
1567
 
1568
 
1569
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1570
 
1571
 
1572
 
1573
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1574
 
1575
 
1576
 
1577
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1578
 
1579
   unconnected output pin
1580
 
1581
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1582
 
1583
 
1584
 
1585
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1586
 
1587
   unconnected output pin
1588
 
1589
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1590
 
1591
 
1592
 
1593
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1594
 
1595
 
1596
 
1597
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1598
 
1599
   unconnected output pin
1600
WARNING:NgdBuild:443 - SFF primitive
1601
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1602
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has
1603
   unconnected output pin
1604
 
1605
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1606
 
1607
   output pin
1608
 
1609
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1610
 
1611
   unconnected output pin
1612
 
1613
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1614
 
1615
   unconnected output pin
1616
 
1617
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1618
 
1619
   output pin
1620
 
1621
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1622
 
1623
   unconnected output pin
1624
 
1625
 
1626
 
1627
   unconnected output pin
1628
 
1629
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1630
 
1631
   output pin
1632
 
1633
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1634
 
1635
   unconnected output pin
1636
 
1637
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1638
 
1639
 
1640
 
1641
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1642
 
1643
 
1644
 
1645
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1646
 
1647
   unconnected output pin
1648
 
1649
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1650
 
1651
   unconnected output pin
1652
 
1653
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1654
 
1655
   output pin
1656
 
1657
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1658
 
1659
   output pin
1660
 
1661
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1662
 
1663
   output pin
1664
 
1665
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1666
 
1667
   output pin
1668
 
1669
 
1670
 
1671
   output pin
1672
 
1673
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1674
 
1675
   output pin
1676
 
1677
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1678
 
1679
 
1680
 
1681
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1682
 
1683
   unconnected output pin
1684
 
1685
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1686
 
1687
   output pin
1688
 
1689
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1690
 
1691
 
1692
 
1693
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1694
 
1695
   unconnected output pin
1696
 
1697
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1698
 
1699
   output pin
1700
 
1701
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1702
 
1703
   unconnected output pin
1704
 
1705
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1706
 
1707
   unconnected output pin
1708
 
1709
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1710
 
1711
   output pin
1712
 
1713
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1714
 
1715
   unconnected output pin
1716
 
1717
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1718
 
1719
   unconnected output pin
1720
 
1721
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1722
 
1723
 
1724
 
1725
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1726
 
1727
   unconnected output pin
1728
 
1729
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1730
 
1731
   unconnected output pin
1732
 
1733
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1734
 
1735
   unconnected output pin
1736
 
1737
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1738
 
1739
   unconnected output pin
1740
 
1741
 
1742
 
1743
   unconnected output pin
1744
 
1745
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1746
 
1747
   unconnected output pin
1748
 
1749
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1750
 
1751
   unconnected output pin
1752
 
1753
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1754
 
1755
   unconnected output pin
1756
 
1757
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1758
 
1759
 
1760
 
1761
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1762
 
1763
   unconnected output pin
1764
 
1765
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1766
 
1767
   unconnected output pin
1768
 
1769
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1770
 
1771
   unconnected output pin
1772
 
1773
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1774
 
1775
   unconnected output pin
1776
 
1777
 
1778
 
1779
   unconnected output pin
1780
 
1781
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1782
 
1783
   unconnected output pin
1784
 
1785
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1786
 
1787
   unconnected output pin
1788
 
1789
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1790
 
1791
   unconnected output pin
1792
 
1793
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1794
 
1795
 
1796
 
1797
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1798
 
1799
   unconnected output pin
1800
 
1801
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1802
 
1803
   unconnected output pin
1804
 
1805
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1806
 
1807
   unconnected output pin
1808
 
1809
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1810
 
1811
   unconnected output pin
1812
 
1813
 
1814
 
1815
   unconnected output pin
1816
 
1817
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1818
 
1819
 
1820
 
1821
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1822
 
1823
 
1824
 
1825
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1826
 
1827
   unconnected output pin
1828
 
1829
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1830
 
1831
   unconnected output pin
1832
 
1833
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1834
 
1835
   unconnected output pin
1836
 
1837
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1838
 
1839
   unconnected output pin
1840
 
1841
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1842
 
1843
   unconnected output pin
1844
 
1845
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1846
 
1847
   unconnected output pin
1848
 
1849
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1850
 
1851
   unconnected output pin
1852
 
1853
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1854
 
1855
   unconnected output pin
1856
 
1857
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1858
 
1859
   unconnected output pin
1860
 
1861
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1862
 
1863
   unconnected output pin
1864
 
1865
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1866
 
1867
WARNING:NgdBuild:443 - SFF primitive
1868
 
1869
   E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin
1870
 
1871
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1872
 
1873
   output pin
1874
 
1875
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1876
 
1877
   unconnected output pin
1878
 
1879
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1880
 
1881
   unconnected output pin
1882
 
1883
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1884
 
1885
   output pin
1886
 
1887
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1888
 
1889
   unconnected output pin
1890
 
1891
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1892
 
1893
   unconnected output pin
1894
 
1895
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
1896
 
1897
WARNING:NgdBuild:443 - SFF primitive
1898
 
1899
   SIZE2_REG1' has unconnected output pin
1900
 
1901
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
1902
 
1903
WARNING:NgdBuild:443 - SFF primitive
1904
 
1905
   unconnected output pin
1906
 
1907
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected
1908
 
1909
WARNING:NgdBuild:440 - FF primitive
1910
 
1911
   has unconnected output pin
1912
 
1913
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'
1914
 
1915
WARNING:NgdBuild:440 - FF primitive
1916
 
1917
   has unconnected output pin
1918
 
1919
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25'
1920
 
1921
WARNING:NgdBuild:440 - FF primitive
1922
 
1923
   has unconnected output pin
1924
 
1925
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'
1926
 
1927
WARNING:NgdBuild:440 - FF primitive
1928
 
1929
   has unconnected output pin
1930
 
1931
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'
1932
 
1933
WARNING:NgdBuild:440 - FF primitive
1934
 
1935
   has unconnected output pin
1936
 
1937
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15'
1938
 
1939
WARNING:NgdBuild:440 - FF primitive
1940
 
1941
   has unconnected output pin
1942
 
1943
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25'
1944
 
1945
WARNING:NgdBuild:440 - FF primitive
1946
 
1947
   has unconnected output pin
1948
 
1949
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'
1950
 
1951
WARNING:NgdBuild:440 - FF primitive
1952
 
1953
   has unconnected output pin
1954
 
1955
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'
1956
 
1957
WARNING:NgdBuild:440 - FF primitive
1958
 
1959
   /gen_rden[1].u_calib_rden_r' has unconnected output pin
1960
 
1961
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
1962
 
1963
WARNING:NgdBuild:440 - FF primitive
1964
 
1965
   /gen_rden[3].u_calib_rden_r' has unconnected output pin
1966
 
1967
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
1968
 
1969
WARNING:NgdBuild:440 - FF primitive
1970
 
1971
   /gen_rden[5].u_calib_rden_r' has unconnected output pin
1972
 
1973
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
1974
 
1975
WARNING:NgdBuild:440 - FF primitive
1976
 
1977
   /gen_rden[7].u_calib_rden_r' has unconnected output pin
1978
 
1979
   'ppc440_0_apu_fpu_virtex5/ppc440_0_apu_fpu_virtex5/gen_apu_fpu_dp_lo.netlist/
1980
 
1981
   no_rlocs.fast_del.carry_fd' has unconnected output pin
1982
 
1983
   "clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"
1984
 
1985
WARNING:NgdBuild:452 - logical net 'N194' has no driver
1986
 
1987
WARNING:NgdBuild:452 - logical net 'N196' has no driver
1988
 
1989
WARNING:NgdBuild:452 - logical net 'N198' has no driver
1990
 
1991
WARNING:NgdBuild:452 - logical net 'N200' has no driver
1992
 
1993
WARNING:NgdBuild:452 - logical net 'N202' has no driver
1994
 
1995
WARNING:NgdBuild:452 - logical net 'N204' has no driver
1996
 
1997
WARNING:NgdBuild:452 - logical net 'N206' has no driver
1998
 
1999
WARNING:NgdBuild:452 - logical net 'N208' has no driver
2000
 
2001
WARNING:NgdBuild:452 - logical net 'N210' has no driver
2002
 
2003
WARNING:NgdBuild:452 - logical net 'N212' has no driver
2004
 
2005
WARNING:NgdBuild:452 - logical net 'N214' has no driver
2006
 
2007
WARNING:NgdBuild:452 - logical net 'N216' has no driver
2008
 
2009
WARNING:NgdBuild:452 - logical net 'N218' has no driver
2010
 
2011
WARNING:NgdBuild:452 - logical net 'N220' has no driver
2012
 
2013
WARNING:NgdBuild:452 - logical net 'N222' has no driver
2014
 
2015
WARNING:NgdBuild:452 - logical net 'N224' has no driver
2016
 
2017
WARNING:NgdBuild:452 - logical net 'N226' has no driver
2018
 
2019
WARNING:NgdBuild:452 - logical net 'N228' has no driver
2020
 
2021
WARNING:NgdBuild:452 - logical net 'N230' has no driver
2022
 
2023
WARNING:NgdBuild:452 - logical net 'N232' has no driver
2024
 
2025
WARNING:NgdBuild:452 - logical net 'N234' has no driver
2026
 
2027
WARNING:NgdBuild:452 - logical net 'N236' has no driver
2028
 
2029
WARNING:NgdBuild:452 - logical net 'N238' has no driver
2030
 
2031
WARNING:NgdBuild:452 - logical net 'N240' has no driver
2032
 
2033
WARNING:NgdBuild:452 - logical net 'N242' has no driver
2034
 
2035
WARNING:NgdBuild:452 - logical net 'N244' has no driver
2036
 
2037
WARNING:NgdBuild:452 - logical net 'N246' has no driver
2038
 
2039
WARNING:NgdBuild:452 - logical net 'N248' has no driver
2040
 
2041
WARNING:NgdBuild:452 - logical net 'N250' has no driver
2042
 
2043
WARNING:NgdBuild:452 - logical net 'N252' has no driver
2044
 
2045
WARNING:NgdBuild:452 - logical net 'N254' has no driver
2046
 
2047
WARNING:NgdBuild:452 - logical net 'N256' has no driver
2048
 
2049
WARNING:NgdBuild:452 - logical net 'N266' has no driver
2050
 
2051
WARNING:NgdBuild:452 - logical net 'N268' has no driver
2052
 
2053
WARNING:NgdBuild:452 - logical net 'N270' has no driver
2054
 
2055
WARNING:NgdBuild:452 - logical net 'N272' has no driver
2056
 
2057
WARNING:NgdBuild:452 - logical net 'N306' has no driver
2058
 
2059
WARNING:NgdBuild:452 - logical net 'N308' has no driver
2060
 
2061
WARNING:NgdBuild:452 - logical net 'N310' has no driver
2062
 
2063
WARNING:NgdBuild:452 - logical net 'N312' has no driver
2064
 
2065
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'
2066
 
2067
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'
2068
 
2069
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'
2070
 
2071
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'
2072
 
2073
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'
2074
 
2075
2076
 
2077
-------------------------------
2078
 
2079
  No Partitions were found in this design.
2080
 
2081
-------------------------------
2082
 
2083
NGDBUILD Design Results Summary:
2084
 
2085
  Number of warnings: 349
2086
 
2087
Writing NGD file "system.ngd" ...
2088
 
2089
Total CPU time to NGDBUILD completion:  1 min  50 sec
2090
 
2091
Writing NGDBUILD log file "system.bld"...
2092
 
2093
NGDBUILD done.
2094
 
2095
2096
 
2097
#----------------------------------------------#
2098
 
2099
# map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing
2100
 
2101
#----------------------------------------------#
2102
 
2103
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
2104
 
2105
 with local file
2106
 
2107
Using target part "5vfx70tff1136-1".
2108
 
2109
WARNING:LIT:395 - The above warning message is repeated 1028 more times for the
2110
 
2111
   N195,
2112
 
2113
   N197,
2114
 
2115
   N199
2116
 
2117
Mapping design into LUTs...
2118
 
2119
   connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has
2120
 
2121
WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top
2122
 
2123
WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been
2124
 
2125
Writing file system_map.ngm...
2126
 
2127
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
2128
 
2129
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig
2130
 
2131
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
2132
 
2133
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig
2134
 
2135
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
2136
 
2137
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig
2138
 
2139
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
2140
 
2141
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig
2142
 
2143
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
2144
 
2145
   of frag REGCLKAU connected to power/ground net
2146
 
2147
   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig
2148
 
2149
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
2150
 
2151
   of frag REGCLKAL connected to power/ground net
2152
 
2153
   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig
2154
 
2155
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
2156
 
2157
   of frag REGCLKAU connected to power/ground net
2158
 
2159
   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig
2160
 
2161
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
2162
 
2163
   of frag REGCLKAL connected to power/ground net
2164
 
2165
   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig
2166
 
2167
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
2168
 
2169
   of frag RDRCLKU connected to power/ground net
2170
 
2171
   x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig
2172
 
2173
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
2174
 
2175
   of frag RDRCLKL connected to power/ground net
2176
 
2177
   x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig
2178
 
2179
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
2180
 
2181
   noeccerr.SDP
2182
 
2183
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
2184
 
2185
   noeccerr.SDP_RDRCLKU_tiesig
2186
 
2187
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
2188
 
2189
   noeccerr.SDP
2190
 
2191
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
2192
 
2193
   noeccerr.SDP_RDRCLKL_tiesig
2194
 
2195
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
2196
 
2197
   ram/SDP.WIDE_PRIM36.noeccerr.SDP
2198
 
2199
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
2200
 
2201
   ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
2202
 
2203
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
2204
 
2205
   ram/SDP.WIDE_PRIM36.noeccerr.SDP
2206
 
2207
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
2208
 
2209
   ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
2210
 
2211
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
2212
 
2213
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
2214
 
2215
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
2216
 
2217
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
2218
 
2219
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
2220
 
2221
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
2222
 
2223
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
2224
 
2225
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
2226
 
2227
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
2228
 
2229
   36.noeccerr.SDP
2230
 
2231
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
2232
 
2233
   36.noeccerr.SDP_RDRCLKU_tiesig
2234
 
2235
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
2236
 
2237
   36.noeccerr.SDP
2238
 
2239
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
2240
 
2241
   36.noeccerr.SDP_RDRCLKL_tiesig
2242
 
2243
Running delay-based LUT packing...
2244
 
2245
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM
2246
 
2247
   timing analysis.
2248
 
2249
   (.mrp).
2250
 
2251
Total REAL time at the beginning of Placer: 2 mins 24 secs
2252
 
2253
2254
 
2255
Phase 1.1  Initial Placement Analysis (Checksum:3a0b7697) REAL time: 2 mins 44 secs
2256
 
2257
Phase 2.7  Design Feasibility Check
2258
 
2259
   Components associated with this bus are as follows:
2260
 
2261
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6>   IOSTANDARD = LVCMOS25
2262
 
2263
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4>   IOSTANDARD = LVCMOS18
2264
 
2265
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2>   IOSTANDARD = LVCMOS18
2266
 
2267
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0>   IOSTANDARD = LVCMOS18
2268
 
2269
2270
 
2271
   Components associated with this bus are as follows:
2272
 
2273
         Comp: fpga_0_SRAM_Mem_DQ_pin<30>   IOSTANDARD = LVDCI_33
2274
 
2275
         Comp: fpga_0_SRAM_Mem_DQ_pin<28>   IOSTANDARD = LVDCI_33
2276
 
2277
         Comp: fpga_0_SRAM_Mem_DQ_pin<26>   IOSTANDARD = LVDCI_33
2278
 
2279
         Comp: fpga_0_SRAM_Mem_DQ_pin<24>   IOSTANDARD = LVDCI_33
2280
 
2281
         Comp: fpga_0_SRAM_Mem_DQ_pin<22>   IOSTANDARD = LVDCI_33
2282
 
2283
         Comp: fpga_0_SRAM_Mem_DQ_pin<20>   IOSTANDARD = LVDCI_33
2284
 
2285
         Comp: fpga_0_SRAM_Mem_DQ_pin<18>   IOSTANDARD = LVDCI_33
2286
 
2287
         Comp: fpga_0_SRAM_Mem_DQ_pin<16>   IOSTANDARD = LVDCI_33
2288
 
2289
         Comp: fpga_0_SRAM_Mem_DQ_pin<14>   IOSTANDARD = LVCMOS33
2290
 
2291
         Comp: fpga_0_SRAM_Mem_DQ_pin<12>   IOSTANDARD = LVCMOS33
2292
 
2293
         Comp: fpga_0_SRAM_Mem_DQ_pin<10>   IOSTANDARD = LVCMOS33
2294
 
2295
         Comp: fpga_0_SRAM_Mem_DQ_pin<8>   IOSTANDARD = LVCMOS33
2296
 
2297
         Comp: fpga_0_SRAM_Mem_DQ_pin<6>   IOSTANDARD = LVCMOS33
2298
 
2299
         Comp: fpga_0_SRAM_Mem_DQ_pin<4>   IOSTANDARD = LVCMOS33
2300
 
2301
         Comp: fpga_0_SRAM_Mem_DQ_pin<2>   IOSTANDARD = LVCMOS33
2302
 
2303
         Comp: fpga_0_SRAM_Mem_DQ_pin<0>   IOSTANDARD = LVCMOS33
2304
 
2305
2306
 
2307
2308
 
2309
Phase 3.31  Local Placement Optimization (Checksum:c9fd22c3) REAL time: 2 mins 45 secs
2310
 
2311
Phase 4.37  Local Placement Optimization
2312
 
2313
2314
 
2315
Phase 5.33  Local Placement Optimization (Checksum:c9fd22c3) REAL time: 10 mins 47 secs
2316
 
2317
Phase 6.32  Local Placement Optimization
2318
 
2319
2320
 
2321
2322
 
2323
2324
 
2325
|------------------------------------------|------------------------------------------|
2326
 
2327
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2328
 
2329
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
2330
 
2331
|                                          |                                          |
2332
 
2333
| CLOCKREGION_X0Y6:                        | CLOCKREGION_X1Y6:                        |
2334
 
2335
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
2336
 
2337
|   0 center BUFIOs available, 0 in use    |                                          |
2338
 
2339
|------------------------------------------|------------------------------------------|
2340
 
2341
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2342
 
2343
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
2344
 
2345
|                                          |                                          |
2346
 
2347
| CLOCKREGION_X0Y4:                        | CLOCKREGION_X1Y4:                        |
2348
 
2349
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
2350
 
2351
|   2 center BUFIOs available, 0 in use    |                                          |
2352
 
2353
|------------------------------------------|------------------------------------------|
2354
 
2355
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2356
 
2357
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
2358
 
2359
|                                          |                                          |
2360
 
2361
| CLOCKREGION_X0Y2:                        | CLOCKREGION_X1Y2:                        |
2362
 
2363
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
2364
 
2365
|   2 center BUFIOs available, 0 in use    |                                          |
2366
 
2367
|------------------------------------------|------------------------------------------|
2368
 
2369
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2370
 
2371
      |
2372
 
2373
|   0 center BUFIOs available, 0 in use    |                                          |
2374
 
2375
|------------------------------------------|------------------------------------------|
2376
 
2377
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2378
 
2379
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
2380
 
2381
|                                          |                                          |
2382
 
2383
2384
 
2385
Clock-Region: 
2386
 
2387
|-----------------------------------------------------------------------------------------------------------------------------------------------------------
2388
 
2389
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
2390
 
2391
|       | Upper Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region
2392
 
2393
|       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region
2394
 
2395
|       | Lower Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region
2396
 
2397
| clock |    region   |                                                                                      -----------------------------------------------
2398
 
2399
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2400
 
2401
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2402
 
2403
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2404
 
2405
2406
 
2407
  key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4
2408
 
2409
|       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |
2410
 
2411
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2412
 
2413
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2414
 
2415
|-------|-------------|------|-----|----|--------|-------
2416
 
2417
|       | Lower Region|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region
2418
 
2419
| clock |    region   |                                                                                      -----------------------------------------------
2420
 
2421
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2422
 
2423
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2424
 
2425
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2426
 
2427
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2428
 
2429
2430
 
2431
  key resource utilizations (used/available): edge-bufios - 3/4; bufrs - 0/2; regional-clock-spines - 0/4
2432
 
2433
|       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |
2434
 
2435
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2436
 
2437
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2438
 
2439
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2440
 
2441
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2442
 
2443
|  type |  expansion  |                                                                                      | 
2444
 
2445
| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |
2446
 
2447
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2448
 
2449
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2450
 
2451
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2452
 
2453
2454
 
2455
2456
 
2457
# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:
2458
 
2459
# Number of Regional Clocking Regions in the device: 16  (4 clock spines in each)
2460
 
2461
# composed of up to 3 clock spines and cover up to 3 regional clock regions)
2462
 
2463
######################################################################################
2464
 
2465
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" driven by "BUFIO_X0Y27"
2466
 
2467
"BUFIO_X0Y27" ;
2468
 
2469
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;
2470
 
2471
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;
2472
 
2473
CLOCKREGION_X0Y6;
2474
 
2475
2476
 
2477
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_bufio_dqs" LOC =
2478
 
2479
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" TNM_NET =
2480
 
2481
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" AREA_GROUP =
2482
 
2483
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" RANGE =
2484
 
2485
2486
 
2487
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" driven by "BUFIO_X0Y11"
2488
 
2489
"BUFIO_X0Y11" ;
2490
 
2491
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;
2492
 
2493
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;
2494
 
2495
CLOCKREGION_X0Y2;
2496
 
2497
2498
 
2499
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_bufio_dqs" LOC =
2500
 
2501
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" TNM_NET =
2502
 
2503
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" AREA_GROUP =
2504
 
2505
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" RANGE =
2506
 
2507
2508
 
2509
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" driven by "BUFIO_X0Y25"
2510
 
2511
"BUFIO_X0Y25" ;
2512
 
2513
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;
2514
 
2515
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;
2516
 
2517
CLOCKREGION_X0Y6;
2518
 
2519
2520
 
2521
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_bufio_dqs" LOC =
2522
 
2523
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" TNM_NET =
2524
 
2525
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" AREA_GROUP =
2526
 
2527
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" RANGE =
2528
 
2529
2530
 
2531
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" driven by "BUFIO_X0Y26"
2532
 
2533
"BUFIO_X0Y26" ;
2534
 
2535
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;
2536
 
2537
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;
2538
 
2539
CLOCKREGION_X0Y6;
2540
 
2541
2542
 
2543
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_bufio_dqs" LOC =
2544
 
2545
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" TNM_NET =
2546
 
2547
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" AREA_GROUP =
2548
 
2549
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" RANGE =
2550
 
2551
2552
 
2553
Phase 7.2  Initial Clock and IO Placement (Checksum:b5943100) REAL time: 11 mins 10 secs
2554
 
2555
Phase 8.36  Local Placement Optimization
2556
 
2557
2558
 
2559
..............
2560
 
2561
....
2562
 
2563
......
2564
 
2565
......
2566
 
2567
.......
2568
 
2569
......
2570
 
2571
......
2572
 
2573
.......
2574
 
2575
........
2576
 
2577
Phase 9.30  Global Clock Region Assignment
2578
 
2579
2580
 
2581
# GLOBAL CLOCK NET DISTRIBUTION UCF REPORT:
2582
 
2583
# Number of Global Clock Regions : 16
2584
 
2585
#
2586
 
2587
2588
 
2589
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT1.CLKOUT1_BUFG_INST" LOC = "BUFGCTRL_X0Y1" ;
2590
 
2591
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.gtxclk_pll_bufg" LOC = "BUFGCTRL_X0Y29" ;
2592
 
2593
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT2.CLKOUT2_BUFG_INST" LOC = "BUFGCTRL_X0Y2" ;
2594
 
2595
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/notsame.usrclk_pll_bufg" LOC = "BUFGCTRL_X0Y28" ;
2596
 
2597
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.clkfbin_pll_bufg" LOC = "BUFGCTRL_X0Y26" ;
2598
 
2599
INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/Using_BUFG_for_CLK0.CLK0_BUFG_INST" LOC = "BUFGCTRL_X0Y7" ;
2600
 
2601
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT0.CLKOUT0_BUFG_INST" LOC = "BUFGCTRL_X0Y5" ;
2602
 
2603
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/bufg2" LOC = "BUFGCTRL_X0Y0" ;
2604
 
2605
INST "fpga_0_SRAM_ZBT_CLK_FB_pin" LOC = "IOB_X1Y111" ;
2606
 
2607
INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" LOC = "IOB_X1Y219" ;
2608
 
2609
INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" LOC = "IOB_X1Y105" ;
2610
 
2611
INST "fpga_0_PCIe_Bridge_RXP_pin" LOC = "IPAD_X1Y13" ;
2612
 
2613
INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" LOC = "IPAD_X1Y17" ;
2614
 
2615
INST "fpga_0_PCIe_Bridge_TXP_pin" LOC = "OPAD_X0Y9" ;
2616
 
2617
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y0" ;
2618
 
2619
INST "ibufgds_76" LOC = "BUFDS_X0Y2" ;
2620
 
2621
# clk_125_0000MHzPLL0 driven by BUFGCTRL_X0Y1
2622
 
2623
TIMEGRP "TN_clk_125_0000MHzPLL0" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0" ;
2624
 
2625
2626
 
2627
NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;
2628
 
2629
AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
2630
 
2631
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk driven by BUFGCTRL_X0Y29
2632
 
2633
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;
2634
 
2635
2636
 
2637
NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;
2638
 
2639
AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
2640
 
2641
# clk_125_0000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y2
2642
 
2643
TIMEGRP "TN_clk_125_0000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0_ADJUST" ;
2644
 
2645
2646
 
2647
NET "clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" TNM_NET = "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;
2648
 
2649
AREA_GROUP "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y3 ;
2650
 
2651
# PCIe_Bridge/Bridge_Clk driven by BUFGCTRL_X0Y28
2652
 
2653
TIMEGRP "TN_PCIe_Bridge/Bridge_Clk" AREA_GROUP = "CLKAG_PCIe_Bridge/Bridge_Clk" ;
2654
 
2655
2656
 
2657
NET "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" TNM_NET = "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;
2658
 
2659
AREA_GROUP "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" RANGE =   CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;
2660
 
2661
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin driven by BUFGCTRL_X0Y26
2662
 
2663
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;
2664
 
2665
2666
 
2667
NET "clk_200_0000MHz" TNM_NET = "TN_clk_200_0000MHz" ;
2668
 
2669
AREA_GROUP "CLKAG_clk_200_0000MHz" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
2670
 
2671
# fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF driven by BUFGCTRL_X0Y7
2672
 
2673
TIMEGRP "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" AREA_GROUP = "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;
2674
 
2675
2676
 
2677
NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;
2678
 
2679
AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X1Y2, CLOCKREGION_X1Y3, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;
2680
 
2681
# clk_125_0000MHz90PLL0_ADJUST driven by BUFGCTRL_X0Y5
2682
 
2683
TIMEGRP "TN_clk_125_0000MHz90PLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHz90PLL0_ADJUST" ;
2684
 
2685
2686
 
2687
NET "clk_62_5000MHzPLL0_ADJUST" TNM_NET = "TN_clk_62_5000MHzPLL0_ADJUST" ;
2688
 
2689
AREA_GROUP "CLKAG_clk_62_5000MHzPLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
2690
 
2691
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg driven by BUFGCTRL_X0Y0
2692
 
2693
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;
2694
 
2695
2696
 
2697
# This report is provided to help reproduce successful clock-region
2698
 
2699
# clock networks, in a format that is directly usable in ucf files.
2700
 
2701
#END of Global Clock Net Distribution UCF Constraints
2702
 
2703
2704
 
2705
######################################################################################
2706
 
2707
2708
 
2709
Number of Global Clock Networks: 15
2710
 
2711
Clock Region Assignment: SUCCESSFUL
2712
 
2713
Clock-Region: 
2714
 
2715
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2716
 
2717
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2718
 
2719
     12 |      0 |      0 |      0 |     80 |     80 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
2720
 
2721
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2722
 
2723
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     38 |    676 |PCIe_Bridge/Bridge_Clk
2724
 
2725
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2726
 
2727
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2728
 
2729
2730
 
2731
 key resource utilizations (used/available): global-clocks - 3/10 ;
2732
 
2733
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2734
 
2735
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2736
 
2737
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2738
 
2739
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2740
 
2741
      4 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |     24 |     52 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
2742
 
2743
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2744
 
2745
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2746
 
2747
2748
 
2749
 key resource utilizations (used/available): global-clocks - 6/10 ;
2750
 
2751
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2752
 
2753
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2754
 
2755
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2756
 
2757
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2758
 
2759
      0 |      0 |      0 |      0 |      0 |     18 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |clk_125_0000MHz90PLL0_ADJUST
2760
 
2761
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz
2762
 
2763
      0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>
2764
 
2765
      4 |      1 |      1 |      0 |      0 |     35 |      0 |      0 |      0 |      0 |      1 |      0 |     51 |   1110 | Total
2766
 
2767
2768
 
2769
Clock-Region: 
2770
 
2771
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2772
 
2773
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2774
 
2775
      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
2776
 
2777
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2778
 
2779
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    104 |    750 |PCIe_Bridge/Bridge_Clk
2780
 
2781
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    312 |clk_125_0000MHzPLL0_ADJUST
2782
 
2783
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2784
 
2785
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2786
 
2787
2788
 
2789
 key resource utilizations (used/available): global-clocks - 5/10 ;
2790
 
2791
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2792
 
2793
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2794
 
2795
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2796
 
2797
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2798
 
2799
      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |clk_125_0000MHz90PLL0_ADJUST
2800
 
2801
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz
2802
 
2803
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2804
 
2805
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2806
 
2807
2808
 
2809
 key resource utilizations (used/available): global-clocks - 4/10 ;
2810
 
2811
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2812
 
2813
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2814
 
2815
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2816
 
2817
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2818
 
2819
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     59 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
2820
 
2821
      0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     28 |    407 |clk_125_0000MHzPLL0_ADJUST
2822
 
2823
      1 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |    178 |   1153 | Total
2824
 
2825
2826
 
2827
Clock-Region: 
2828
 
2829
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2830
 
2831
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2832
 
2833
      4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)
2834
 
2835
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2836
 
2837
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     79 |clk_125_0000MHz90PLL0_ADJUST
2838
 
2839
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      3 |clk_200_0000MHz
2840
 
2841
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2842
 
2843
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2844
 
2845
2846
 
2847
 key resource utilizations (used/available): global-clocks - 3/10 ;
2848
 
2849
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2850
 
2851
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2852
 
2853
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2854
 
2855
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2856
 
2857
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     27 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
2858
 
2859
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2860
 
2861
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2862
 
2863
2864
 
2865
 key resource utilizations (used/available): global-clocks - 4/10 ;
2866
 
2867
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2868
 
2869
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2870
 
2871
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2872
 
2873
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2874
 
2875
      4 |      0 |      0 |      0 |      1 |     20 |      0 |      0 |      0 |      0 |      0 |      0 |     51 |    262 |clk_125_0000MHzPLL0_ADJUST
2876
 
2877
      0 |      0 |      0 |      0 |      6 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP
2878
 
2879
      6 |      0 |      0 |      0 |      7 |     20 |      0 |      0 |      0 |      0 |      0 |      0 |     51 |    329 | Total
2880
 
2881
2882
 
2883
Clock-Region: 
2884
 
2885
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2886
 
2887
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2888
 
2889
     10 |      0 |      0 |      0 |     40 |     40 |     16 |      1 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
2890
 
2891
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2892
 
2893
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |PCIe_Bridge/Bridge_Clk
2894
 
2895
      0 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     23 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP
2896
 
2897
      3 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |     76 |   1089 | Total
2898
 
2899
2900
 
2901
Clock-Region: 
2902
 
2903
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2904
 
2905
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2906
 
2907
     12 |      2 |      1 |      0 |     60 |     60 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
2908
 
2909
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2910
 
2911
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     49 |clk_125_0000MHz90PLL0_ADJUST
2912
 
2913
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     99 |clk_62_5000MHzPLL0_ADJUST
2914
 
2915
      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |     72 |    749 | Total
2916
 
2917
2918
 
2919
Clock-Region: 
2920
 
2921
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2922
 
2923
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2924
 
2925
     10 |      0 |      0 |      0 |     40 |     40 |     16 |      1 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
2926
 
2927
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2928
 
2929
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     28 |PCIe_Bridge/Bridge_Clk
2930
 
2931
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP
2932
 
2933
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2934
 
2935
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2936
 
2937
2938
 
2939
 key resource utilizations (used/available): global-clocks - 7/10 ;
2940
 
2941
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2942
 
2943
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2944
 
2945
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2946
 
2947
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2948
 
2949
      0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin
2950
 
2951
      0 |      0 |      0 |      0 |      0 |      8 |      0 |      0 |      0 |      0 |      0 |      0 |     91 |    751 |clk_125_0000MHzPLL0_ADJUST
2952
 
2953
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    249 |clk_62_5000MHzPLL0_ADJUST
2954
 
2955
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2956
 
2957
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2958
 
2959
2960
 
2961
 key resource utilizations (used/available): global-clocks - 2/10 ;
2962
 
2963
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2964
 
2965
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2966
 
2967
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2968
 
2969
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2970
 
2971
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      4 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP
2972
 
2973
      0 |      0 |      0 |      0 |     19 |     23 |      0 |      0 |      0 |      0 |      0 |      0 |     97 |    800 | Total
2974
 
2975
2976
 
2977
Clock-Region: 
2978
 
2979
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2980
 
2981
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2982
 
2983
     12 |      0 |      0 |      0 |     80 |     80 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
2984
 
2985
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2986
 
2987
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    106 |    471 |clk_125_0000MHzPLL0_ADJUST
2988
 
2989
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP
2990
 
2991
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    116 |    782 | Total
2992
 
2993
2994
 
2995
Clock-Region: 
2996
 
2997
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2998
 
2999
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
3000
 
3001
      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
3002
 
3003
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
3004
 
3005
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    146 |    674 |clk_125_0000MHzPLL0_ADJUST
3006
 
3007
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    146 |    674 | Total
3008
 
3009
3010
 
3011
The above detailed report is the initial placement of the logic after the clock region assignment. The final placement
3012
 
3013
maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.
3014
 
3015
3016
 
3017
######################################################################################
3018
 
3019
3020
 
3021
3022
 
3023
Phase 10.3  Local Placement Optimization (Checksum:b5943100) REAL time: 12 mins 46 secs
3024
 
3025
Phase 11.5  Local Placement Optimization
3026
 
3027
3028
 
3029
..
3030
 
3031
...........
3032
 
3033
......
3034
 
3035
.....
3036
 
3037
.....
3038
 
3039
.....
3040
 
3041
....
3042
 
3043
.....
3044
 
3045
....
3046
 
3047
.....
3048
 
3049
.......
3050
 
3051
.......
3052
 
3053
.......
3054
 
3055
...
3056
 
3057
.....
3058
 
3059
.....
3060
 
3061
......
3062
 
3063
......
3064
 
3065
......
3066
 
3067
.....
3068
 
3069
.....
3070
 
3071
....
3072
 
3073
....
3074
 
3075
...
3076
 
3077
...
3078
 
3079
..
3080
 
3081
...
3082
 
3083
...
3084
 
3085
...
3086
 
3087
.
3088
 
3089
..
3090
 
3091
..
3092
 
3093
...
3094
 
3095
....
3096
 
3097
....
3098
 
3099
.
3100
 
3101
...
3102
 
3103
..
3104
 
3105
..
3106
 
3107
..
3108
 
3109
....
3110
 
3111
.
3112
 
3113
..
3114
 
3115
.
3116
 
3117
..
3118
 
3119
...
3120
 
3121
.
3122
 
3123
...
3124
 
3125
...
3126
 
3127
...
3128
 
3129
.
3130
 
3131
.
3132
 
3133
...
3134
 
3135
.
3136
 
3137
....
3138
 
3139
.
3140
 
3141
.....
3142
 
3143
...
3144
 
3145
...
3146
 
3147
.....
3148
 
3149
....
3150
 
3151
....
3152
 
3153
......
3154
 
3155
....
3156
 
3157
....
3158
 
3159
Phase 12.8  Global Placement (Checksum:64c223c7) REAL time: 20 mins 44 secs
3160
 
3161
Phase 13.29  Local Placement Optimization
3162
 
3163
3164
 
3165
Phase 14.5  Local Placement Optimization (Checksum:64c223c7) REAL time: 20 mins 49 secs
3166
 
3167
Phase 15.18  Placement Optimization
3168
 
3169
3170
 
3171
Phase 16.5  Local Placement Optimization (Checksum:d0a37aa3) REAL time: 23 mins 28 secs
3172
 
3173
Phase 17.34  Placement Validation
3174
 
3175
3176
 
3177
Total CPU  time to Placer completion: 22 mins 30 secs
3178
 
3179
Writing output files...
3180
 
3181
Design Summary:
3182
 
3183
Number of warnings:   52
3184
 
3185
  Number of Slice Registers:                14,755 out of  44,800   32%
3186
 
3187
    Number used as Latches:                      1
3188
 
3189
    Number used as logic:                   15,565 out of  44,800   34%
3190
 
3191
      Number using O5 output only:             371
3192
 
3193
    Number used as Memory:                     724 out of  13,120    5%
3194
 
3195
        Number using O6 output only:            12
3196
 
3197
        Number using O5 and O6:                184
3198
 
3199
        Number using O6 output only:             4
3200
 
3201
        Number using O6 output only:           492
3202
 
3203
  Number of route-thrus:                       581
3204
 
3205
    Number using O5 output only:                81
3206
 
3207
3208
 
3209
  Number of occupied Slices:                 7,735 out of  11,200   69%
3210
 
3211
    Number with an unused Flip Flop:         6,649 out of  21,404   31%
3212
 
3213
    Number of fully used LUT-FF pairs:       9,770 out of  21,404   45%
3214
 
3215
    Number of slice register sites lost
3216
 
3217
3218
 
3219
  one Flip Flop within a slice.  A control set is a unique combination of
3220
 
3221
  The Slice Logic Distribution report is not meaningful if the design is
3222
 
3223
  OVERMAPPING of BRAM resources should be ignored if the design is
3224
 
3225
3226
 
3227
  Number of bonded IOBs:                       255 out of     640   39%
3228
 
3229
    IOB Flip Flops:                            494
3230
 
3231
    Number of bonded OPADs:                      2 out of      32    6%
3232
 
3233
Specific Feature Utilization:
3234
 
3235
    Number using BlockRAM only:                 20
3236
 
3237
    Total primitives used:
3238
 
3239
      Number of 18k BlockRAM used:               6
3240
 
3241
    Total Memory used (KB):                    756 out of   5,328   14%
3242
 
3243
    Number used as BUFGs:                       15
3244
 
3245
  Number of BUFDSs:                              1 out of       8   12%
3246
 
3247
  Number of DCM_ADVs:                            1 out of      12    8%
3248
 
3249
  Number of GTX_DUALs:                           1 out of       8   12%
3250
 
3251
    Number of LOCed PCIEs:                       1 out of       1  100%
3252
 
3253
  Number of PPC440s:                             1 out of       1  100%
3254
 
3255
  Number of RPM macros:           64
3256
 
3257
3258
 
3259
Total REAL time to MAP completion:  24 mins 23 secs
3260
 
3261
3262
 
3263
See MAP report file "system_map.mrp" for details.
3264
 
3265
3266
 
3267
#----------------------------------------------#
3268
 
3269
# par -ise ../__xps/ise/system.ise -w -ol high system_map.ncd system.ncd
3270
 
3271
#----------------------------------------------#
3272
 
3273
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
3274
 
3275
3276
 
3277
3278
 
3279
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
3280
 
3281
3282
 
3283
   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
3284
 
3285
   overrides constraint  [system.pcf(90241)].
3286
 
3287
3288
 
3289
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
3290
 
3291
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP
3292
 
3293
INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please
3294
 
3295
3296
 
3297
3298
 
3299
3300
 
3301
3302
 
3303
   Number of BUFGs                          15 out of 32     46%
3304
 
3305
   Number of DCM_ADVs                        1 out of 12      8%
3306
 
3307
   Number of FIFO36_72_EXPs                  2 out of 148     1%
3308
 
3309
3310
 
3311
   Number of IDELAYCTRLs                     3 out of 22     13%
3312
 
3313
3314
 
3315
      Number of LOCed ILOGICs                8 out of 131     6%
3316
 
3317
   Number of External IOBs                 255 out of 640    39%
3318
 
3319
3320
 
3321
      Number of LOCed IODELAYs               8 out of 80     10%
3322
 
3323
   Number of External IPADs                  4 out of 690     1%
3324
 
3325
3326
 
3327
   Number of OLOGICs                       236 out of 800    29%
3328
 
3329
      Number of LOCed OPADs                  2 out of 2     100%
3330
 
3331
   Number of PCIEs                           1 out of 3      33%
3332
 
3333
3334
 
3335
   Number of PPC440s                         1 out of 1     100%
3336
 
3337
   Number of RAMB36SDP_EXPs                  6 out of 148     4%
3338
 
3339
3340
 
3341
      Number of LOCed RAMB36_EXPs            6 out of 10     60%
3342
 
3343
   Number of Slice Registers             14755 out of 44800  32%
3344
 
3345
      Number used as Latches                 1
3346
 
3347
3348
 
3349
   Number of Slice LUT-Flip Flop pairs   21404 out of 44800  47%
3350
 
3351
3352
 
3353
Router effort level (-rl):    High
3354
 
3355
Starting initial Timing Analysis.  REAL time: 1 mins 25 secs
3356
 
3357
3358
 
3359
   signal.
3360
 
3361
   signal.
3362
 
3363
   signal.
3364
 
3365
   signal.
3366
 
3367
   signal.
3368
 
3369
3370
 
3371
   that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail,
3372
 
3373
3374
 
3375
3376
 
3377
3378
 
3379
3380
 
3381
3382
 
3383
3384
 
3385
3386
 
3387
3388
 
3389
3390
 
3391
3392
 
3393
3394
 
3395
Total REAL time to Router completion: 9 mins 7 secs
3396
 
3397
3398
 
3399
-------------------------------
3400
 
3401
  No Partitions were found in this design.
3402
 
3403
-------------------------------
3404
 
3405
Generating "PAR" statistics.
3406
 
3407
**************************
3408
 
3409
**************************
3410
 
3411
+---------------------+--------------+------+------+------------+-------------+
3412
 
3413
+---------------------+--------------+------+------+------------+-------------+
3414
 
3415
|              ADJUST | BUFGCTRL_X0Y2| No   | 4263 |  0.532     |  2.076      |
3416
 
3417
|PCIe_Bridge/Bridge_C |              |      |      |            |             |
3418
 
3419
+---------------------+--------------+------+------+------------+-------------+
3420
 
3421
|               DJUST | BUFGCTRL_X0Y6| No   |  490 |  0.318     |  2.057      |
3422
 
3423
|clk_125_0000MHz90PLL |              |      |      |            |             |
3424
 
3425
+---------------------+--------------+------+------+------------+-------------+
3426
 
3427
|tFlash_SysACE_CLK_pi |              |      |      |            |             |
3428
 
3429
+---------------------+--------------+------+------+------------+-------------+
3430
 
3431
|dge/comp_block_plus/ |              |      |      |            |             |
3432
 
3433
|                  lk |BUFGCTRL_X0Y27| No   |   94 |  0.260     |  2.085      |
3434
 
3435
|fpga_0_Ethernet_MAC_ |              |      |      |            |             |
3436
 
3437
|                     |BUFGCTRL_X0Y30| No   |   12 |  0.093     |  1.934      |
3438
 
3439
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
3440
 
3441
|f_top/u_phy_top/u_ph |              |      |      |            |             |
3442
 
3443
+---------------------+--------------+------+------+------------+-------------+
3444
 
3445
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
3446
 
3447
| y_io/delayed_dqs<1> |        IO Clk| No   |   18 |  0.083     |  0.380      |
3448
 
3449
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
3450
 
3451
|f_top/u_phy_top/u_ph |              |      |      |            |             |
3452
 
3453
+---------------------+--------------+------+------+------------+-------------+
3454
 
3455
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
3456
 
3457
| y_io/delayed_dqs<3> |        IO Clk| No   |   18 |  0.107     |  0.404      |
3458
 
3459
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
3460
 
3461
      |            |             |
3462
 
3463
| y_io/delayed_dqs<5> |        IO Clk| No   |   18 |  0.101     |  0.425      |
3464
 
3465
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
3466
 
3467
|f_top/u_phy_top/u_ph |              |      |      |            |             |
3468
 
3469
+---------------------+--------------+------+------+------------+-------------+
3470
 
3471
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
3472
 
3473
| y_io/delayed_dqs<6> |        IO Clk| No   |   18 |  0.096     |  0.393      |
3474
 
3475
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
3476
 
3477
|f_top/u_phy_top/u_ph |              |      |      |            |             |
3478
 
3479
+---------------------+--------------+------+------+------------+-------------+
3480
 
3481
|PHY_tx_clk_pin_BUFGP |              |      |      |            |             |
3482
 
3483
+---------------------+--------------+------+------+------------+-------------+
3484
 
3485
+---------------------+--------------+------+------+------------+-------------+
3486
 
3487
|dge/comp_block_plus/ |              |      |      |            |             |
3488
 
3489
|        lk/gt_usrclk |BUFGCTRL_X0Y29| No   |    6 |  0.096     |  1.916      |
3490
 
3491
|     clk_200_0000MHz | BUFGCTRL_X0Y4| No   |    4 |  0.128     |  1.879      |
3492
 
3493
|RS232_Uart_1_Interru |              |      |      |            |             |
3494
 
3495
+---------------------+--------------+------+------+------------+-------------+
3496
 
3497
|  t_MAC/phy_tx_clk_i |         Local|      |    9 |  2.410     |  3.454      |
3498
 
3499
|ppc440_0_jtagppc_bus |              |      |      |            |             |
3500
 
3501
+---------------------+--------------+------+------+------------+-------------+
3502
 
3503
|dge/comp_block_plus/ |              |      |      |            |             |
3504
 
3505
|lk/SIO/.pcie_gt_wrap |              |      |      |            |             |
3506
 
3507
+---------------------+--------------+------+------+------------+-------------+
3508
 
3509
* Net Skew is the difference between the minimum and maximum routing
3510
 
3511
is reported in TRCE timing report. Clock Skew is the difference between
3512
 
3513
3514
 
3515
3516
 
3517
3518
 
3519
   This may be due to a setup or hold violation.
3520
 
3521
----------------------------------------------------------------------------------------------------------
3522
 
3523
                                            |             |    Slack   | Achievable | Errors |    Score
3524
 
3525
  NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | SETUP       |     0.030ns|     7.970ns|       0|           0
3526
 
3527
                                            | MINPERIOD   |     0.000ns|     8.000ns|       0|           0
3528
 
3529
  NET "PCIe_Bridge/PCIe_Bridge/comp_block_p | SETUP       |     0.075ns|     3.925ns|       0|           0
3530
 
3531
      4 ns HIGH 50%                         | MINPERIOD   |     0.000ns|     4.000ns|       0|           0
3532
 
3533
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.012ns|     0.838ns|       0|           0
3534
 
3535
  dqs[2].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
3536
 
3537
------------------------------------------------------------------------------------------------------
3538
 
3539
  CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS"       | HOLD        |     1.026ns|            |       0|           0
3540
 
3541
------------------------------------------------------------------------------------------------------
3542
 
3543
  L0_CLK_OUT_2_ = PERIOD TIMEGRP         "c | HOLD        |     0.079ns|            |       0|           0
3544
 
3545
  LK_OUT_2_" TS_sys_clk_pin *         1.25  |             |            |            |        |
3546
 
3547
------------------------------------------------------------------------------------------------------
3548
 
3549
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
3550
 
3551
  DELAY = 0.85 ns                           |             |            |            |        |
3552
 
3553
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0
3554
 
3555
  dqs[1].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
3556
 
3557
------------------------------------------------------------------------------------------------------
3558
 
3559
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
3560
 
3561
  DELAY = 0.85 ns                           |             |            |            |        |
3562
 
3563
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0
3564
 
3565
  dqs[3].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
3566
 
3567
------------------------------------------------------------------------------------------------------
3568
 
3569
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
3570
 
3571
  DELAY = 0.85 ns                           |             |            |            |        |
3572
 
3573
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0
3574
 
3575
  dqs[6].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
3576
 
3577
------------------------------------------------------------------------------------------------------
3578
 
3579
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
3580
 
3581
  DELAY = 0.85 ns                           |             |            |            |        |
3582
 
3583
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.068ns|     0.532ns|       0|           0
3584
 
3585
  qs<0>"         MAXDELAY = 0.6 ns          |             |            |            |        |
3586
 
3587
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0
3588
 
3589
  qs<1>"         MAXDELAY = 0.6 ns          |             |            |            |        |
3590
 
3591
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0
3592
 
3593
  qs<2>"         MAXDELAY = 0.6 ns          |             |            |            |        |
3594
 
3595
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0
3596
 
3597
  qs<3>"         MAXDELAY = 0.6 ns          |             |            |            |        |
3598
 
3599
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0
3600
 
3601
  qs<4>"         MAXDELAY = 0.6 ns          |             |            |            |        |
3602
 
3603
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0
3604
 
3605
  qs<5>"         MAXDELAY = 0.6 ns          |             |            |            |        |
3606
 
3607
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0
3608
 
3609
  qs<6>"         MAXDELAY = 0.6 ns          |             |            |            |        |
3610
 
3611
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.071ns|     0.529ns|       0|           0
3612
 
3613
  qs<7>"         MAXDELAY = 0.6 ns          |             |            |            |        |
3614
 
3615
  TS_PLB_PCIe = MAXDELAY FROM TIMEGRP "SPLB | SETUP       |     0.449ns|     7.551ns|       0|           0
3616
 
3617
    DATAPATHONLY                            |             |            |            |        |
3618
 
3619
  TS_PCIe_PLB = MAXDELAY FROM TIMEGRP "Brid | SETUP       |     0.639ns|     7.361ns|       0|           0
3620
 
3621
    DATAPATHONLY                            |             |            |            |        |
3622
 
3623
  TS_MC_CLK = PERIOD TIMEGRP "mc_clk" 5 ns  | MINPERIOD   |     1.010ns|     3.990ns|       0|           0
3624
 
3625
------------------------------------------------------------------------------------------------------
3626
 
3627
  RP "PADS" TO TIMEGRP         "RXCLK_GRP_E | HOLD        |     1.060ns|            |       0|           0
3628
 
3629
------------------------------------------------------------------------------------------------------
3630
 
3631
  L0_CLK_OUT_0_ = PERIOD TIMEGRP         "c | HOLD        |     0.476ns|            |       0|           0
3632
 
3633
  LK_OUT_0_" TS_sys_clk_pin *         1.25  |             |            |            |        |
3634
 
3635
------------------------------------------------------------------------------------------------------
3636
 
3637
  pin" 100 MHz HIGH 50%                     |             |            |            |        |
3638
 
3639
  TS_clock_generator_0_clock_generator_0_PL | SETUP       |     3.644ns|     1.356ns|       0|           0
3640
 
3641
  lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |
3642
 
3643
  H 50%                                     |             |            |            |        |
3644
 
3645
  TS_clock_generator_0_clock_generator_0_PL | SETUP       |     4.149ns|     8.008ns|       0|           0
3646
 
3647
  lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |
3648
 
3649
   HIGH 50%                                 |             |            |            |        |
3650
 
3651
  NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | NETSKEW     |     4.422ns|     0.578ns|       0|           0
3652
 
3653
------------------------------------------------------------------------------------------------------
3654
 
3655
  UFGP" MAXSKEW = 5 ns                      |             |            |            |        |
3656
 
3657
  TS_clock_generator_0_clock_generator_0_PL | MINPERIOD   |     4.900ns|     3.100ns|       0|           0
3658
 
3659
  lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |
3660
 
3661
  HIGH 50%                                  |             |            |            |        |
3662
 
3663
  TSTXOUT_Ethernet_MAC = MAXDELAY FROM TIME | MAXDELAY    |     7.423ns|     2.577ns|       0|           0
3664
 
3665
  IMEGRP "PADS" 10 ns                       |             |            |            |        |
3666
 
3667
  NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | SETUP       |     9.210ns|    13.685ns|       0|           0
3668
 
3669
------------------------------------------------------------------------------------------------------
3670
 
3671
  M TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO      | HOLD        |     0.290ns|            |       0|           0
3672
 
3673
------------------------------------------------------------------------------------------------------
3674
 
3675
   TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO       | HOLD        |     0.915ns|            |       0|           0
3676
 
3677
------------------------------------------------------------------------------------------------------
3678
 
3679
  NM_GATE_DLY" TO TIMEGRP "TNM_CLK0"        | HOLD        |     0.003ns|            |       0|           0
3680
 
3681
------------------------------------------------------------------------------------------------------
3682
 
3683
  P "TNM_CAL_RDEN_DLY" TO TIMEGRP         " | HOLD        |     0.001ns|            |       0|           0
3684
 
3685
------------------------------------------------------------------------------------------------------
3686
 
3687
  NM_RDEN_DLY" TO TIMEGRP "TNM_CLK0"        | HOLD        |     0.023ns|            |       0|           0
3688
 
3689
------------------------------------------------------------------------------------------------------
3690
 
3691
  K_pin_BUFGP/IBUFG" PERIOD = 30 ns         | HOLD        |     0.465ns|            |       0|           0
3692
 
3693
------------------------------------------------------------------------------------------------------
3694
 
3695
  UFGP" PERIOD = 40 ns HIGH 14 ns           | HOLD        |     0.357ns|            |       0|           0
3696
 
3697
  Pin to Pin Skew Constraint                | MAXDELAY    | 2106523.523ns| 2106523.837ns|       0|           0
3698
 
3699
  TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGR | N/A         |         N/A|         N/A|     N/A|         N/A
3700
 
3701
  TNM_CLK0" TS_MC_CLK * 4                   |             |            |            |        |
3702
 
3703
  NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 n | N/A         |         N/A|         N/A|     N/A|         N/A
3704
 
3705
------------------------------------------------------------------------------------------------------
3706
 
3707
3708
 
3709
Derived Constraints for TS_MC_CLK
3710
 
3711
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
3712
 
3713
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
3714
 
3715
|TS_MC_CLK                      |      5.000ns|      3.990ns|      1.584ns|            0|            0|            0|          345|
3716
 
3717
| TS_MC_PHY_INIT_DATA_SEL_90    |     20.000ns|      6.337ns|          N/A|            0|            0|          274|            0|
3718
 
3719
| TS_MC_RDEN_DLY                |     20.000ns|      1.868ns|          N/A|            0|            0|            5|            0|
3720
 
3721
| TS_MC_RDEN_SEL_MUX            |     20.000ns|          N/A|          N/A|            0|            0|            0|            0|
3722
 
3723
3724
 
3725
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
3726
 
3727
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
3728
 
3729
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
3730
 
3731
| TS_clock_generator_0_clock_gen|      8.000ns|      4.973ns|          N/A|            0|            0|          626|            0|
3732
 
3733
| TS_clock_generator_0_clock_gen|      8.000ns|      3.100ns|          N/A|            0|            0|            0|            0|
3734
 
3735
| TS_clock_generator_0_clock_gen|      8.000ns|      7.974ns|          N/A|            0|            0|      4031781|            0|
3736
 
3737
| TS_clock_generator_0_clock_gen|      5.000ns|      1.356ns|          N/A|            0|            0|            2|            0|
3738
 
3739
| TS_clock_generator_0_clock_gen|     16.000ns|      8.008ns|          N/A|            0|            0|        11042|            0|
3740
 
3741
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
3742
 
3743
All constraints were met.
3744
 
3745
   constraint does not cover any paths or that it has no requested value.
3746
 
3747
3748
 
3749
3750
 
3751
3752
 
3753
3754
 
3755
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
3756
 
3757
INFO:ParHelpers:199 - All "EXACT" mode Directed Routing constrained nets successfully routed. The number of constraints
3758
 
3759
Total REAL time to PAR completion: 10 mins 4 secs
3760
 
3761
3762
 
3763
3764
 
3765
Routing: Completed - No errors found.
3766
 
3767
3768
 
3769
Number of warning messages: 9
3770
 
3771
3772
 
3773
3774
 
3775
3776
 
3777
3778
 
3779
3780
 
3781
# Starting program post_par_trce
3782
 
3783
#----------------------------------------------#
3784
 
3785
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
3786
 
3787
3788
 
3789
 with local file
3790
 
3791
Loading device for application Rf_Device from file '5vfx70t.nph' in environment
3792
 
3793
   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
3794
 
3795
   8 ns HIGH 50%;> [system.pcf(90242)] overrides constraint 
3796
 
3797
3798
 
3799
   TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP        "TNM_CLK0" TS_MC_CLK * 4;
3800
 
3801
INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more
3802
 
3803
   Tools User Guide for information on generating a TSI report.
3804
 
3805
Release 11.2 Trace  (nt)
3806
 
3807
3808
 
3809
3810
 
3811
Design file:              system.ncd
3812
 
3813
Device,speed:             xc5vfx70t,-1 (PRODUCTION 1.65 2009-06-01, STEPPING
3814
 
3815
Report level:             error report
3816
 
3817
3818
 
3819
   option. All paths that are not constrained will be reported in the
3820
 
3821
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a
3822
 
3823
   for more information on accounting for different loading conditions, please
3824
 
3825
3826
 
3827
Timing summary:
3828
 
3829
3830
 
3831
3832
 
3833
3834
 
3835
   Minimum period:  13.685ns (Maximum frequency:  73.073MHz)
3836
 
3837
   Maximum net delay:   0.838ns
3838
 
3839
3840
 
3841
Analysis completed Tue Jun 30 23:01:07 2009
3842
 
3843
3844
 
3845
3846
 
3847
Number of info messages: 3
3848
 
3849
3850
 
3851
xflow done!
3852
 
3853
xilperl C:/devtools/Xilinx/11.1/EDK/data/fpga_impl/observe_par.pl -error yes implementation/system.par
3854
 
3855
*********************************************
3856
 
3857
*********************************************
3858
 
3859
Release 11.2 - Bitgen L.46 (nt)
3860
 
3861
PMSPEC -- Overriding Xilinx file
3862
 
3863
3864
 
3865
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
3866
 
3867
Opened constraints file system.pcf.
3868
 
3869
Tue Jun 30 23:01:40 2009
3870
 
3871
Running DRC.
3872
 
3873
   Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX
3874
 
3875
   guidelines to minimize the impact on GTX performance.
3876
 
3877
   Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.
3878
 
3879
   data into the flip-flop.
3880
 
3881
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_w
3882
 
3883
   design practice. Use the CE pin to control the loading of data into the
3884
 
3885
WARNING:PhysDesignRules:367 - The signal
3886
 
3887
   not drive any load pins in the design.
3888
 
3889
   > is incomplete. The signal does not
3890
 
3891
WARNING:PhysDesignRules:367 - The signal
3892
 
3893
   drive any load pins in the design.
3894
 
3895
   > is incomplete. The signal does not
3896
 
3897
WARNING:PhysDesignRules:367 - The signal 
3898
 
3899
WARNING:PhysDesignRules:1269 - Dangling pins on
3900
 
3901
   qs[1].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
3902
 
3903
WARNING:PhysDesignRules:1273 - Dangling pins on
3904
 
3905
   qs[1].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
3906
 
3907
WARNING:PhysDesignRules:1269 - Dangling pins on
3908
 
3909
   qs[4].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
3910
 
3911
WARNING:PhysDesignRules:1273 - Dangling pins on
3912
 
3913
   qs[4].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
3914
 
3915
WARNING:PhysDesignRules:1269 - Dangling pins on
3916
 
3917
   qs[7].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
3918
 
3919
WARNING:PhysDesignRules:1273 - Dangling pins on
3920
 
3921
   qs[7].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
3922
 
3923
WARNING:PhysDesignRules:1269 - Dangling pins on
3924
 
3925
   qs[2].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
3926
 
3927
WARNING:PhysDesignRules:1273 - Dangling pins on
3928
 
3929
   qs[2].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
3930
 
3931
WARNING:PhysDesignRules:1269 - Dangling pins on
3932
 
3933
   qs[5].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
3934
 
3935
WARNING:PhysDesignRules:1273 - Dangling pins on
3936
 
3937
   qs[5].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
3938
 
3939
WARNING:PhysDesignRules:1269 - Dangling pins on
3940
 
3941
   qs[0].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
3942
 
3943
WARNING:PhysDesignRules:1273 - Dangling pins on
3944
 
3945
   qs[0].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
3946
 
3947
WARNING:PhysDesignRules:1269 - Dangling pins on
3948
 
3949
   qs[3].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
3950
 
3951
WARNING:PhysDesignRules:1273 - Dangling pins on
3952
 
3953
   qs[3].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
3954
 
3955
WARNING:PhysDesignRules:1269 - Dangling pins on
3956
 
3957
   qs[6].u_iob_dqs/u_iddr_dq_ce>:.  The Q1 output pin of IFF is not
3958
 
3959
WARNING:PhysDesignRules:1273 - Dangling pins on
3960
 
3961
   qs[6].u_iob_dqs/u_iddr_dq_ce>:.  The SR pin is used for the IFF
3962
 
3963
WARNING:PhysDesignRules:367 - The signal
3964
 
3965
   fpu_is_full.sqrt_sqrt_flt_pt_op_sqrt_op.spd.op_exp_exp_sig_del_delay_55_2/Pro
3966
 
3967
   in the design.
3968
 
3969
   
3970
 
3971
   toComp7000.C6LUT.O6> is incomplete. The signal does not drive any load pins
3972
 
3973
DRC detected 0 errors and 26 warnings.  Please see the previously displayed
3974
 
3975
Creating bit map...
3976
 
3977
Bitstream generation is complete.
3978
 
3979
3980
 
3981
3982
 
3983
3984
 
3985
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
3986
 
3987
Done writing Tab View settings to:
3988
 
3989
3990
 
3991
Xilinx EDK 11.2 Build EDK_LS3.47
3992
 
3993
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
3994
 
3995
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
3996
 
3997
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
3998
 
3999
Generating Block Diagram to Buffer
4000
 
4001
Generated Block Diagram SVG
4002
 
4003
At Local date and time: Wed Jul 01 10:06:56 2009
4004
 
4005
4006
 
4007
*********************************************
4008
 
4009
*********************************************
4010
 
4011
-bt implementation/system.bit -o implementation/download.bit
4012
 
4013
bitinit version Xilinx EDK 11.2 Build EDK_LS3.47
4014
 
4015
4016
 
4017
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
4018
 
4019
   hs line 253 - deprecated core for architecture 'virtex5fx'!
4020
 
4021
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m
4022
 
4023
4024
 
4025
4026
 
4027
4028
 
4029
Address Map for Processor ppc440_0
4030
 
4031
  (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC
4032
 
4033
  (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0
4034
 
4035
 
4036
 
4037
  (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0
4038
 
4039
  (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0
4040
 
4041
 
4042
 
4043
  (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0
4044
 
4045
 
4046
 
4047
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
4048
 
4049
 
4050
 
4051
Computing clock values...
4052
 
4053
   'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be
4054
 
4055
   through the clock generator IP.
4056
 
4057
 
4058
 
4059
   performed for IPs connected to that clock port, unless they are connected
4060
 
4061
4062
 
4063
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4064
 
4065
 
4066
 
4067
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4068
 
4069
 
4070
 
4071
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4072
 
4073
 
4074
 
4075
 
4076
 
4077
 
4078
 
4079
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
4080
 
4081
   PARAMETER C_SPLB_DWIDTH value to 128
4082
 
4083
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
4084
 
4085
   PARAMETER C_SPLB_NUM_MASTERS value to 1
4086
 
4087
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
4088
 
4089
   PARAMETER C_SPLB_SMALLEST_MASTER value to 128
4090
 
4091
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
4092
 
4093
   value to 0x2000
4094
 
4095
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
4096
 
4097
   C_PORT_DWIDTH value to 64
4098
 
4099
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
4100
 
4101
   value to 8
4102
 
4103
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01
4104
 
4105
   C_SPLB_DWIDTH value to 128
4106
 
4107
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
4108
 
4109
   value to 128
4110
 
4111
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
4112
 
4113
   value to 128
4114
 
4115
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
4116
 
4117
   value to 128
4118
 
4119
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
4120
 
4121
   value to 128
4122
 
4123
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
4124
 
4125
   value to 128
4126
 
4127
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
4128
 
4129
   C_SPLB_DWIDTH value to 128
4130
 
4131
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
4132
 
4133
   C_SPLB_SMALLEST_MASTER value to 128
4134
 
4135
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
4136
 
4137
   C_MPLB_DWIDTH value to 128
4138
 
4139
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
4140
 
4141
   C_MPLB_SMALLEST_SLAVE value to 128
4142
 
4143
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
4144
 
4145
   C_SPLB_MID_WIDTH value to 1
4146
 
4147
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
4148
 
4149
   C_SPLB_NUM_MASTERS value to 1
4150
 
4151
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
4152
 
4153
   C_SPLB_SMALLEST_MASTER value to 128
4154
 
4155
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
4156
 
4157
   C_SPLB_DWIDTH value to 128
4158
 
4159
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4160
 
4161
   C_PLBV46_NUM_MASTERS value to 1
4162
 
4163
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4164
 
4165
   C_PLBV46_NUM_SLAVES value to 1
4166
 
4167
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4168
 
4169
   C_PLBV46_MID_WIDTH value to 1
4170
 
4171
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4172
 
4173
   value to 128
4174
 
4175
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
4176
 
4177
   PARAMETER C_SPLB_DWIDTH value to 128
4178
 
4179
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
4180
 
4181
   C_SPLB_DWIDTH value to 128
4182
 
4183
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
4184
 
4185
   C_SPLB_MID_WIDTH value to 1
4186
 
4187
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
4188
 
4189
   C_SPLB_NUM_MASTERS value to 1
4190
 
4191
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
4192
 
4193
   value to 128
4194
 
4195
Checking platform address map ...
4196
 
4197
Initializing Memory...
4198
 
4199
data2mem -bm "implementation/system_bd" -bt "implementation/system.bit"  -bd
4200
 
4201
Memory Initialization completed successfully.
4202
 
4203
*********************************************
4204
 
4205
*********************************************
4206
 
4207
Release 11.2 - iMPACT L.46 (nt)
4208
 
4209
Preference Table
4210
 
4211
StartupClock         Auto_Correction
4212
 
4213
KeepSVF              False
4214
 
4215
UseHighz             False
4216
 
4217
UserLevel            Novice
4218
 
4219
svfUseTime           false
4220
 
4221
AutoDetecting cable. Please wait.
4222
 
4223
Checking cable driver.
4224
 
4225
 Driver version: src=2301, dest=2301.
4226
 
4227
13:58:07, version = 900.
4228
 
4229
 Max current requested during enumeration is 300 mA.
4230
 
4231
write (count, cmdBuffer, dataBuffer) failed C0000004.
4232
 
4233
 Setting cable speed to 6 MHz.
4234
 
4235
Firmware version = 2301.
4236
 
4237
Firmware hex file version = 2401.
4238
 
4239
Downloaded firmware version = 2401.
4240
 
4241
 PLD version = 200Dh.
4242
 
4243
INFO:iMPACT:1777 -
4244
 
4245
4246
 
4247
----------------------------------------------------------------------
4248
 
4249
INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.
4250
 
4251
   Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...
4252
 
4253
----------------------------------------------------------------------
4254
 
4255
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
4256
 
4257
4258
 
4259
   Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...
4260
 
4261
----------------------------------------------------------------------
4262
 
4263
'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15
4264
 
4265
4266
 
4267
----------------------------------------------------------------------
4268
 
4269
----------------------------------------------------------------------
4270
 
4271
done.
4272
 
4273
Elapsed time =      0 sec.
4274
 
4275
INFO:iMPACT:1777 -
4276
 
4277
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
4278
 
4279
4280
 
4281
UserID read from the bitstream file = 0xFFFFFFFF.
4282
 
4283
----------------------------------------------------------------------
4284
 
4285
Maximum TCK operating frequency for this device chain: 10000000.
4286
 
4287
Boundary-scan chain validated successfully.
4288
 
4289
4290
 
4291
Reading:   41.02 C
4292
 
4293
Reading:   1.002 V
4294
 
4295
Reading:   2.508 V
4296
 
4297
 Match_cycle = 2.
4298
 
4299
'5': Reading status register contents...
4300
 
4301
Decryptor security set                            :         0
4302
 
4303
DCI matched                                       :         1
4304
 
4305
status of GTS_CFG_B                               :         1
4306
 
4307
status of GHIGH                                   :         1
4308
 
4309
value of MODE pin M1                              :         0
4310
 
4311
Internal signal indicates when housecleaning is completed:         1
4312
 
4313
Internal signal indicates that chip is configured :         1
4314
 
4315
Indicates when ID value written does not match chip ID:         0
4316
 
4317
System Monitor Over-Temperature Alarm             :         0
4318
 
4319
startup_state[19] CFG startup state machine       :         0
4320
 
4321
E-fuse program voltage available                  :         0
4322
 
4323
SPI Flash Type[23] Select                         :         1
4324
 
4325
CFG bus width auto detection result               :         0
4326
 
4327
Reserved                                          :         0
4328
 
4329
IPROG pulsed                                      :         0
4330
 
4331
Indicates that efuse logic is busy                :         0
4332
 
4333
'5': Programmed successfully.
4334
 
4335
----------------------------------------------------------------------
4336
 
4337
----------------------------------------------------------------------
4338
 
4339
----------------------------------------------------------------------
4340
 
4341
----------------------------------------------------------------------
4342
 
4343
INFO:iMPACT:2219 - Status register values:
4344
 
4345
INFO:iMPACT:579 - '5': Completed downloading bit file to device.
4346
 
4347
INFO:iMPACT - '5': Checking done pin....done.
4348
 
4349
4350
 
4351
Done!
4352
 
4353
At Local date and time: Wed Jul 01 10:07:40 2009
4354
 
4355
4356
 
4357
Creating software libraries...
4358
 
4359
libgen -mhs system.mhs -p xc5vfx70tff1136-1  -msg __xps/ise/xmsgprops.lst system.mss
4360
 
4361
Xilinx EDK 11.2 Build EDK_LS3.47
4362
 
4363
4364
 
4365
__xps/ise/xmsgprops.lst system.mss
4366
 
4367
Release 11.2 - psf2Edward EDK_LS3.47 (nt)
4368
 
4369
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
4370
 
4371
   hs line 253 - deprecated core for architecture 'virtex5fx'!
4372
 
4373
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m
4374
 
4375
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
4376
 
4377
   hs line 253 - deprecated core for architecture 'virtex5fx'!
4378
 
4379
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m
4380
 
4381
4382
 
4383
IPNAME:plb_v46 INSTANCE:plb_v46_0 -
4384
 
4385
line 109 - 1 master(s) : 12 slave(s)
4386
 
4387
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs
4388
 
4389
IPNAME:fcb_v20 INSTANCE:ppc440_0_fcb_v20 -
4390
 
4391
 
4392
 
4393
Checking port drivers...
4394
 
4395
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m
4396
 
4397
 
4398
 
4399
4400
 
4401
4402
 
4403
4404
 
4405
4406
 
4407
4408
 
4409
4410
 
4411
4412
 
4413
WARNING:EDK:411 - pcie -
4414
 
4415
   ss line 77 - deprecated driver!
4416
 
4417
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.m
4418
 
4419
INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0:
4420
 
4421
 
4422
 
4423
 
4424
 
4425
  - LEDs_Positions
4426
 
4427
  - Push_Buttons_5Bit
4428
 
4429
  - SRAM
4430
 
4431
  - ppc440_0_apu_fpu_virtex5
4432
 
4433
  - xps_intc_0
4434
 
4435
-- Generating libraries for processor: ppc440_0 --
4436
 
4437
4438
 
4439
Running DRCs.
4440
 
4441
Running post_generate.
4442
 
4443
"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mfpu=dp_full -mcpu=440  -O2 -c"
4444
 
4445
4446
 
4447
"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mfpu=dp_full -mcpu=440  -O2 -c"
4448
 
4449
Compiling common
4450
 
4451
4452
 
4453
Compiling standalone
4454
 
4455
Compiling emaclite
4456
 
4457
Compiling pci
4458
 
4459
Compiling sysace
4460
 
4461
Compiling cpu_ppc440
4462
 
4463
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
4464
 
4465
-D USE_DP_FPU -D GCC_PPC440 -mregnames
4466
 
4467
   text    data     bss     dec     hex filename
4468
 
4469
4470
 
4471
Done!
4472
 
4473
At Local date and time: Wed Jul 01 11:26:01 2009
4474
 
4475
4476
 
4477
Downloading Bitstream onto the target board
4478
 
4479
impact -batch etc/download.cmd
4480
 
4481
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
4482
 
4483
Name                 Setting
4484
 
4485
AutoSignature        False
4486
 
4487
ConcurrentMode       False
4488
 
4489
ConfigOnFailure      Stop
4490
 
4491
MessageLevel         Detailed
4492
 
4493
 
4494
 
4495
 
4496
 
4497
 Driver file xusb_xp2.sys found.
4498
 
4499
 
4500
 
4501
 Cable PID = 0008.
4502
 
4503
Type = 0x0005.
4504
 
4505
 
4506
 
4507
Firmware version = 2401.
4508
 
4509
Firmware hex file version = 2401.
4510
 
4511
 
4512
 
4513
INFO:iMPACT:1777 -
4514
 
4515
4516
 
4517
 
4518
 
4519
----------------------------------------------------------------------
4520
 
4521
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
4522
 
4523
 
4524
 
4525
INFO:iMPACT:501 - '1': Added Device xccace successfully.
4526
 
4527
 
4528
 
4529
 
4530
 
4531
 
4532
 
4533
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
4534
 
4535
----------------------------------------------------------------------
4536
 
4537
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
4538
 
4539
----------------------------------------------------------------------
4540
 
4541
Elapsed time =      1 sec.
4542
 
4543
'5': Loading file 'implementation/download.bit' ...
4544
 
4545
   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
4546
 
4547
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
4548
 
4549
done.
4550
 
4551
----------------------------------------------------------------------
4552
 
4553
----------------------------------------------------------------------
4554
 
4555
Validating chain...
4556
 
4557
5: Device Temperature: Current Reading:   33.15 C, Min. Reading:   30.69 C, Max.
4558
 
4559
5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.
4560
 
4561
5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.502 V, Max.
4562
 
4563
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
4564
 
4565
'5': Programming device...
4566
 
4567
done.
4568
 
4569
CRC error                                         :         0
4570
 
4571
DCM locked                                        :         1
4572
 
4573
End of startup signal from Startup block          :         1
4574
 
4575
status of GWE                                     :         1
4576
 
4577
value of MODE pin M0                              :         1
4578
 
4579
Value of MODE pin M2                              :         1
4580
 
4581
Value driver in from INIT pad                     :         1
4582
 
4583
Value of DONE pin                                 :         1
4584
 
4585
Decryptor error Signal                            :         0
4586
 
4587
startup_state[18] CFG startup state machine       :         0
4588
 
4589
startup_state[20] CFG startup state machine       :         1
4590
 
4591
SPI Flash Type[22] Select                         :         1
4592
 
4593
SPI Flash Type[24] Select                         :         1
4594
 
4595
CFG bus width auto detection result               :         0
4596
 
4597
BPI address wrap around error                     :         0
4598
 
4599
read back crc error                               :         0
4600
 
4601
 Match_cycle = 2.
4602
 
4603
Elapsed time =     11 sec.
4604
 
4605
----------------------------------------------------------------------
4606
 
4607
----------------------------------------------------------------------
4608
 
4609
----------------------------------------------------------------------
4610
 
4611
----------------------------------------------------------------------
4612
 
4613
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
4614
 
4615
INFO:iMPACT - '5': Programing completed successfully.
4616
 
4617
4618
 
4619
4620
 
4621
4622
 
4623
4624
 
4625
4626
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4627
 
4628
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4629
 
4630
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4631
 
4632
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4633
 
4634
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
4635
 
4636
Done.
4637
 
4638
Done.
4639
 
4640
Done.
4641
 
4642
Done.
4643
 
4644
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4645
 
4646
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4647
 
4648
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4649
 
4650
 
4651
 
4652
 
4653
 
4654
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4655
 
4656
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4657
 
4658
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4659
 
4660
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4661
 
4662
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4663
 
4664
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4665
 
4666
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
4667
 
4668
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
4669
 
4670
Done.
4671
 
4672
Done.
4673
 
4674
Done.
4675
 
4676
Writing filter settings....
4677
 
4678
Done writing filter settings to:
4679
 
4680
4681
 
4682
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
4683
 
4684
Xilinx Platform Studio (XPS)
4685
 
4686
4687
 
4688
4689
 
4690
4691
 
4692
 
4693
 
4694
 
4695
 
4696
4697
 
4698
4699
 
4700
4701
 
4702
4703
 
4704
4705
 
4706
4707
 
4708
4709
 
4710
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
4711
 
4712
Done writing Tab View settings to:
4713
 
4714
4715
Xilinx Platform Studio (XPS)
4716
 
4717
4718
 
4719
4720
 
4721
4722
 
4723
4724
 
4725
4726
 
4727
4728
 
4729
4730
 
4731
4732
 
4733
4734
 
4735
4736
 
4737
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
4738
 
4739
 
4740
 
4741
 
4742
 
4743
Xilinx EDK 11.2 Build EDK_LS3.47
4744
 
4745
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
4746
 
4747
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
4748
 
4749
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
4750
 
4751
Generating Block Diagram to Buffer
4752
 
4753
Generated Block Diagram SVG
4754
 
4755
At Local date and time: Wed Jul 01 17:11:24 2009
4756
 
4757
4758
 
4759
Downloading Bitstream onto the target board
4760
 
4761
impact -batch etc/download.cmd
4762
 
4763
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
4764
 
4765
Name                 Setting
4766
 
4767
AutoSignature        False
4768
 
4769
ConcurrentMode       False
4770
 
4771
ConfigOnFailure      Stop
4772
 
4773
MessageLevel         Detailed
4774
 
4775
 
4776
AutoDetecting cable. Please wait.
4777
 
4778
Checking cable driver.
4779
 
4780
 Driver version: src=2301, dest=2301.
4781
 
4782
13:58:07, version = 900.
4783
 
4784
 Max current requested during enumeration is 150 mA.
4785
 
4786
 
4787
 
4788
 
4789
 
4790
 
4791
 
4792
 
4793
 
4794
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6
4795
 
4796
   Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...
4797
 
4798
----------------------------------------------------------------------
4799
 
4800
'1': : Manufacturer's ID = Xilinx xccace, Version : 0
4801
 
4802
INFO:iMPACT:1777 -
4803
 
4804
4805
 
4806
----------------------------------------------------------------------
4807
 
4808
INFO:iMPACT:501 - '1': Added Device xccace successfully.
4809
 
4810
 
4811
 
4812
4813
 
4814
----------------------------------------------------------------------
4815
 
4816
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
4817
 
4818
INFO:iMPACT:1777 -
4819
 
4820
4821
 
4822
----------------------------------------------------------------------
4823
 
4824
----------------------------------------------------------------------
4825
 
4826
done.
4827
 
4828
Elapsed time =      0 sec.
4829
 
4830
 
4831
 
4832
 
4833
 
4834
UserID read from the bitstream file = 0xFFFFFFFF.
4835
 
4836
----------------------------------------------------------------------
4837
 
4838
Maximum TCK operating frequency for this device chain: 10000000.
4839
 
4840
Boundary-scan chain validated successfully.
4841
 
4842
Reading:   42.99 C
4843
 
4844
Reading:   1.002 V
4845
 
4846
Reading:   2.505 V
4847
 
4848
4849
 
4850
 Match_cycle = 2.
4851
 
4852
 
4853
 
4854
 
4855
 
4856
DCI matched                                       :         1
4857
 
4858
status of GTS_CFG_B                               :         1
4859
 
4860
status of GHIGH                                   :         1
4861
 
4862
value of MODE pin M1                              :         0
4863
 
4864
Internal signal indicates when housecleaning is completed:         1
4865
 
4866
Internal signal indicates that chip is configured :         1
4867
 
4868
Indicates when ID value written does not match chip ID:         0
4869
 
4870
System Monitor Over-Temperature Alarm             :         0
4871
 
4872
startup_state[19] CFG startup state machine       :         0
4873
 
4874
 
4875
 
4876
 
4877
 
4878
CFG bus width auto detection result               :         0
4879
 
4880
Reserved                                          :         0
4881
 
4882
IPROG pulsed                                      :         0
4883
 
4884
Indicates that efuse logic is busy                :         0
4885
 
4886
'5': Programmed successfully.
4887
 
4888
----------------------------------------------------------------------
4889
 
4890
----------------------------------------------------------------------
4891
 
4892
----------------------------------------------------------------------
4893
 
4894
INFO:iMPACT:2219 - Status register values:
4895
 
4896
 
4897
 
4898
 
4899
 
4900
----------------------------------------------------------------------
4901
 
4902
4903
 
4904
Done!
4905
 
4906
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
4907
 
4908
Done.
4909
 
4910
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
4911
 
4912
Done.
4913
 
4914
At Local date and time: Wed Jul 01 17:17:34 2009
4915
 
4916
4917
 
4918
 
4919
 
4920
 
4921
 
4922
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
4923
 
4924
Name                 Setting
4925
 
4926
AutoSignature        False
4927
 
4928
ConcurrentMode       False
4929
 
4930
ConfigOnFailure      Stop
4931
 
4932
MessageLevel         Detailed
4933
 
4934
SpiByteSwap          Auto_Correction
4935
 
4936
Connecting to cable (Usb Port - USB21).
4937
 
4938
 Driver file xusb_xp2.sys found.
4939
 
4940
 
4941
 
4942
 
4943
 
4944
Type = 0x0005.
4945
 
4946
 Setting cable speed to 6 MHz.
4947
 
4948
Firmware version = 2401.
4949
 
4950
Firmware hex file version = 2401.
4951
 
4952
 PLD version = 200Dh.
4953
 
4954
INFO:iMPACT:1777 -
4955
 
4956
4957
 
4958
----------------------------------------------------------------------
4959
 
4960
----------------------------------------------------------------------
4961
 
4962
 
4963
 
4964
 
4965
 
4966
INFO:iMPACT:501 - '1': Added Device xccace successfully.
4967
 
4968
----------------------------------------------------------------------
4969
 
4970
'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15
4971
 
4972
----------------------------------------------------------------------
4973
 
4974
----------------------------------------------------------------------
4975
 
4976
done.
4977
 
4978
Elapsed time =      0 sec.
4979
 
4980
INFO:iMPACT:1777 -
4981
 
4982
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
4983
 
4984
 
4985
 
4986
 
4987
 
4988
done.
4989
 
4990
 
4991
 
4992
----------------------------------------------------------------------
4993
 
4994
Validating chain...
4995
 
4996
 
4997
 
4998
5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.996 V, Max.
4999
Reading:   0.999 V
5000
5: VCCAUX Supply: Current Reading:   2.502 V, Min. Reading:   2.502 V, Max.
5001
 
5002
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
5003
5004
'5': Programming device...
5005
 Match_cycle = 2.
5006
done.
5007
'5': Reading status register contents...
5008
CRC error                                         :         0
5009
Decryptor security set                            :         0
5010
DCM locked                                        :         1
5011
DCI matched                                       :         1
5012
End of startup signal from Startup block          :         1
5013
status of GTS_CFG_B                               :         1
5014
status of GWE                                     :         1
5015
status of GHIGH                                   :         1
5016
value of MODE pin M0                              :         1
5017
value of MODE pin M1                              :         0
5018
 
5019
Internal signal indicates when housecleaning is completed:         1
5020
 
5021
 
5022
 
5023
 
5024
 
5025
System Monitor Over-Temperature Alarm             :         0
5026
 
5027
startup_state[19] CFG startup state machine       :         0
5028
 
5029
E-fuse program voltage available                  :         0
5030
 
5031
SPI Flash Type[23] Select                         :         1
5032
 
5033
CFG bus width auto detection result               :         0
5034
 
5035
Reserved                                          :         0
5036
 
5037
IPROG pulsed                                      :         0
5038
 
5039
 
5040
 
5041
'5': Programmed successfully.
5042
 
5043
----------------------------------------------------------------------
5044
 
5045
----------------------------------------------------------------------
5046
 
5047
----------------------------------------------------------------------
5048
 
5049
----------------------------------------------------------------------
5050
 
5051
INFO:iMPACT:2219 - Status register values:
5052
 
5053
INFO:iMPACT:579 - '5': Completed downloading bit file to device.
5054
 
5055
INFO:iMPACT - '5': Checking done pin....done.
5056
 
5057
5058
 
5059
Done!
5060
 
5061
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5062
 
5063
Done.
5064
 
5065
Done.
5066
 
5067
Done.
5068
 
5069
Done.
5070
 
5071
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5072
 
5073
Writing filter settings....
5074
 
5075
Done writing filter settings to:
5076
 
5077
5078
 
5079
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
5080
 
5081
Xilinx Platform Studio (XPS)
5082
 
5083
5084
 
5085
5086
 
5087
5088
 
5089
5090
 
5091
5092
 
5093
5094
 
5095
5096
 
5097
5098
 
5099
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
5100
 
5101
Done writing Tab View settings to:
5102
 
5103
5104
 
5105
 
5106
 
5107
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
5108
 
5109
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
5110
 
5111
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
5112
 
5113
Generating Block Diagram to Buffer
5114
 
5115
 
5116
 
5117
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5118
 
5119
At Local date and time: Wed Jul 01 18:45:58 2009
5120
 
5121
5122
 
5123
Downloading Bitstream onto the target board
5124
 
5125
 
5126
 
5127
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
5128
 
5129
Name                 Setting
5130
 
5131
AutoSignature        False
5132
 
5133
ConcurrentMode       False
5134
 
5135
 
5136
 
5137
MessageLevel         Detailed
5138
 
5139
SpiByteSwap          Auto_Correction
5140
 
5141
Connecting to cable (Usb Port - USB21).
5142
 
5143
 Driver file xusb_xp2.sys found.
5144
 
5145
 
5146
 
5147
 Cable PID = 0008.
5148
 
5149
Type = 0x0005.
5150
 
5151
 Setting cable speed to 6 MHz.
5152
 
5153
Firmware version = 2401.
5154
 
5155
 
5156
 
5157
 PLD version = 200Dh.
5158
 
5159
INFO:iMPACT:1777 -
5160
 
5161
5162
 
5163
----------------------------------------------------------------------
5164
 
5165
 
5166
 
5167
INFO:iMPACT:1777 -
5168
 
5169
5170
 
5171
----------------------------------------------------------------------
5172
 
5173
INFO:iMPACT:501 - '1': Added Device xccace successfully.
5174
 
5175
 
5176
 
5177
5178
 
5179
----------------------------------------------------------------------
5180
 
5181
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
5182
 
5183
INFO:iMPACT:1777 -
5184
 
5185
 
5186
 
5187
----------------------------------------------------------------------
5188
 
5189
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
5190
 
5191
----------------------------------------------------------------------
5192
 
5193
done.
5194
 
5195
 
5196
 
5197
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
5198
 
5199
done.
5200
 
5201
----------------------------------------------------------------------
5202
 
5203
----------------------------------------------------------------------
5204
 
5205
 
5206
 
5207
Validating chain...
5208
 
5209
5: Device Temperature: Current Reading:   42.99 C, Min. Reading:   37.58 C, Max.
5210
 
5211
5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.
5212
 
5213
5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.502 V, Max.
5214
 
5215
 
5216
 
5217
done.
5218
 
5219
CRC error                                         :         0
5220
 
5221
DCM locked                                        :         1
5222
 
5223
End of startup signal from Startup block          :         1
5224
 
5225
 
5226
 
5227
value of MODE pin M0                              :         1
5228
 
5229
Value of MODE pin M2                              :         1
5230
 
5231
Value driver in from INIT pad                     :         1
5232
 
5233
Value of DONE pin                                 :         1
5234
 
5235
 
5236
 
5237
startup_state[18] CFG startup state machine       :         0
5238
 
5239
startup_state[20] CFG startup state machine       :         1
5240
 
5241
SPI Flash Type[22] Select                         :         1
5242
 
5243
SPI Flash Type[24] Select                         :         1
5244
 
5245
 
5246
 
5247
BPI address wrap around error                     :         0
5248
 
5249
read back crc error                               :         0
5250
 
5251
 Match_cycle = 2.
5252
 
5253
Elapsed time =     11 sec.
5254
 
5255
 
5256
 
5257
----------------------------------------------------------------------
5258
 
5259
----------------------------------------------------------------------
5260
 
5261
----------------------------------------------------------------------
5262
 
5263
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
5264
 
5265
INFO:iMPACT - '5': Programing completed successfully.
5266
 
5267
5268
 
5269
5270
 
5271
 
5272
 
5273
 
5274
 
5275
5276
 
5277
5278
 
5279
 
5280
 
5281
Done writing Tab View settings to:
5282
 
5283
5284
 
5285
 
5286
 
5287
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
5288
 
5289
 
5290
 
5291
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
5292
 
5293
Generating Block Diagram to Buffer
5294
 
5295
Generated Block Diagram SVG
5296
 
5297
At Local date and time: Thu Jul 02 09:58:07 2009
5298
 
5299
5300
 
5301
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
5302
 
5303
powerpc-eabi-size RTOSDemo/executable.elf
5304
 
5305
  51202     372   87844  139418   2209a RTOSDemo/executable.elf
5306
 
5307
5308
 
5309
5310
 
5311
 
5312
 
5313
 
5314
 
5315
*********************************************
5316
 
5317
 
5318
 
5319
Preference Table
5320
 
5321
 
5322
 
5323
 
5324
 
5325
UseHighz             False
5326
 
5327
UserLevel            Novice
5328
 
5329
svfUseTime           false
5330
 
5331
AutoDetecting cable. Please wait.
5332
 
5333
Checking cable driver.
5334
 
5335
 Driver version: src=2301, dest=2301.
5336
 
5337
13:58:07, version = 900.
5338
 
5339
 Max current requested during enumeration is 300 mA.
5340
 
5341
write (count, cmdBuffer, dataBuffer) failed C0000004.
5342
 
5343
 Setting cable speed to 6 MHz.
5344
 
5345
Firmware version = 2301.
5346
 
5347
Firmware hex file version = 2401.
5348
 
5349
 
5350
 
5351
 PLD version = 200Dh.
5352
 
5353
INFO:iMPACT:1777 -
5354
 
5355
5356
 
5357
 
5358
 
5359
 
5360
 
5361
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
5362
 
5363
INFO:iMPACT:1777 -
5364
 
5365
INFO:iMPACT:501 - '1': Added Device xccace successfully.
5366
 
5367
----------------------------------------------------------------------
5368
 
5369
'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15
5370
 
5371
   Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...
5372
 
5373
5374
 
5375
----------------------------------------------------------------------
5376
 
5377
----------------------------------------------------------------------
5378
 
5379
done.
5380
 
5381
Elapsed time =      0 sec.
5382
 
5383
 
5384
 
5385
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
5386
 
5387
 
5388
 
5389
 
5390
 
5391
 
5392
 
5393
Maximum TCK operating frequency for this device chain: 10000000.
5394
 
5395
Boundary-scan chain validated successfully.
5396
 
5397
Reading:   32.66 C
5398
 
5399
 
5400
 
5401
 
5402
 
5403
5404
 
5405
 Match_cycle = 2.
5406
 
5407
'5': Reading status register contents...
5408
 
5409
Decryptor security set                            :         0
5410
 
5411
DCI matched                                       :         1
5412
 
5413
status of GTS_CFG_B                               :         1
5414
 
5415
status of GHIGH                                   :         1
5416
 
5417
value of MODE pin M1                              :         0
5418
 
5419
Internal signal indicates when housecleaning is completed:         1
5420
 
5421
Internal signal indicates that chip is configured :         1
5422
 
5423
 
5424
 
5425
System Monitor Over-Temperature Alarm             :         0
5426
 
5427
 
5428
 
5429
 
5430
 
5431
SPI Flash Type[23] Select                         :         1
5432
 
5433
CFG bus width auto detection result               :         0
5434
 
5435
Reserved                                          :         0
5436
 
5437
 
5438
 
5439
 
5440
 
5441
'5': Programmed successfully.
5442
 
5443
----------------------------------------------------------------------
5444
 
5445
----------------------------------------------------------------------
5446
 
5447
----------------------------------------------------------------------
5448
 
5449
----------------------------------------------------------------------
5450
 
5451
INFO:iMPACT:2219 - Status register values:
5452
 
5453
INFO:iMPACT:579 - '5': Completed downloading bit file to device.
5454
 
5455
INFO:iMPACT - '5': Checking done pin....done.
5456
 
5457
5458
 
5459
Done!
5460
 
5461
 
5462
 
5463
 
5464
 
5465
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
5466
 
5467
 
5468
 
5469
 
5470
 
5471
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
5472
 
5473
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
5474
 
5475
At Local date and time: Thu Jul 02 10:23:31 2009
5476
 
5477
 
5478
 
5479
 
5480
 
5481
powerpc-eabi-size RTOSDemo/executable.elf
5482
 
5483
  50962     372   87844  139178   21faa RTOSDemo/executable.elf
5484
 
5485
5486
 
5487
5488
 
5489
5490
 
5491
5492
 
5493
 make -f system.make download started...
5494
 
5495
*********************************************
5496
 
5497
*********************************************
5498
 
5499
Release 11.2 - iMPACT L.46 (nt)
5500
 
5501
Preference Table
5502
 
5503
 
5504
 
5505
 
5506
 
5507
 
5508
 
5509
UserLevel            Novice
5510
 
5511
svfUseTime           false
5512
 
5513
AutoDetecting cable. Please wait.
5514
 
5515
 
5516
 
5517
 
5518
 
5519
13:58:07, version = 900.
5520
 
5521
 Max current requested during enumeration is 300 mA.
5522
 
5523
 Cable Type = 3, Revision = 0.
5524
 
5525
Cable connection established.
5526
 
5527
File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.
5528
 
5529
PLD file version = 200Dh.
5530
 
5531
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6
5532
 
5533
   Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...
5534
 
5535
----------------------------------------------------------------------
5536
 
5537
'1': : Manufacturer's ID = Xilinx xccace, Version : 0
5538
 
5539
 
5540
 
5541
 
5542
 
5543
 
5544
 
5545
 
5546
 
5547
INFO:iMPACT:1777 -
5548
 
5549
 
5550
 
5551
----------------------------------------------------------------------
5552
 
5553
 
5554
 
5555
 
5556
 
5557
----------------------------------------------------------------------
5558
 
5559
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
5560
 
5561
----------------------------------------------------------------------
5562
 
5563
Elapsed time =      1 sec.
5564
 
5565
'5': Loading file 'implementation/download.bit' ...
5566
 
5567
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
5568
 
5569
done.
5570
 
5571
----------------------------------------------------------------------
5572
 
5573
----------------------------------------------------------------------
5574
 
5575
Validating chain...
5576
 
5577
5: Device Temperature: Current Reading:   41.02 C, Min. Reading:   36.10 C, Max.
5578
 
5579
 
5580
 
5581
5: VCCAUX Supply: Current Reading:   2.502 V, Min. Reading:   2.502 V, Max.
5582
 
5583
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
5584
 
5585
'5': Programming device...
5586
 
5587
done.
5588
 
5589
 
5590
 
5591
 
5592
 
5593
End of startup signal from Startup block          :         1
5594
 
5595
status of GWE                                     :         1
5596
 
5597
value of MODE pin M0                              :         1
5598
 
5599
Value of MODE pin M2                              :         1
5600
 
5601
Value driver in from INIT pad                     :         1
5602
 
5603
Value of DONE pin                                 :         1
5604
 
5605
Decryptor error Signal                            :         0
5606
 
5607
startup_state[18] CFG startup state machine       :         0
5608
 
5609
startup_state[20] CFG startup state machine       :         1
5610
 
5611
SPI Flash Type[22] Select                         :         1
5612
 
5613
SPI Flash Type[24] Select                         :         1
5614
 
5615
CFG bus width auto detection result               :         0
5616
 
5617
 
5618
 
5619
 
5620
 
5621
 Match_cycle = 2.
5622
 
5623
Elapsed time =     11 sec.
5624
 
5625
----------------------------------------------------------------------
5626
 
5627
 
5628
 
5629
 
5630
 
5631
----------------------------------------------------------------------
5632
 
5633
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
5634
 
5635
INFO:iMPACT - '5': Programing completed successfully.
5636
 
5637
5638
 
5639
5640
 
5641
5642
 
5643
5644
 
5645
5646
 
5647
 make -f system.make program started...
5648
 
5649
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
5650
 
5651
 
5652
 
5653
   text    data     bss     dec     hex filename
5654
 
5655
 
5656
 
5657
Done!
5658
 
5659
Done.
5660
 
5661
At Local date and time: Thu Jul 02 11:19:46 2009
5662
 
5663
 
5664
 
5665
 
5666
 
5667
powerpc-eabi-size RTOSDemo/executable.elf
5668
 
5669
  50970     372   87852  139194   21fba RTOSDemo/executable.elf
5670
 
5671
5672
 
5673
5674
 
5675
5676
 
5677
 make -f system.make program started...
5678
 
5679
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
5680
 
5681
-D USE_DP_FPU -D GCC_PPC440 -mregnames
5682
 
5683
   text    data     bss     dec     hex filename
5684
 
5685
5686
 
5687
 
5688
 
5689
 
5690
 
5691
 
5692
 
5693
5694
 
5695
 
5696
 
5697
powerpc-eabi-size RTOSDemo/executable.elf
5698
 
5699
 
5700
 
5701
 
5702
 
5703
5704
 
5705
5706
 
5707
 make -f system.make program started...
5708
 
5709
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
5710
 
5711
-D USE_DP_FPU -D GCC_PPC440 -mregnames
5712
 
5713
   text    data     bss     dec     hex filename
5714
 
5715
5716
 
5717
Done!
5718
 
5719
Done.
5720
 
5721
At Local date and time: Thu Jul 02 11:55:33 2009
5722
 
5723
 
5724
 
5725
 
5726
 
5727
 
5728
 
5729
 
5730
 
5731
5732
 
5733
 
5734
 
5735
5736
 
5737
 
5738
 
5739
 
5740
 
5741
-D USE_DP_FPU -D GCC_PPC440 -mregnames
5742
 
5743
   text    data     bss     dec     hex filename
5744
 
5745
5746
 
5747
Done!
5748
 
5749
Done.
5750
 
5751
At Local date and time: Thu Jul 02 13:29:26 2009
5752
 
5753
5754
 
5755
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
5756
 
5757
powerpc-eabi-size RTOSDemo/executable.elf
5758
 
5759
  51242     372   87852  139466   220ca RTOSDemo/executable.elf
5760
 
5761
 
5762
 
5763
 
5764
 
5765
 
5766
 
5767
 
5768
 
5769
 
5770
 
5771
 
5772
 
5773
 
5774
 
5775
Preference Table
5776
 
5777
 
5778
 
5779
KeepSVF              False
5780
 
5781
 
5782
 
5783
 
5784
 
5785
svfUseTime           false
5786
 
5787
AutoDetecting cable. Please wait.
5788
 
5789
Checking cable driver.
5790
 
5791
 Driver version: src=2301, dest=2301.
5792
 
5793
13:58:07, version = 900.
5794
 
5795
 Max current requested during enumeration is 300 mA.
5796
 
5797
 Cable Type = 3, Revision = 0.
5798
 
5799
Cable connection established.
5800
 
5801
File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.
5802
 
5803
PLD file version = 200Dh.
5804
 
5805
 
5806
 
5807
 
5808
 
5809
----------------------------------------------------------------------
5810
 
5811
 
5812
 
5813
5814
 
5815
 
5816
 
5817
 
5818
 
5819
INFO:iMPACT:501 - '1': Added Device xccace successfully.
5820
 
5821
INFO:iMPACT:1777 -
5822
 
5823
5824
 
5825
----------------------------------------------------------------------
5826
 
5827
----------------------------------------------------------------------
5828
 
5829
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
5830
 
5831
INFO:iMPACT:1777 -
5832
 
5833
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
5834
 
5835
----------------------------------------------------------------------
5836
 
5837
done.
5838
 
5839
 
5840
 
5841
 
5842
 
5843
 
5844
 
5845
----------------------------------------------------------------------
5846
 
5847
 
5848
 
5849
Validating chain...
5850
 
5851
 
5852
 
5853
 
5854
 
5855
5: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.493 V, Max.
5856
 
5857
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
5858
 
5859
'5': Programming device...
5860
 
5861
done.
5862
 
5863
CRC error                                         :         0
5864
 
5865
DCM locked                                        :         1
5866
 
5867
End of startup signal from Startup block          :         1
5868
 
5869
status of GWE                                     :         1
5870
 
5871
value of MODE pin M0                              :         1
5872
 
5873
Value of MODE pin M2                              :         1
5874
 
5875
 
5876
 
5877
Value of DONE pin                                 :         1
5878
 
5879
 
5880
 
5881
startup_state[18] CFG startup state machine       :         0
5882
 
5883
 
5884
 
5885
SPI Flash Type[22] Select                         :         1
5886
 
5887
SPI Flash Type[24] Select                         :         1
5888
 
5889
CFG bus width auto detection result               :         0
5890
 
5891
BPI address wrap around error                     :         0
5892
 
5893
 
5894
 
5895
 
5896
 
5897
Elapsed time =     11 sec.
5898
 
5899
----------------------------------------------------------------------
5900
 
5901
 
5902
 
5903
 
5904
 
5905
----------------------------------------------------------------------
5906
 
5907
 
5908
 
5909
INFO:iMPACT - '5': Programing completed successfully.
5910
 
5911
5912
 
5913
 
5914
 
5915
5916
 
5917
5918
 
5919
 
5920
 
5921
5922
 
5923
 make -f system.make download started...
5924
5925
*********************************************
5926
Downloading Bitstream onto the target board
5927
 
5928
impact -batch etc/download.cmd
5929
Release 11.2 - iMPACT L.46 (nt)
5930
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
5931
Preference Table
5932
Name                 Setting
5933
StartupClock         Auto_Correction
5934
AutoSignature        False
5935
KeepSVF              False
5936
ConcurrentMode       False
5937
UseHighz             False
5938
ConfigOnFailure      Stop
5939
UserLevel            Novice
5940
MessageLevel         Detailed
5941
svfUseTime           false
5942
SpiByteSwap          Auto_Correction
5943
AutoDetecting cable. Please wait.
5944
Connecting to cable (Usb Port - USB21).
5945
Checking cable driver.
5946
 Driver file xusb_xp2.sys found.
5947
 Driver version: src=2301, dest=2301.
5948
 Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS
5949
13:58:07, version = 900.
5950
 Cable PID = 0008.
5951
 
5952
Type = 0x0005.
5953
 Cable Type = 3, Revision = 0.
5954
 Setting cable speed to 6 MHz.
5955
Cable connection established.
5956
Firmware version = 2401.
5957
File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.
5958
Firmware hex file version = 2401.
5959
PLD file version = 200Dh.
5960
 PLD version = 200Dh.
5961
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6
5962
INFO:iMPACT:1777 -
5963
 
5964
5965
----------------------------------------------------------------------
5966
----------------------------------------------------------------------
5967
'1': : Manufacturer's ID = Xilinx xccace, Version : 0
5968
INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.
5969
5970
----------------------------------------------------------------------
5971
----------------------------------------------------------------------
5972
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
5973
INFO:iMPACT:1777 -
5974
   Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...
5975
INFO:iMPACT:501 - '1': Added Device xccace successfully.
5976
5977
----------------------------------------------------------------------
5978
----------------------------------------------------------------------
5979
'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15
5980
INFO:iMPACT:1777 -
5981
   Reading c:/devtools/Xilinx/11.1/ISE/xc9500xl/data/xc95144xl.bsd...
5982
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
5983
5984
----------------------------------------------------------------------
5985
----------------------------------------------------------------------
5986
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
5987
----------------------------------------------------------------------
5988
----------------------------------------------------------------------
5989
done.
5990
Elapsed time =      1 sec.
5991
Elapsed time =      0 sec.
5992
'5': Loading file 'implementation/download.bit' ...
5993
INFO:iMPACT:1777 -
5994
   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
5995
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
5996
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
5997
5998
done.
5999
UserID read from the bitstream file = 0xFFFFFFFF.
6000
----------------------------------------------------------------------
6001
----------------------------------------------------------------------
6002
----------------------------------------------------------------------
6003
Maximum TCK operating frequency for this device chain: 10000000.
6004
Validating chain...
6005
Boundary-scan chain validated successfully.
6006
5: Device Temperature: Current Reading:   73.02 C, Min. Reading:   70.06 C, Max.
6007
 
6008
5: VCCINT Supply: Current Reading:   0.993 V, Min. Reading:   0.993 V, Max.
6009
Reading:   0.999 V
6010
5: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.493 V, Max.
6011
Reading:   2.502 V
6012
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
6013
6014
'5': Programming device...
6015
 Match_cycle = 2.
6016
done.
6017
'5': Reading status register contents...
6018
CRC error                                         :         0
6019
Decryptor security set                            :         0
6020
DCM locked                                        :         1
6021
DCI matched                                       :         1
6022
End of startup signal from Startup block          :         1
6023
status of GTS_CFG_B                               :         1
6024
status of GWE                                     :         1
6025
status of GHIGH                                   :         1
6026
value of MODE pin M0                              :         1
6027
value of MODE pin M1                              :         0
6028
 
6029
Internal signal indicates when housecleaning is completed:         1
6030
Value driver in from INIT pad                     :         1
6031
Internal signal indicates that chip is configured :         1
6032
Value of DONE pin                                 :         1
6033
Indicates when ID value written does not match chip ID:         0
6034
Decryptor error Signal                            :         0
6035
System Monitor Over-Temperature Alarm             :         0
6036
startup_state[18] CFG startup state machine       :         0
6037
startup_state[19] CFG startup state machine       :         0
6038
startup_state[20] CFG startup state machine       :         1
6039
E-fuse program voltage available                  :         0
6040
SPI Flash Type[22] Select                         :         1
6041
 
6042
SPI Flash Type[24] Select                         :         1
6043
CFG bus width auto detection result               :         0
6044
CFG bus width auto detection result               :         0
6045
Reserved                                          :         0
6046
BPI address wrap around error                     :         0
6047
IPROG pulsed                                      :         0
6048
 
6049
Indicates that efuse logic is busy                :         0
6050
 Match_cycle = 2.
6051
'5': Programmed successfully.
6052
Elapsed time =     12 sec.
6053
----------------------------------------------------------------------
6054
----------------------------------------------------------------------
6055
----------------------------------------------------------------------
6056
----------------------------------------------------------------------
6057
----------------------------------------------------------------------
6058
----------------------------------------------------------------------
6059
----------------------------------------------------------------------
6060
 
6061
INFO:iMPACT:2219 - Status register values:
6062
 
6063
 
6064
 
6065
INFO:iMPACT - '5': Checking done pin....done.
6066
 
6067
6068
 
6069
 
6070
 
6071
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
6072
 
6073
At Local date and time: Thu Jul 02 13:38:54 2009
6074
 
6075
 
6076
 
6077
6078
 
6079
Done!
6080
 
6081
 
6082
 
6083
6084
 
6085
6086
 
6087
 
6088
 
6089
At Local date and time: Thu Jul 02 13:39:21 2009
6090
 
6091
6092
 
6093
 
6094
 
6095
powerpc-eabi-size RTOSDemo/executable.elf
6096
 
6097
  50774     372   87852  138998   21ef6 RTOSDemo/executable.elf
6098
 
6099
6100
 
6101
6102
 
6103
 
6104
 
6105
 make -f system.make program started...
6106
 
6107
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
6108
 
6109
-D USE_DP_FPU -D GCC_PPC440 -mregnames
6110
 
6111
   text    data     bss     dec     hex filename
6112
 
6113
6114
 
6115
Done!
6116
 
6117
At Local date and time: Thu Jul 02 13:53:08 2009
6118
 
6119
6120
 
6121
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
6122
 
6123
powerpc-eabi-size RTOSDemo/executable.elf
6124
 
6125
  50542     372   87860  138774   21e16 RTOSDemo/executable.elf
6126
 
6127
6128
 
6129
6130
 
6131
6132
 
6133
 make -f system.make program started...
6134
 
6135
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
6136
 
6137
-D USE_DP_FPU -D GCC_PPC440 -mregnames
6138
 
6139
   text    data     bss     dec     hex filename
6140
 
6141
6142
 
6143
Done!
6144
 
6145
At Local date and time: Thu Jul 02 14:20:50 2009
6146
 
6147
6148
 
6149
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
6150
 
6151
powerpc-eabi-size RTOSDemo/executable.elf
6152
 
6153
  50298     372   87852  138522   21d1a RTOSDemo/executable.elf
6154
 
6155
6156
 
6157
 
6158
 
6159
 make -f system.make program started...
6160
 
6161
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
6162
 
6163
-D USE_DP_FPU -D GCC_PPC440 -mregnames
6164
 
6165
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c:426: error: 'tskTCB' has no member named 'xEventTaskList'
6166
 
6167
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
6168
 
6169
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1543: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6170
 
6171
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
6172
 
6173
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
6174
 
6175
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
6176
 
6177
 
6178
 
6179
6180
 
6181
6182
 
6183
6184
 
6185
 make -f system.make program started...
6186
 
6187
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
6188
 
6189
-D USE_DP_FPU -D GCC_PPC440 -mregnames
6190
 
6191
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c:426: error: 'tskTCB' has no member named 'xEventList'
6192
 
6193
 
6194
 
6195
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1543: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6196
 
6197
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
6198
 
6199
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
6200
 
6201
6202
 
6203
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:839: warning: assignment from incompatible pointer type
6204
 
6205
make: *** [RTOSDemo/executable.elf] Error 1
6206
 
6207
 
6208
 
6209
Done!
6210
 
6211
At Local date and time: Thu Jul 02 15:32:24 2009
6212
 
6213
6214
 
6215
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
6216
 
6217
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
6218
 
6219
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1543: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6220
 
6221
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
6222
 
6223
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
6224
 
6225
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
6226
 
6227
6228
 
6229
   text    data     bss     dec     hex filename
6230
 
6231
6232
 
6233
Done!
6234
 
6235
At Local date and time: Thu Jul 02 15:38:48 2009
6236
 
6237
6238
 
6239
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
6240
 
6241
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c: In function 'vTaskSwitchContext':
6242
 
6243
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1549: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6244
 
6245
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: 'xSecondary' undeclared (first use in this function)
6246
 
6247
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1591: error: for each function it appears in.)
6248
 
6249
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
6250
 
6251
 
6252
 
6253
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
6254
 
6255
6256
 
6257
 
6258
 
6259
6260
 
6261
6262
 
6263
 make -f system.make program started...
6264
 
6265
 
6266
 
6267
-D USE_DP_FPU -D GCC_PPC440 -mregnames
6268
 
6269
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1548: warning: passing argument 1 of 'vApplicationStackOverflowHook' from incompatible pointer type
6270
 
6271
 
6272
 
6273
 
6274
 
6275
 
6276
 
6277
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGiveMutexRecursive':
6278
 
6279
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueTakeMutexRecursive':
6280
 
6281
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c: In function 'xQueueGenericReceive':
6282
 
6283
6284
 
6285
6286
 
6287
6288
 
6289
6290
 
6291
 make -f system.make program started...
6292
 
6293
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
6294
 
6295
 
6296
 
6297
 
6298
 
6299
6300
 
6301
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:348: warning: comparison of distinct pointer types lacks a cast
6302
 
6303
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c:394: warning: comparison of distinct pointer types lacks a cast
6304
 
6305
 
6306
 
6307
powerpc-eabi-size RTOSDemo/executable.elf
6308
 
6309
  51334     372   87852  139558   22126 RTOSDemo/executable.elf
6310
 
6311
6312
 
6313
6314
 
6315
 
6316
 
6317
 
6318
 
6319
*********************************************
6320
 
6321
Release 11.2 - iMPACT L.46 (nt)
6322
 
6323
 
6324
 
6325
StartupClock         Auto_Correction
6326
 
6327
KeepSVF              False
6328
 
6329
UseHighz             False
6330
 
6331
UserLevel            Novice
6332
 
6333
 
6334
 
6335
AutoDetecting cable. Please wait.
6336
 
6337
 
6338
 
6339
 
6340
 
6341
 
6342
 
6343
 Max current requested during enumeration is 300 mA.
6344
 
6345
 
6346
 
6347
Cable connection established.
6348
 
6349
File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.
6350
 
6351
PLD file version = 200Dh.
6352
 
6353
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6
6354
 
6355
   Reading c:/devtools/Xilinx/11.1/ISE/virtex5/data/xc5vfx70t.bsd...
6356
 
6357
----------------------------------------------------------------------
6358
 
6359
'1': : Manufacturer's ID = Xilinx xccace, Version : 0
6360
 
6361
 
6362
 
6363
INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.
6364
 
6365
   Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...
6366
 
6367
6368
 
6369
 
6370
 
6371
----------------------------------------------------------------------
6372
 
6373
'3': : Manufacturer's ID = Xilinx xcf32p, Version : 15
6374
 
6375
 
6376
 
6377
----------------------------------------------------------------------
6378
 
6379
done.
6380
 
6381
 
6382
 
6383
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
6384
 
6385
   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
6386
 
6387
 
6388
 
6389
done.
6390
 
6391
----------------------------------------------------------------------
6392
 
6393
 
6394
 
6395
Validating chain...
6396
 
6397
5: Device Temperature: Current Reading:   69.08 C, Min. Reading:   66.62 C, Max.
6398
 
6399
5: VCCINT Supply: Current Reading:   0.993 V, Min. Reading:   0.990 V, Max.
6400
 
6401
5: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.493 V, Max.
6402
 
6403
 
6404
 
6405
'5': Programming device...
6406
 
6407
done.
6408
 
6409
 
6410
 
6411
DCM locked                                        :         1
6412
 
6413
End of startup signal from Startup block          :         1
6414
 
6415
status of GWE                                     :         1
6416
 
6417
value of MODE pin M0                              :         1
6418
 
6419
Value of MODE pin M2                              :         1
6420
 
6421
 
6422
 
6423
Value of DONE pin                                 :         1
6424
 
6425
Decryptor error Signal                            :         0
6426
 
6427
 
6428
 
6429
startup_state[20] CFG startup state machine       :         1
6430
 
6431
SPI Flash Type[22] Select                         :         1
6432
 
6433
SPI Flash Type[24] Select                         :         1
6434
 
6435
CFG bus width auto detection result               :         0
6436
 
6437
 
6438
 
6439
read back crc error                               :         0
6440
 
6441
 Match_cycle = 2.
6442
 
6443
 
6444
 
6445
 
6446
 
6447
----------------------------------------------------------------------
6448
 
6449
----------------------------------------------------------------------
6450
 
6451
 
6452
 
6453
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
6454
 
6455
INFO:iMPACT - '5': Programing completed successfully.
6456
 
6457
 
6458
 
6459
6460
 
6461
6462
 
6463
6464
 
6465
 make -f system.make program started...
6466
 
6467
make: Nothing to be done for `program'.
6468
 
6469
6470
 
6471
6472
 
6473
 make -f system.make program started...
6474
 
6475
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
6476
 
6477
-D USE_DP_FPU -D GCC_PPC440 -mregnames
6478
 
6479
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c:426: warning: dereferencing 'void *' pointer
6480
 
6481
 
6482
 
6483
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:844: warning: dereferencing 'void *' pointer
6484
 
6485
6486
 
6487
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1593: error: invalid operands to binary ==
6488
 
6489
 
6490
 
6491
6492
 
6493
 
6494
 
6495
At Local date and time: Thu Jul 02 15:55:43 2009
6496
 
6497
 
6498
 
6499
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
6500
 
6501
 
6502
 
6503
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:844: error: request for member 'xEventListItem' in something not a structure or union
6504
 
6505
 
6506
 
6507
6508
 
6509
 
6510
 
6511
6512
 
6513
 
6514
 
6515
 make -f system.make program started...
6516
 
6517
 
6518
 
6519
-D USE_DP_FPU -D GCC_PPC440 -mregnames
6520
 
6521
 
6522
 
6523
make: *** [RTOSDemo/executable.elf] Error 1
6524
 
6525
 
6526
 
6527
Done!
6528
 
6529
 
6530
 
6531
6532
 
6533
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
6534
 
6535
powerpc-eabi-size RTOSDemo/executable.elf
6536
 
6537
 
6538
 
6539
6540
 
6541
6542
 
6543
 
6544
 
6545
 make -f system.make program started...
6546
 
6547
 
6548
 
6549
-D USE_DP_FPU -D GCC_PPC440 -mregnames
6550
 
6551
 
6552
 
6553
6554
 
6555
 
6556
 
6557
At Local date and time: Thu Jul 02 16:32:08 2009
6558
 
6559
6560
 
6561
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
6562
 
6563
 
6564
 
6565
  51878     372   87852  140102   22346 RTOSDemo/executable.elf
6566
 
6567
6568
 
6569
6570
 
6571
6572
 
6573
6574
 
6575
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
6576
 
6577
Done writing Tab View settings to:
6578
 
6579
6580
 
6581
Xilinx EDK 11.2 Build EDK_LS3.47
6582
 
6583
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
6584
 
6585
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
6586
 
6587
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
6588
 
6589
Generating Block Diagram to Buffer
6590
 
6591
Generated Block Diagram SVG
6592
 
6593
At Local date and time: Thu Jul 02 17:37:11 2009
6594
 
6595
6596
 
6597
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
6598
 
6599
powerpc-eabi-size RTOSDemo/executable.elf
6600
 
6601
  51910     372   87852  140134   22366 RTOSDemo/executable.elf
6602
 
6603
6604
 
6605
6606
 
6607
 make -f system.make download started...
6608
 
6609
*********************************************
6610
 
6611
*********************************************
6612
 
6613
Release 11.2 - iMPACT L.46 (nt)
6614
 
6615
Preference Table
6616
 
6617
StartupClock         Auto_Correction
6618
 
6619
KeepSVF              False
6620
 
6621
UseHighz             False
6622
 
6623
UserLevel            Novice
6624
 
6625
svfUseTime           false
6626
 
6627
AutoDetecting cable. Please wait.
6628
 
6629
Checking cable driver.
6630
 
6631
 Driver version: src=2301, dest=2301.
6632
 
6633
13:58:07, version = 900.
6634
 
6635
 Max current requested during enumeration is 300 mA.
6636
 
6637
write (count, cmdBuffer, dataBuffer) failed C0000004.
6638
 
6639
 Setting cable speed to 6 MHz.
6640
 
6641
Firmware version = 2301.
6642
 
6643
Firmware hex file version = 2401.
6644
 
6645
Downloaded firmware version = 2401.
6646
 
6647
 PLD version = 200Dh.
6648
 
6649
INFO:iMPACT:1777 -
6650
 
6651
6652
 
6653
----------------------------------------------------------------------
6654
 
6655
INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.
6656
 
6657
   Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...
6658
 
6659
----------------------------------------------------------------------
6660
 
6661
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
6662
 
6663
6664
INFO:iMPACT:1777 -
6665
 
6666
6667
 
6668
----------------------------------------------------------------------
6669
 
6670
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
6671
 
6672
----------------------------------------------------------------------
6673
 
6674
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
6675
 
6676
----------------------------------------------------------------------
6677
 
6678
Elapsed time =      2 sec.
6679
 
6680
'5': Loading file 'implementation/download.bit' ...
6681
 
6682
   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
6683
 
6684
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
6685
 
6686
done.
6687
 
6688
----------------------------------------------------------------------
6689
 
6690
----------------------------------------------------------------------
6691
 
6692
Validating chain...
6693
 
6694
5: Device Temperature: Current Reading:   42.99 C, Min. Reading:   37.58 C, Max.
6695
 
6696
5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.
6697
 
6698
5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.502 V, Max.
6699
 
6700
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
6701
 
6702
'5': Programming device...
6703
 
6704
done.
6705
 
6706
CRC error                                         :         0
6707
 
6708
DCM locked                                        :         1
6709
 
6710
End of startup signal from Startup block          :         1
6711
 
6712
status of GWE                                     :         1
6713
 
6714
value of MODE pin M0                              :         1
6715
 
6716
Value of MODE pin M2                              :         1
6717
 
6718
Value driver in from INIT pad                     :         1
6719
 
6720
Value of DONE pin                                 :         1
6721
 
6722
Decryptor error Signal                            :         0
6723
 
6724
startup_state[18] CFG startup state machine       :         0
6725
 
6726
startup_state[20] CFG startup state machine       :         1
6727
 
6728
SPI Flash Type[22] Select                         :         1
6729
 
6730
SPI Flash Type[24] Select                         :         1
6731
 
6732
CFG bus width auto detection result               :         0
6733
 
6734
BPI address wrap around error                     :         0
6735
 
6736
read back crc error                               :         0
6737
 
6738
 Match_cycle = 2.
6739
 
6740
Elapsed time =     11 sec.
6741
 
6742
----------------------------------------------------------------------
6743
 
6744
----------------------------------------------------------------------
6745
 
6746
----------------------------------------------------------------------
6747
 
6748
----------------------------------------------------------------------
6749
 
6750
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
6751
 
6752
INFO:iMPACT - '5': Programing completed successfully.
6753
 
6754
6755
 
6756
6757
 
6758
 
6759
 
6760
6761
 
6762
6763
 
6764
 make -f system.make program started...
6765
 
6766
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
6767
 
6768
 
6769
 
6770
   text    data     bss     dec     hex filename
6771
 
6772
 
6773
 
6774
Done!
6775
 
6776
 
6777
 
6778
At Local date and time: Thu Jul 02 20:25:21 2009
6779
 
6780
6781
 
6782
 
6783
 
6784
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'xTaskCheckForTimeOut':
6785
 
6786
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:71: error: (Each undeclared identifier is reported only once
6787
 
6788
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:77: error: 'pdTRUE' undeclared (first use in this function)
6789
 
6790
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: At top level:
6791
 
6792
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:83: warning: previous implicit declaration of 'vTaskSetTimeOutState' was here
6793
 
6794
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:97: error: 'xNumOfOverflows' undeclared (first use in this function)
6795
 
6796
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:109: warning: comparison is always true due to limited range of data type
6797
 
6798
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:116: error: expected expression before 'xTimeOutType'
6799
 
6800
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:134: warning: incompatible implicit declaration of built-in function 'printf'
6801
 
6802
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:150: warning: incompatible implicit declaration of built-in function 'printf'
6803
 
6804
make: *** [RTOSDemo/executable.elf] Error 1
6805
 
6806
6807
 
6808
Done!
6809
 
6810
At Local date and time: Thu Jul 02 20:27:35 2009
6811
 
6812
6813
 
6814
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
6815
 
6816
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:53:19: error: conio.h: No such file or directory
6817
 
6818
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:113: warning: comparison is always true due to limited range of data type
6819
 
6820
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:184: warning: incompatible implicit declaration of built-in function 'exit'
6821
 
6822
make: *** [RTOSDemo/executable.elf] Error 1
6823
 
6824
6825
 
6826
Done!
6827
 
6828
At Local date and time: Thu Jul 02 20:28:16 2009
6829
 
6830
6831
 
6832
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
6833
 
6834
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6835
 
6836
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:113: warning: comparison is always true due to limited range of data type
6837
 
6838
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:144: warning: incompatible implicit declaration of built-in function 'printf'
6839
 
6840
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:157: warning: incompatible implicit declaration of built-in function 'printf'
6841
 
6842
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:181: warning: incompatible implicit declaration of built-in function 'printf'
6843
 
6844
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:105: warning: return type of 'main' is not 'int'
6845
 
6846
/
6847
 
6848
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:71: multiple definition of `vTaskSetTimeOutState'
6849
 
6850
/cygdrive/c/devtools/Xilinx/11.1/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc/powerpc-eabi/4.1.1/../../../../powerpc-eabi/bin/ld: Warning: size of symbol `vTaskSetTimeOutState' changed from 68 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccwVIJA2.o to 72 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o
6851
 
6852
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:77: multiple definition of `xTaskCheckForTimeOut'
6853
 
6854
/cygdrive/c/devtools/Xilinx/11.1/EDK/gnu/powerpc-eabi/nt/bin/../lib/gcc/powerpc-eabi/4.1.1/../../../../powerpc-eabi/bin/ld: Warning: size of symbol `xTaskCheckForTimeOut' changed from 388 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccwVIJA2.o to 276 in /cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o
6855
 
6856
tasks.c:(.text+0x1798): undefined reference to `vApplicationStackOverflowHook'
6857
 
6858
/cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccpw6KfT.o: In function `main':
6859
 
6860
main.c:(.text+0x304): undefined reference to `getch'
6861
 
6862
make: *** [RTOSDemo/executable.elf] Error 1
6863
 
6864
6865
 
6866
Done!
6867
 
6868
At Local date and time: Thu Jul 02 20:31:20 2009
6869
 
6870
6871
 
6872
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
6873
 
6874
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6875
 
6876
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
6877
 
6878
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:105: warning: return type of 'main' is not 'int'
6879
 
6880
/cygdrive/c/DOCUME~1/RICHAR~1.DOM/LOCALS~1/Temp/ccZOTZW1.o: In function `vTaskSwitchContext':
6881
 
6882
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c:1557: undefined reference to `vApplicationStackOverflowHook'
6883
 
6884
make: *** [RTOSDemo/executable.elf] Error 1
6885
 
6886
6887
 
6888
Done!
6889
 
6890
At Local date and time: Thu Jul 02 20:31:50 2009
6891
 
6892
6893
 
6894
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
6895
 
6896
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6897
 
6898
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:123: warning: comparison is always true due to limited range of data type
6899
 
6900
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
6901
 
6902
powerpc-eabi-size RTOSDemo/executable.elf
6903
 
6904
  50578     368   87832  138778   21e1a RTOSDemo/executable.elf
6905
 
6906
6907
 
6908
6909
 
6910
 make -f system.make program started...
6911
 
6912
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
6913
 
6914
-D USE_DP_FPU -D GCC_PPC440 -mregnames
6915
 
6916
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
6917
 
6918
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:148: warning: incompatible implicit declaration of built-in function 'printf'
6919
 
6920
6921
 
6922
   text    data     bss     dec     hex filename
6923
 
6924
6925
 
6926
Done!
6927
 
6928
Done.
6929
 
6930
At Local date and time: Thu Jul 02 20:38:30 2009
6931
 
6932
6933
 
6934
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
6935
 
6936
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6937
 
6938
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:123: warning: comparison is always true due to limited range of data type
6939
 
6940
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
6941
 
6942
powerpc-eabi-size RTOSDemo/executable.elf
6943
 
6944
  50706     368   87832  138906   21e9a RTOSDemo/executable.elf
6945
 
6946
6947
 
6948
6949
 
6950
 make -f system.make program started...
6951
 
6952
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
6953
 
6954
-D USE_DP_FPU -D GCC_PPC440 -mregnames
6955
 
6956
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
6957
 
6958
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:151: warning: incompatible implicit declaration of built-in function 'printf'
6959
 
6960
6961
 
6962
   text    data     bss     dec     hex filename
6963
 
6964
6965
 
6966
Done!
6967
 
6968
Done.
6969
 
6970
At Local date and time: Thu Jul 02 20:43:10 2009
6971
 
6972
6973
 
6974
    -mfpu=dp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
6975
 
6976
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c: In function 'main':
6977
 
6978
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
6979
 
6980
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
6981
 
6982
powerpc-eabi-size RTOSDemo/executable.elf
6983
 
6984
  50730     368   87840  138938   21eba RTOSDemo/executable.elf
6985
 
6986
6987
 
6988
6989
 
6990
 make -f system.make program started...
6991
 
6992
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
6993
 
6994
-D USE_DP_FPU -D GCC_PPC440 -mregnames
6995
 
6996
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
6997
 
6998
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
6999
 
7000
powerpc-eabi-size RTOSDemo/executable.elf
7001
 
7002
  50694     368   87840  138902   21e96 RTOSDemo/executable.elf
7003
 
7004
7005
 
7006
7007
 
7008
7009
 
7010
 make -f system.make program started...
7011
 
7012
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
7013
 
7014
-D USE_DP_FPU -D GCC_PPC440 -mregnames
7015
 
7016
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
7017
 
7018
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
7019
 
7020
powerpc-eabi-size RTOSDemo/executable.elf
7021
 
7022
  50730     368   87840  138938   21eba RTOSDemo/executable.elf
7023
 
7024
7025
 
7026
7027
 
7028
7029
 
7030
 make -f system.make program started...
7031
 
7032
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
7033
 
7034
-D USE_DP_FPU -D GCC_PPC440 -mregnames
7035
 
7036
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
7037
 
7038
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
7039
 
7040
powerpc-eabi-size RTOSDemo/executable.elf
7041
 
7042
  50802     368   87832  139002   21efa RTOSDemo/executable.elf
7043
 
7044
7045
 
7046
7047
 
7048
7049
 
7050
 make -f system.make program started...
7051
 
7052
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
7053
 
7054
-D USE_DP_FPU -D GCC_PPC440 -mregnames
7055
 
7056
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:120: warning: comparison is always true due to limited range of data type
7057
 
7058
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
7059
 
7060
powerpc-eabi-size RTOSDemo/executable.elf
7061
 
7062
  50846     368   87832  139046   21f26 RTOSDemo/executable.elf
7063
 
7064
7065
 
7066
7067
 
7068
7069
 
7070
 make -f system.make program started...
7071
 
7072
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
7073
 
7074
-D USE_DP_FPU -D GCC_PPC440 -mregnames
7075
 
7076
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:122: warning: comparison is always true due to limited range of data type
7077
 
7078
/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c:108: warning: return type of 'main' is not 'int'
7079
 
7080
powerpc-eabi-size RTOSDemo/executable.elf
7081
 
7082
  50866     368   87832  139066   21f3a RTOSDemo/executable.elf
7083
 
7084
7085
 
7086
7087
 
7088
7089
 
7090
 make -f system.make program started...
7091
 
7092
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
7093
 
7094
-D USE_DP_FPU -D GCC_PPC440 -mregnames
7095
 
7096
   text    data     bss     dec     hex filename
7097
 
7098
7099
 
7100
Done!
7101
 
7102
Done.
7103
 
7104
Done.
7105
 
7106
At Local date and time: Fri Jul 03 02:08:31 2009
7107
 
7108
7109
 
7110
Downloading Bitstream onto the target board
7111
 
7112
impact -batch etc/download.cmd
7113
 
7114
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
7115
 
7116
Name                 Setting
7117
 
7118
AutoSignature        False
7119
 
7120
ConcurrentMode       False
7121
 
7122
ConfigOnFailure      Stop
7123
 
7124
MessageLevel         Detailed
7125
 
7126
SpiByteSwap          Auto_Correction
7127
 
7128
Connecting to cable (Usb Port - USB21).
7129
 
7130
 Driver file xusb_xp2.sys found.
7131
 
7132
 Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS
7133
 
7134
 Cable PID = 0008.
7135
 
7136
Type = 0x0005.
7137
 
7138
 Setting cable speed to 6 MHz.
7139
 
7140
Firmware version = 2401.
7141
 
7142
Firmware hex file version = 2401.
7143
 
7144
 PLD version = 200Dh.
7145
 
7146
INFO:iMPACT:1777 -
7147
 
7148
7149
 
7150
----------------------------------------------------------------------
7151
 
7152
----------------------------------------------------------------------
7153
 
7154
 
7155
 
7156
 
7157
 
7158
INFO:iMPACT:501 - '1': Added Device xccace successfully.
7159
 
7160
INFO:iMPACT:1777 -
7161
 
7162
7163
 
7164
----------------------------------------------------------------------
7165
 
7166
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
7167
 
7168
   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
7169
 
7170
----------------------------------------------------------------------
7171
 
7172
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
7173
 
7174
----------------------------------------------------------------------
7175
 
7176
Elapsed time =      1 sec.
7177
 
7178
'5': Loading file 'implementation/download.bit' ...
7179
 
7180
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
7181
 
7182
done.
7183
 
7184
----------------------------------------------------------------------
7185
 
7186
----------------------------------------------------------------------
7187
 
7188
 
7189
 
7190
5: Device Temperature: Current Reading:   38.07 C, Min. Reading:   35.12 C, Max.
7191
 
7192
5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.
7193
 
7194
5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.502 V, Max.
7195
 
7196
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
7197
 
7198
'5': Programming device...
7199
 
7200
done.
7201
 
7202
CRC error                                         :         0
7203
 
7204
DCM locked                                        :         1
7205
 
7206
End of startup signal from Startup block          :         1
7207
 
7208
status of GWE                                     :         1
7209
 
7210
value of MODE pin M0                              :         1
7211
 
7212
Value of MODE pin M2                              :         1
7213
 
7214
Value driver in from INIT pad                     :         1
7215
 
7216
Value of DONE pin                                 :         1
7217
 
7218
Decryptor error Signal                            :         0
7219
 
7220
startup_state[18] CFG startup state machine       :         0
7221
 
7222
startup_state[20] CFG startup state machine       :         1
7223
 
7224
SPI Flash Type[22] Select                         :         1
7225
 
7226
 
7227
 
7228
CFG bus width auto detection result               :         0
7229
 
7230
BPI address wrap around error                     :         0
7231
 
7232
read back crc error                               :         0
7233
 
7234
 
7235
 
7236
 
7237
 
7238
----------------------------------------------------------------------
7239
 
7240
 
7241
 
7242
----------------------------------------------------------------------
7243
 
7244
 
7245
 
7246
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
7247
 
7248
 
7249
 
7250
7251
 
7252
7253
 
7254
7255
 
7256
7257
 
7258
7259
 
7260
7261
 
7262
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
7263
 
7264
 
7265
 
7266
7267
 
7268
 
7269
 
7270
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
7271
 
7272
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
7273
 
7274
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
7275
 
7276
 
7277
 
7278
Generated Block Diagram SVG
7279
 
7280
At Local date and time: Fri Jul 03 18:19:28 2009
7281
 
7282
7283
 
7284
 
7285
 
7286
impact -batch etc/download.cmd
7287
 
7288
 
7289
 
7290
 
7291
 
7292
 
7293
 
7294
ConcurrentMode       False
7295
 
7296
 
7297
 
7298
 
7299
 
7300
 
7301
 
7302
Connecting to cable (Usb Port - USB21).
7303
 
7304
 Driver file xusb_xp2.sys found.
7305
 
7306
 Driver windrvr6.sys version = 9.0.0.0. WinDriver v9.00 Jungo (c) 1997 - 2007 Build Date: Mar 27 2007 X86 32bit SYS
7307
 
7308
 Cable PID = 0008.
7309
 
7310
Type = 0x0005.
7311
 
7312
 Setting cable speed to 6 MHz.
7313
 
7314
 
7315
 
7316
 
7317
 
7318
 PLD version = 200Dh.
7319
 
7320
INFO:iMPACT:1777 -
7321
 
7322
7323
 
7324
----------------------------------------------------------------------
7325
 
7326
----------------------------------------------------------------------
7327
 
7328
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
7329
 
7330
INFO:iMPACT:1777 -
7331
 
7332
INFO:iMPACT:501 - '1': Added Device xccace successfully.
7333
 
7334
INFO:iMPACT:1777 -
7335
 
7336
 
7337
 
7338
----------------------------------------------------------------------
7339
 
7340
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
7341
 
7342
INFO:iMPACT:1777 -
7343
 
7344
7345
 
7346
----------------------------------------------------------------------
7347
 
7348
----------------------------------------------------------------------
7349
 
7350
done.
7351
 
7352
Elapsed time =      0 sec.
7353
 
7354
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
7355
 
7356
 
7357
 
7358
UserID read from the bitstream file = 0xFFFFFFFF.
7359
 
7360
 
7361
 
7362
 
7363
 
7364
Boundary-scan chain validated successfully.
7365
 
7366
Reading:   74.99 C
7367
 
7368
Reading:   1.002 V
7369
 
7370
Reading:   2.505 V
7371
 
7372
7373
 
7374
 Match_cycle = 2.
7375
 
7376
 
7377
 
7378
Decryptor security set                            :         0
7379
 
7380
DCI matched                                       :         1
7381
 
7382
status of GTS_CFG_B                               :         1
7383
 
7384
status of GHIGH                                   :         1
7385
 
7386
value of MODE pin M1                              :         0
7387
 
7388
Internal signal indicates when housecleaning is completed:         1
7389
 
7390
Internal signal indicates that chip is configured :         1
7391
 
7392
 
7393
 
7394
 
7395
 
7396
startup_state[19] CFG startup state machine       :         0
7397
 
7398
E-fuse program voltage available                  :         0
7399
 
7400
 
7401
 
7402
CFG bus width auto detection result               :         0
7403
 
7404
 
7405
 
7406
IPROG pulsed                                      :         0
7407
 
7408
 
7409
 
7410
'5': Programmed successfully.
7411
 
7412
----------------------------------------------------------------------
7413
 
7414
----------------------------------------------------------------------
7415
 
7416
----------------------------------------------------------------------
7417
 
7418
----------------------------------------------------------------------
7419
 
7420
 
7421
 
7422
 
7423
 
7424
INFO:iMPACT - '5': Checking done pin....done.
7425
 
7426
7427
 
7428
 
7429
 
7430
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
7431
 
7432
 
7433
 
7434
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
7435
 
7436
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
7437
 
7438
At Local date and time: Fri Jul 03 18:20:05 2009
7439
 
7440
 
7441
 
7442
 
7443
 
7444
powerpc-eabi-size RTOSDemo/executable.elf
7445
 
7446
  44758     372   87852  132982   20776 RTOSDemo/executable.elf
7447
7448
7449
 
7450
7451
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_DP_FPU_Xilinx_Virtex5_GCC/; exit;"
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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
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7464
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
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Done writing Tab View settings to:
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7478
 make -f system.make hwclean started...
7479
 
7480
rm -f implementation/system.ngc
7481
 
7482
rm -f __xps/ise/_xmsgs/platgen.xmsgs
7483
 
7484
rm -f implementation/system.bit
7485
 
7486
rm -f implementation/system_bd.bmm
7487
 
7488
rm -f __xps/system_routed
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7490
rm -rf xst.srp system.srp
7491
 
7492
7493
 
7494
Done!
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7496
At Local date and time: Sun Jul 05 09:37:10 2009
7497
 
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7500
rm -f libgen.log
7501
 
7502
rm -f RTOSDemo/executable.elf
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7510
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_DP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
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Done writing Tab View settings to:
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