URL https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC440_SP_FPU_Xilinx_Virtex5_GCC/] [system.log] - Blame information for rev 586

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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
 
Generating Block Diagram to Buffer
 
Generated Block Diagram SVG
 
The project file (XMP) has changed on disk.
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
 
At Local date and time: Tue Jun 30 18:34:41 2009
 make -f system.make hwclean started...
 
rm -f implementation/system.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f __xps/system_routed
rm -rf implementation synthesis xst hdl
rm -rf xst.srp system.srp
rm -f __xps/ise/_xmsgs/bitinit.xmsgs
 
 
Done!
 
At Local date and time: Tue Jun 30 18:34:46 2009
 make -f system.make bitsclean started...
 
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f __xps/system_routed
 
 
Done!
 
At Local date and time: Tue Jun 30 18:34:52 2009
 make -f system.make netlistclean started...
 
rm -f implementation/system.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
 
 
Done!
 
At Local date and time: Tue Jun 30 18:34:57 2009
 make -f system.make libsclean started...
 
rm -rf ppc440_0/
rm -f libgen.log
rm -f __xps/ise/_xmsgs/libgen.xmsgs
 
 
Done!
 
At Local date and time: Tue Jun 30 18:35:02 2009
 make -f system.make programclean started...
 
rm -f RTOSDemo/executable.elf
 
 
Done!
 
At Local date and time: Tue Jun 30 18:35:08 2009
 make -f system.make swclean started...
 
rm -rf ppc440_0/
rm -f libgen.log
rm -f __xps/ise/_xmsgs/libgen.xmsgs
rm -f RTOSDemo/executable.elf
 
 
Done!
 
Writing filter settings....
 
Done writing filter settings to:
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
 
Done writing Tab View settings to:
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
 
Xilinx Platform Studio (XPS)
Xilinx EDK 11.2 Build EDK_LS3.47
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
 
Generating Block Diagram to Buffer
 
Generated Block Diagram SVG
 
At Local date and time: Fri Jul 03 21:23:32 2009
 make -f system.make bits started...
 
****************************************************
Creating system netlist for hardware specification..
****************************************************
platgen -p xc5vfx70tff1136-1 -lang vhdl   -msg __xps/ise/xmsgprops.lst system.mhs
 
 
 (nt)
 

 
Command Line: platgen -p xc5vfx70tff1136-1 -lang vhdl -msg
 
 
 
 
 

 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
 
 
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
 
   hs line 253 - deprecated core for architecture 'virtex5fx'!
 
 
 

 

 

 
Address Map for Processor ppc440_0
 
  (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC
 
  (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0
 
  (0x81440000-0x8144ffff) LEDs_8Bit     plb_v46_0
 
  (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0
 
  (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0
 
  (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0
 
  (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0
 
  (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
 
 
 
Computing clock values...
 
 
 
   through the clock generator IP.
 
 
 
   performed for IPs connected to that clock port, unless they are connected
 

 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_SLAVES value to 12
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   value to 0x2000
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   C_PORT_DWIDTH value to 64
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   value to 8
 
 
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
 
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
 
 
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
 
   C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_MPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_MPLB_SMALLEST_SLAVE value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_SLAVES value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
 
   PARAMETER C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
 
   value to 128
 
Checking platform address map ...
 
Checking platform configuration ...
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m
 
   performance.
 
   The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs
 
   operation.
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
 
line 290 - 1 master(s) : 1 slave(s)
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 

 
WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
 
   hs line 462 - floating connection!
 
Performing Clock DRCs...
 
Performing Reset DRCs...
 
Overriding system level properties...
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
 
   C_PPC440MC_ADDR_BASE value to 0x00000000
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
 
   C_PPC440MC_ADDR_HIGH value to 0x0fffffff
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_0
 
   C_NUM_PPC_USED value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
 
   value to 0b00000000000000000000000000000001
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
 
   value to 0b00000000000000000000000000000001
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
 
   value to 0b00000000000000000000000000000000
 
Running system level update procedures...
 
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
 
Running system level DRCs...
 
Performing System level DRCs on properties...
 
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
 
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
 
implementation/pcie_bridge_wrapper/pcie_bridge_wrapper.ucf.
 

 

 
implementation/ethernet_mac_wrapper/ethernet_mac_wrapper.ucf.
 

 

 
implementation/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ucf.
 

 

 
Modify defaults ...
 
Creating stub ...
 
Processing licensed instances ...
 

 

 
IPNAME:plbv46_pcie INSTANCE:pcie_bridge -
 
line 253 - Copying (BBD-specified) netlist files.
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
IPNAME:apu_fpu_virtex5 INSTANCE:ppc440_0_apu_fpu_virtex5 -
 
line 401 - Copying (BBD-specified) netlist files.
 
Managing cache ...
 
Elaborating instances ...
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 

 

 
Completion time: 2.00 seconds
 
Constructing platform-level connectivity ...
 

 

 

 

 

 
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
 
INSTANCE:ppc440_0 -
 
line 78 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:xps_bram_if_cntlr_1 -
 
line 118 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:rs232_uart_1 -
 
line 138 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:leds_positions -
 
line 168 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:dip_switches_8bit -
 
line 196 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:sram -
 
line 223 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:ppc440_0_splb0 -
 
line 290 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:ddr2_sdram -
 
line 317 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:ppc440_0_fcb_v20 -
 
line 394 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:clock_generator_0 -
 
line 408 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
INSTANCE:proc_sys_reset_0 -
 
line 453 - Running XST synthesis
 
 
 

 
 
 
line 78 - Running NGCBUILD
 
 with local file
 

 
xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..
 

 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa
 

 

 
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
NGCBUILD Design Results Summary:
 
  Number of warnings:   0
 
Writing NGC file "../ppc440_0_wrapper.ngc" ...
 
Total CPU time to NGCBUILD completion:   5 sec
 
Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...
 
NGCBUILD done.
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
 
 

 
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
 
../rs232_uart_1_wrapper.ngc
 
Reading NGO file
 
 
 
Partition Implementation Status
 
 
 

 
 
 
  Number of errors:     0
 

 
Total REAL time to NGCBUILD completion:  2 sec
 

 

 
IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -
 
line 253 - Running NGCBUILD
 
 with local file
 

 
xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..
 

 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa
 
Executing edif2ngd -noa
 
tion\pcie_bridge_wrapper_fifo_generator_v4_3.edn"
 
Release 11.2 - edif2ngd L.46 (nt)
 
INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)
 
PMSPEC -- Overriding Xilinx file 
 
Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...
 
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa
 
Loading design module
 
Loading design module
 
tion\pcie_bridge_wrapper/dpram_70_512.ngc"...
 
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa
 

 

 
 
 
  No Partitions were found in this design.
 
 
 
NGCBUILD Design Results Summary:
 
 
 
Writing NGC file "../pcie_bridge_wrapper.ngc" ...
 
 
 
Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...
 
 
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
 
 

 
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
 
ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc
 
 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa
 
 
 
 
 
 
 
 
 
Writing module to "ethernetlite_v1_01_b_dmem_v2.ngo"...
 
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa
 
 
Applying constraints in "ethernet_mac_wrapper.ucf" to the design...
 
 
 
 
 
 
 
 
 
  Number of errors:     0
 

 
 
Total CPU time to NGCBUILD completion:   5 sec
 
 
 
 
 
 
 
 
 
 
 
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
 
 
 
Reading NGO file
 
 
 
Applying constraints in "ddr2_sdram_wrapper.ucf" to the design...
 
Partition Implementation Status
 
 
 

 
 
 
  Number of errors:     0
 

 
Total REAL time to NGCBUILD completion:  6 sec
 

 

 
IPNAME:ppc440_0_apu_fpu_virtex5_wrapper INSTANCE:ppc440_0_apu_fpu_virtex5 -
 
line 401 - Running NGCBUILD
 
 with local file
 

 
xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_apu_fpu_virtex5_wrapper.ucf -sd
 
 
 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa
 
 
 
tion\ppc440_0_apu_fpu_virtex5_wrapper/apu_fpu_sp_lo.ngc"...
 
Applying constraints in "ppc440_0_apu_fpu_virtex5_wrapper.ucf" to the design...
 
Partition Implementation Status
 

 
 
 

 
 
 

 
Total REAL time to NGCBUILD completion:  6 sec
 
 
 

 
IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 -
 
 
 
 with local file
 
 
 
xc5vfx70tff1136-1 -intstyle silent -sd .. xps_intc_0_wrapper.ngc
 
 
 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa
 
 
 
-------------------------------
 
 
 
-------------------------------
 
NGCBUILD Design Results Summary:
 
  Number of warnings:   0
 
Writing NGC file "../xps_intc_0_wrapper.ngc" ...
 
Total CPU time to NGCBUILD completion:   1 sec
 
Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...
 
NGCBUILD done.
 
Rebuilding cache ...
 
Total run time: 1330.00 seconds
 
bash -c "cd synthesis; ./synthesis.sh"
 
Running XST synthesis ...
 
Release 11.2 - ngcbuild L.46 (nt)
 
Overriding Xilinx file  with local file
 

 
./system.ngc ../implementation/system.ngc -sd ../implementation -i -ise
 

 
"c:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/synthesis/
 
Loading design module "../implementation/ppc440_0_wrapper.ngc"...
 
Loading design module "../implementation/xps_bram_if_cntlr_1_wrapper.ngc"...
 
"../implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc"...
 
Loading design module "../implementation/leds_8bit_wrapper.ngc"...
 
Loading design module "../implementation/push_buttons_5bit_wrapper.ngc"...
 
Loading design module "../implementation/iic_eeprom_wrapper.ngc"...
 
Loading design module "../implementation/pcie_bridge_wrapper.ngc"...
 
Loading design module "../implementation/ethernet_mac_wrapper.ngc"...
 
Loading design module "../implementation/sysace_compactflash_wrapper.ngc"...
 
Loading design module
 
Loading design module "../implementation/clock_generator_0_wrapper.ngc"...
 
Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...
 

 
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
NGCBUILD Design Results Summary:
 
  Number of warnings:   0
 
Writing NGC file "../implementation/system.ngc" ...
 
Total CPU time to NGCBUILD completion:   11 sec
 
Writing NGCBUILD log file "../implementation/system.blc"...
 
NGCBUILD done.
 
Running Xilinx Implementation tools..
 
xflow -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise ../__xps/ise/system.ise system.ngc
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
../__xps/ise/system.ise system.ngc
 
 with local file
 
.... Copying flowfile c:/devtools/Xilinx/11.1/ISE/xilinx/data/fpga.flw into
 
C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementat
 

 
C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementat
 
Using Option File(s):
 
tion/xflow.opt
 
Creating Script File ...
 
#----------------------------------------------#
 
# ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm
 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa
 
#----------------------------------------------#
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
 with local file
 

 
timestamp -bm system.bmm
 
ion/system.ngc -uc system.ucf system.ngd
 
Reading NGO file
 
tion/system.ngc" ...
 
Done.
 
Applying constraints in "system.ucf" to the design...
 
   'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_
 
   'VIRTEX5' to correct post-ngdbuild and timing simulation for this primitive.
 
   should be changed in this same manner in the source netlist or constraint
 
Resolving constraint associations...
 
WARNING:ConstraintSystem:3 - Constraint 
 
 
 
   found.
 
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
 
   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
 
   PLL_ADV output(s):
 
   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *
 

 
   'TS_sys_clk_pin', was traced into PLL_ADV instance
 
 
 
   CLKOUT1: 
 
   1.25 HIGH 50%>
 
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
 
 
 
   PLL_ADV output(s):
 
   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *
 

 
 
 
   The following new TNM groups and period specifications were generated at the
 
 
 
   2 HIGH 50%>
 
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
 
 
 
   PLL_ADV output(s):
 
 
 

 
 
 
Processing BMM file ...
 
WARNING:NgdBuild:1212 - User specified non-default attribute value
 
   "clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".
 
 
 
Checking expanded design ...
 
   'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_
 
   has unconnected output pin
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   RE_I' has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
 
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   ' has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
 
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   ' has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
 
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   has unconnected output pin
 
 
 
   ' has unconnected output pin
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   _H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected
   output pin
WARNING:NgdBuild:443 - SFF primitive
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
 
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
 
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
 
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
 
WARNING:NgdBuild:443 - SFF primitive
 
   SIZE2_REG1' has unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
 
WARNING:NgdBuild:443 - SFF primitive
 
   unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'
 
WARNING:NgdBuild:440 - FF primitive
 
   /gen_rden[1].u_calib_rden_r' has unconnected output pin
 
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
 
WARNING:NgdBuild:440 - FF primitive
 
   /gen_rden[3].u_calib_rden_r' has unconnected output pin
 
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
 
WARNING:NgdBuild:440 - FF primitive
 
   /gen_rden[5].u_calib_rden_r' has unconnected output pin
 
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
 
WARNING:NgdBuild:440 - FF primitive
 
   /gen_rden[7].u_calib_rden_r' has unconnected output pin
 
   "clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"
 
WARNING:NgdBuild:452 - logical net 'N194' has no driver
 
WARNING:NgdBuild:452 - logical net 'N196' has no driver
 
WARNING:NgdBuild:452 - logical net 'N198' has no driver
 
WARNING:NgdBuild:452 - logical net 'N200' has no driver
 
WARNING:NgdBuild:452 - logical net 'N202' has no driver
 
WARNING:NgdBuild:452 - logical net 'N204' has no driver
 
WARNING:NgdBuild:452 - logical net 'N206' has no driver
 
WARNING:NgdBuild:452 - logical net 'N208' has no driver
 
WARNING:NgdBuild:452 - logical net 'N210' has no driver
 
WARNING:NgdBuild:452 - logical net 'N212' has no driver
 
WARNING:NgdBuild:452 - logical net 'N214' has no driver
 
WARNING:NgdBuild:452 - logical net 'N216' has no driver
 
WARNING:NgdBuild:452 - logical net 'N218' has no driver
 
WARNING:NgdBuild:452 - logical net 'N220' has no driver
 
WARNING:NgdBuild:452 - logical net 'N222' has no driver
 
WARNING:NgdBuild:452 - logical net 'N224' has no driver
 
WARNING:NgdBuild:452 - logical net 'N226' has no driver
 
WARNING:NgdBuild:452 - logical net 'N228' has no driver
 
WARNING:NgdBuild:452 - logical net 'N230' has no driver
 
WARNING:NgdBuild:452 - logical net 'N232' has no driver
 
WARNING:NgdBuild:452 - logical net 'N234' has no driver
 
WARNING:NgdBuild:452 - logical net 'N236' has no driver
 
WARNING:NgdBuild:452 - logical net 'N238' has no driver
 
WARNING:NgdBuild:452 - logical net 'N240' has no driver
 
WARNING:NgdBuild:452 - logical net 'N242' has no driver
 
WARNING:NgdBuild:452 - logical net 'N244' has no driver
 
WARNING:NgdBuild:452 - logical net 'N246' has no driver
 
WARNING:NgdBuild:452 - logical net 'N248' has no driver
 
WARNING:NgdBuild:452 - logical net 'N250' has no driver
 
WARNING:NgdBuild:452 - logical net 'N252' has no driver
 
WARNING:NgdBuild:452 - logical net 'N254' has no driver
 
WARNING:NgdBuild:452 - logical net 'N256' has no driver
 
WARNING:NgdBuild:452 - logical net 'N266' has no driver
 
WARNING:NgdBuild:452 - logical net 'N268' has no driver
 
WARNING:NgdBuild:452 - logical net 'N270' has no driver
 
WARNING:NgdBuild:452 - logical net 'N272' has no driver
 
WARNING:NgdBuild:452 - logical net 'N306' has no driver
 
WARNING:NgdBuild:452 - logical net 'N308' has no driver
 
WARNING:NgdBuild:452 - logical net 'N310' has no driver
 
WARNING:NgdBuild:452 - logical net 'N312' has no driver
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'
 

 
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
NGDBUILD Design Results Summary:
 
  Number of warnings: 348
 
Writing NGD file "system.ngd" ...
 
Total CPU time to NGDBUILD completion:  1 min  21 sec
 
Writing NGDBUILD log file "system.bld"...
 
NGDBUILD done.
 

 
#----------------------------------------------#
 
# map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing
 
#----------------------------------------------#
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
 with local file
 
Using target part "5vfx70tff1136-1".
 
WARNING:LIT:395 - The above warning message is repeated 1028 more times for the
 
   N195,
 
   N197,
 
   N199
 
Mapping design into LUTs...
 
   connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has
 
WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top
 
WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been
 
Writing file system_map.ngm...
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
 
   of frag REGCLKAU connected to power/ground net
 
   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
 
   of frag REGCLKAL connected to power/ground net
 
   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
 
   of frag REGCLKAU connected to power/ground net
 
   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
 
   of frag REGCLKAL connected to power/ground net
 
   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
 
   of frag RDRCLKU connected to power/ground net
 
   x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
 
   of frag RDRCLKL connected to power/ground net
 
   x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
 
   noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
 
   noeccerr.SDP_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
 
   noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
 
   noeccerr.SDP_RDRCLKL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
 
   ram/SDP.WIDE_PRIM36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
 
   ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
 
   ram/SDP.WIDE_PRIM36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
 
   ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
 
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
 
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
 
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
 
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
 
   36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
 
   36.noeccerr.SDP_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
 
   36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
 
   36.noeccerr.SDP_RDRCLKL_tiesig
 
Running delay-based LUT packing...
 
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM
 
   timing analysis.
 
   (.mrp).
 
Total REAL time at the beginning of Placer: 2 mins 41 secs
 

 
Phase 1.1  Initial Placement Analysis (Checksum:9d0c7baf) REAL time: 3 mins 15 secs
 
Phase 2.7  Design Feasibility Check
 
   Components associated with this bus are as follows:
 
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6>   IOSTANDARD = LVCMOS25
 
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4>   IOSTANDARD = LVCMOS18
 
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2>   IOSTANDARD = LVCMOS18
 
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0>   IOSTANDARD = LVCMOS18
 

 
   Components associated with this bus are as follows:
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<30>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<28>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<26>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<24>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<22>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<20>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<18>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<16>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<14>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<12>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<10>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<8>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<6>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<4>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<2>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<0>   IOSTANDARD = LVCMOS33
 

 

 
Phase 3.31  Local Placement Optimization (Checksum:dec56134) REAL time: 3 mins 16 secs
 
Phase 4.37  Local Placement Optimization
 

 
Phase 5.33  Local Placement Optimization (Checksum:dec56134) REAL time: 13 mins
 
Phase 6.32  Local Placement Optimization
 

 

 

 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
 
|                                          |                                          |
 
| CLOCKREGION_X0Y6:                        | CLOCKREGION_X1Y6:                        |
 
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
 
|   0 center BUFIOs available, 0 in use    |                                          |
 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
 
|                                          |                                          |
 
| CLOCKREGION_X0Y4:                        | CLOCKREGION_X1Y4:                        |
 
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
 
|   2 center BUFIOs available, 0 in use    |                                          |
 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
 
|                                          |                                          |
 
| CLOCKREGION_X0Y2:                        | CLOCKREGION_X1Y2:                        |
 
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
 
|   2 center BUFIOs available, 0 in use    |                                          |
 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
      |
 
|   0 center BUFIOs available, 0 in use    |                                          |
 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
 
|                                          |                                          |
 

 
Clock-Region: 
 
|-----------------------------------------------------------------------------------------------------------------------------------------------------------
 
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
 
|       | Upper Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region
 
|       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region
 
|       | Lower Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region
 
| clock |    region   |                                                                                      -----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 

 
  key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4
 
----
 
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
 
|       | Upper Region|   8  |  0  |  0 |   60   |   60   |  1280 |   640 |  1920 |   0  |   0  |  1  |   0  | <- Available resources in the upper region
 
|       |CurrentRegion|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region
 
-|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|  type |  expansion  |                                                                                      | 
 
| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>"
 
| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>"
 
| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>"
 

 
Clock-Region: 
 
|-----------------------------------------------------------------------------------------------------------------------------------------------------------
 
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
 
|       | Upper Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region
 
|       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region
 
|       | Lower Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region
 
| clock |    region   |                                                                                      -----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
    0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>"
 
| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>"
 
| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>"
 

 

 
######################################################################################
 
#
 
# Number of Regional Clock Networks used in this design: 8 (each network can be
 
#
 

 
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bufio_dqs" LOC =
 
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" TNM_NET =
 
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" AREA_GROUP =
 
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" RANGE =
 

 
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" driven by "BUFIO_X0Y9"
 
"BUFIO_X0Y9" ;
 
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;
 
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;
 
CLOCKREGION_X0Y2;
 

 
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_bufio_dqs" LOC =
 
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" TNM_NET =
 
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" AREA_GROUP =
 
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" RANGE =
 

 
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" driven by "BUFIO_X0Y4"
 
"BUFIO_X0Y4" ;
 
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;
 
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;
 
CLOCKREGION_X0Y1;
 

 
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_bufio_dqs" LOC =
 
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" TNM_NET =
 
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" AREA_GROUP =
 
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" RANGE =
 

 
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" driven by "BUFIO_X0Y7"
 
"BUFIO_X0Y7" ;
 
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;
 
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;
 
CLOCKREGION_X0Y1;
 

 
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_bufio_dqs" LOC =
 
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" TNM_NET =
 
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" AREA_GROUP =
 
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" RANGE =
 

 
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" driven by "BUFIO_X0Y10"
 
"BUFIO_X0Y10" ;
 
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;
 
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;
 
CLOCKREGION_X0Y2;
 

 

 
Phase 8.36  Local Placement Optimization (Checksum:e5ad4bb9) REAL time: 13 mins 24 secs
 
.........................
 
.
 
.....
 
.....
 
......
 
.......
 
.......
 
........
 
........
 
Phase 9.30  Global Clock Region Assignment
 

 
# GLOBAL CLOCK NET DISTRIBUTION UCF REPORT:
 
# Number of Global Clock Regions : 16
 
#
 

 
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT1.CLKOUT1_BUFG_INST" LOC = "BUFGCTRL_X0Y1" ;
 
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.gtxclk_pll_bufg" LOC = "BUFGCTRL_X0Y29" ;
 
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT2.CLKOUT2_BUFG_INST" LOC = "BUFGCTRL_X0Y2" ;
 
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/notsame.usrclk_pll_bufg" LOC = "BUFGCTRL_X0Y28" ;
 
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.clkfbin_pll_bufg" LOC = "BUFGCTRL_X0Y26" ;
 
INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/Using_BUFG_for_CLK0.CLK0_BUFG_INST" LOC = "BUFGCTRL_X0Y7" ;
 
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT0.CLKOUT0_BUFG_INST" LOC = "BUFGCTRL_X0Y5" ;
 
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/bufg2" LOC = "BUFGCTRL_X0Y0" ;
 
INST "fpga_0_SRAM_ZBT_CLK_FB_pin" LOC = "IOB_X1Y111" ;
 
INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" LOC = "IOB_X1Y219" ;
 
INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" LOC = "IOB_X1Y105" ;
 
INST "fpga_0_PCIe_Bridge_RXP_pin" LOC = "IPAD_X1Y13" ;
 
INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" LOC = "IPAD_X1Y17" ;
 
INST "fpga_0_PCIe_Bridge_TXP_pin" LOC = "OPAD_X0Y9" ;
 
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y0" ;
 
INST "ibufgds_76" LOC = "BUFDS_X0Y2" ;
 
# clk_125_0000MHzPLL0 driven by BUFGCTRL_X0Y1
 
TIMEGRP "TN_clk_125_0000MHzPLL0" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0" ;
 

 
NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;
 
AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y3, CLOCKREGION_X0Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
 
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk driven by BUFGCTRL_X0Y29
 
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;
 

 
NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;
 
AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
 
# clk_125_0000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y2
 
TIMEGRP "TN_clk_125_0000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0_ADJUST" ;
 

 
NET "clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" TNM_NET = "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;
 
AREA_GROUP "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X0Y1 ;
 
# PCIe_Bridge/Bridge_Clk driven by BUFGCTRL_X0Y28
 
TIMEGRP "TN_PCIe_Bridge/Bridge_Clk" AREA_GROUP = "CLKAG_PCIe_Bridge/Bridge_Clk" ;
 

 
NET "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" TNM_NET = "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;
 
AREA_GROUP "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" RANGE =   CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X1Y2, CLOCKREGION_X1Y3, CLOCKREGION_X1Y4 ;
 
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin driven by BUFGCTRL_X0Y26
 
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;
 

 
NET "clk_200_0000MHz" TNM_NET = "TN_clk_200_0000MHz" ;
 
AREA_GROUP "CLKAG_clk_200_0000MHz" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
 
# fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF driven by BUFGCTRL_X0Y7
 
TIMEGRP "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" AREA_GROUP = "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;
 

 
NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;
 
AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;
 
# clk_125_0000MHz90PLL0_ADJUST driven by BUFGCTRL_X0Y5
 
TIMEGRP "TN_clk_125_0000MHz90PLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHz90PLL0_ADJUST" ;
 

 
NET "clk_62_5000MHzPLL0_ADJUST" TNM_NET = "TN_clk_62_5000MHzPLL0_ADJUST" ;
 
AREA_GROUP "CLKAG_clk_62_5000MHzPLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
 
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg driven by BUFGCTRL_X0Y0
 
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;
 

 
# This report is provided to help reproduce successful clock-region
 
# clock networks, in a format that is directly usable in ucf files.
 
#END of Global Clock Net Distribution UCF Constraints
 

 
######################################################################################
 

 
Number of Global Clock Networks: 15
 
Clock Region Assignment: SUCCESSFUL
 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
     12 |      0 |      0 |      0 |     80 |     80 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     17 |    656 |PCIe_Bridge/Bridge_Clk
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 2/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      4 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |     24 |     52 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
 
      8 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |      0 |      0 |    104 |   1315 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
     12 |      4 |      2 |      0 |     40 |     40 |      0 |      0 |      0 |      0 |      1 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      6 |    156 |PCIe_Bridge/Bridge_Clk
 
      2 |      1 |      0 |      0 |      0 |     17 |      0 |      0 |      0 |      0 |      0 |      0 |     10 |    991 |clk_125_0000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      8 |clk_62_5000MHzPLL0_ADJUST
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 4/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     11 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
 
      0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP
 
      2 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |    240 |   1203 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
     12 |      2 |      1 |      0 |     60 |     60 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     12 |clk_125_0000MHz90PLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 4/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     90 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
 
      3 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     48 |    725 |clk_125_0000MHzPLL0_ADJUST
 
      5 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     76 |   1199 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
      4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     86 |clk_125_0000MHz90PLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      3 |clk_200_0000MHz
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 2/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      4 |      0 |      0 |      0 |      0 |      0 |      3 |      0 |      0 |      0 |      0 |      0 |     99 |   1148 |clk_125_0000MHzPLL0_ADJUST
 
      4 |      0 |      0 |      0 |      0 |      0 |      3 |      0 |      0 |      0 |      0 |      0 |     99 |   1191 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
      4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     36 |clk_125_0000MHz90PLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    219 |clk_62_5000MHzPLL0_ADJUST
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 4/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     83 |    834 |clk_125_0000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     37 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP
 
      0 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |     83 |    892 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
     12 |      2 |      1 |      0 |     60 |     60 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     48 |clk_125_0000MHz90PLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      8 |    227 |clk_62_5000MHzPLL0_ADJUST
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 1/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 7/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin
 
      0 |      0 |      0 |      0 |      0 |      8 |      0 |      0 |      0 |      0 |      0 |      0 |     65 |    555 |clk_125_0000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |    100 |clk_62_5000MHzPLL0_ADJUST
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 1/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 2/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |clk_62_5000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      8 |    347 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     34 |    208 |clk_125_0000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     34 |    208 | Total
 

 
The above detailed report is the initial placement of the logic after the clock region assignment. The final placement
 
maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.
 

 
######################################################################################
 

 

 
Phase 10.3  Local Placement Optimization (Checksum:e5ad4bb9) REAL time: 14 mins 49 secs
 
Phase 11.5  Local Placement Optimization
 

 
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Phase 12.8  Global Placement (Checksum:651fc219) REAL time: 20 mins 14 secs
 
Phase 13.29  Local Placement Optimization
 

 
Phase 14.5  Local Placement Optimization (Checksum:651fc219) REAL time: 20 mins 19 secs
 
Phase 15.18  Placement Optimization
 

 
Phase 16.5  Local Placement Optimization (Checksum:11e1af7) REAL time: 23 mins 46 secs
 
Phase 17.34  Placement Validation
 

 
Total CPU  time to Placer completion: 21 mins
 
Writing output files...
 
Design Summary:
 
Number of warnings:   50
 
  Number of Slice Registers:                13,531 out of  44,800   30%
 
    Number used as Latches:                      1
 
  Number of Slice LUTs:                     14,602 out of  44,800   32%
 
      Number using O6 output only:          12,711
 
      Number using O5 and O6:                  919
 
      Number used as Dual Port RAM:            164
 
        Number using O5 output only:            32
 
      Number used as Single Port RAM:            4
 
      Number used as Shift Register:           373
 
    Number used as exclusive route-thru:       113
 
    Number using O6 output only:               417
 
    Number using O5 and O6:                     10
 
Slice Logic Distribution:
 
  Number of LUT Flip Flop pairs used:       19,423
 
    Number with an unused LUT:               4,821 out of  19,423   24%
 
    Number of unique control sets:           1,396
 
      to control set restrictions:           3,277 out of  44,800    7%
 
  A LUT Flip Flop pair for this architecture represents one LUT paired with
 
  clock, reset, set, and enable signals for a registered element.
 
  over-mapped for a non-slice resource or if Placement fails.
 
  over-mapped for a non-BRAM resource or if placement fails.
 
IO Utilization:
 
    Number of LOCed IOBs:                      255 out of     255  100%
 
    Number of bonded IPADs:                      4 out of      50    8%
 

 
  Number of BlockRAM/FIFO:                      22 out of     148   14%
 
    Number using FIFO only:                      2
 
      Number of 36k BlockRAM used:              16
 
      Number of 36k FIFO used:                   2
 
  Number of BUFG/BUFGCTRLs:                     15 out of      32   46%
 
  Number of IDELAYCTRLs:                         3 out of      22   13%
 
  Number of BUFIOs:                              8 out of      80   10%
 
  Number of DSP48Es:                             3 out of     128    2%
 
  Number of PCIEs:                               1 out of       3   33%
 
  Number of PLL_ADVs:                            2 out of       6   33%
 

 
Average Fanout of Non-Clock Nets:                3.81
 
Peak Memory Usage:  789 MB
 
Total CPU time to MAP completion:   21 mins 42 secs
 
Mapping completed.
 

 

 
# Starting program par
 
system.pcf
 
Release 11.2 - par L.46 (nt)
 
PMSPEC -- Overriding Xilinx file  with local file
 

 
Loading device for application Rf_Device from file '5vfx70t.nph' in environment
 
   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
 
Constraints file: system.pcf.
 
WARNING:ConstraintSystem:65 - Constraint  [system.pcf(78662)]
 

 
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
 

 
   "TNM_CLK0" TS_MC_CLK * 4; ignored during timing analysis.
 
   consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.
 
Device speed data version:  "PRODUCTION 1.65 2009-06-01".
 

 
Device Utilization Summary:
 
   Number of BUFDSs                          1 out of 8      12%
 
   Number of BUFIOs                          8 out of 80     10%
 
   Number of DSP48Es                         3 out of 128     2%
 
      Number of LOCed FIFO36_72_EXPs         2 out of 2     100%
 
   Number of GTX_DUALs                       1 out of 8      12%
 
      Number of LOCed IDELAYCTRLs            3 out of 3     100%
 
   Number of ILOGICs                       131 out of 800    16%
 

 
      Number of LOCed IOBs                 255 out of 255   100%
 
   Number of IODELAYs                       80 out of 800    10%
 

 
      Number of LOCed IPADs                  4 out of 4     100%
 
   Number of JTAGPPCs                        1 out of 1     100%
 
   Number of External OPADs                  2 out of 32      6%
 

 
      Number of LOCed PCIEs                  1 out of 1     100%
 
   Number of PLL_ADVs                        2 out of 6      33%
 
   Number of RAMB18X2SDPs                    4 out of 148     2%
 
      Number of LOCed RAMB36SDP_EXPs         1 out of 6      16%
 
   Number of RAMB36_EXPs                    10 out of 148     6%
 

 
      Number used as Flip Flops          13529
 
      Number used as LatchThrus              1
 
   Number of Slice LUTS                  14602 out of 44800  32%
 

 
Overall effort level (-ol):   High
 

 
Finished initial Timing Analysis.  REAL time: 1 mins 5 secs
 
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0> has no load.  PAR will not attempt to route this
 
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0> has no load.  PAR will not attempt to route this
 
WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<31> has no load.  PAR will not attempt to route this
 
WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<30> has no load.  PAR will not attempt to route this
 
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull has no load.  PAR will not attempt to route this
 
Starting Router
 
INFO:Route:501 - One or more directed routing (DIRT) constraints generated for a specific device have been found. Note
 
   verify that the same connectivity is available in the target device for this implementation.
 
Phase  1  : 95521 unrouted;      REAL time: 1 mins 22 secs
 
Phase  2  : 84728 unrouted;      REAL time: 1 mins 35 secs
 
Phase  3  : 34551 unrouted;      REAL time: 3 mins 59 secs
 
Phase  4  : 34616 unrouted; (Setup:0, Hold:93713, Component Switching Limit:0)     REAL time: 4 mins 32 secs
 
Updating file: system.ncd with current fully routed design.
 
Phase  5  : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0)     REAL time: 5 mins 40 secs
 
Phase  6  : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0)     REAL time: 5 mins 40 secs
 
Phase  7  : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0)     REAL time: 5 mins 40 secs
 
Phase  8  : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0)     REAL time: 5 mins 40 secs
 
Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 6 mins 40 secs
 
Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 6 mins 55 secs
 
Total CPU time to Router completion: 6 mins 44 secs
 
Partition Implementation Status
 

 

 

 

 
Generating Clock Report
 

 
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
 
|clk_125_0000MHzPLL0_ |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|                  lk |BUFGCTRL_X0Y28| No   | 1452 |  0.412     |  2.085      |
 
|clk_62_5000MHzPLL0_A |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|dge/comp_block_plus/ |              |      |      |            |             |
 
|                  lk |BUFGCTRL_X0Y27| No   |   93 |  0.266     |  2.085      |
 
|fpga_0_SysACE_Compac |              |      |      |            |             |
 
|             n_BUFGP | BUFGCTRL_X0Y8| No   |   55 |  0.163     |  1.770      |
 
|fpga_0_Ethernet_MAC_ |              |      |      |            |             |
 
|                     |BUFGCTRL_X0Y30| No   |   12 |  0.038     |  1.879      |
 
|clk_125_0000MHz90PLL |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|dge/comp_block_plus/ |              |      |      |            |             |
 
|        lk/gt_usrclk |BUFGCTRL_X0Y29| No   |    6 |  0.058     |  1.886      |
 
|     clk_200_0000MHz | BUFGCTRL_X0Y4| No   |    4 |  0.100     |  1.879      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
 
|f_top/u_phy_top/u_ph |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
 
| y_io/delayed_dqs<1> |        IO Clk| No   |   18 |  0.083     |  0.380      |
 
|fpga_0_Ethernet_MAC_ |              |      |      |            |             |
 
|                     |BUFGCTRL_X0Y31| No   |    6 |  0.004     |  1.941      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |
 
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
 
| y_io/delayed_dqs<2> |        IO Clk| No   |   18 |  0.101     |  0.425      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
 
|f_top/u_phy_top/u_ph |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
 
| y_io/delayed_dqs<5> |        IO Clk| No   |   18 |  0.101     |  0.425      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
 
|f_top/u_phy_top/u_ph |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
 
| y_io/delayed_dqs<6> |        IO Clk| No   |   18 |  0.096     |  0.393      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
 
|f_top/u_phy_top/u_ph |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
+---------------------+--------------+------+------+------------+-------------+
 
|dge/comp_block_plus/ |              |      |      |            |             |
 
|lk/SIO/.pcie_gt_wrap |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|  t_MAC/phy_tx_clk_i |         Local|      |    9 |  2.887     |  3.720      |
 
|RS232_Uart_1_Interru |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|         _JTGC405TCK |         Local|      |    1 |  0.000     |  1.526      |
 

 
only delays for the net. Note this is different from Clock Skew which
 
the minimum and maximum path delays which includes logic delays.
 
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
 
Number of Timing Constraints that were not applied: 5
 
Asterisk (*) preceding a constraint indicates it was not met.
 

 
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
 
----------------------------------------------------------------------------------------------------------
 
  s HIGH 50%                                | HOLD        |     0.035ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  lus/comp_endpoint/core_clk" PERIOD =      | HOLD        |     0.349ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  L0_CLK_OUT_2_ = PERIOD TIMEGRP         "c | HOLD        |     0.021ns|            |       0|           0
 
  LK_OUT_2_" TS_sys_clk_pin *         1.25  |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS"       | HOLD        |     1.027ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
 
  DELAY = 0.85 ns                           |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0
 
  dqs[1].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
 
  DELAY = 0.85 ns                           |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0
 
  dqs[2].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
 
  DELAY = 0.85 ns                           |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0
 
  dqs[4].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
 
  DELAY = 0.85 ns                           |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0
 
  dqs[7].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  ge_Clk" TO TIMEGRP "SPLB_Clk" 8 ns        | HOLD        |     0.502ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  _Clk" TO TIMEGRP "Bridge_Clk" 8 ns        | HOLD        |     0.456ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  HIGH 50%                                  |             |            |            |        |
 
  TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | MAXDELAY    |     1.695ns|     4.305ns|       0|           0
 
  thernet_MAC" 6 ns                         |             |            |            |        |
 
  TS_clock_generator_0_clock_generator_0_PL | SETUP       |     2.151ns|     4.917ns|       0|           0
 
  lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |
 
  PHASE 2 ns HIGH 50%                       |             |            |            |        |
 
  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |     6.000ns|     4.000ns|       0|           0
 
------------------------------------------------------------------------------------------------------
 
  L0_CLK_OUT_3_ = PERIOD TIMEGRP         "c | HOLD        |     0.465ns|            |       0|           0
 
  LK_OUT_3_" TS_sys_clk_pin *         2 HIG |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  L0_CLK_OUT_4_ = PERIOD TIMEGRP         "c | HOLD        |     0.116ns|            |       0|           0
 
  LK_OUT_4_" TS_sys_clk_pin *         0.625 |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  UFGP" MAXSKEW = 5 ns                      |             |            |            |        |
 
  NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW     |     4.833ns|     0.167ns|       0|           0
 
------------------------------------------------------------------------------------------------------
 
  L0_CLK_OUT_1_ = PERIOD TIMEGRP         "c |             |            |            |        |
 
  LK_OUT_1_" TS_sys_clk_pin *         1.25  |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  GRP "TXCLK_GRP_Ethernet_MAC" TO         T |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  UFGP" PERIOD = 40 ns HIGH 14 ns           | HOLD        |     0.458ns|            |       0|           0
 
  TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM | SETUP       |    13.905ns|     6.095ns|       0|           0
 
     TIMEGRP "TNM_CLK0" TS_MC_CLK * 4       |             |            |            |        |
 
  TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FRO | SETUP       |    14.527ns|     5.473ns|       0|           0
 
      TIMEGRP "TNM_CLK90" TS_MC_CLK * 4     |             |            |            |        |
 
  TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    17.706ns|     2.294ns|       0|           0
 
    TS_MC_CLK * 4                           |             |            |            |        |
 
  TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGR | SETUP       |    18.115ns|     1.885ns|       0|           0
 
  TNM_CLK0" TS_MC_CLK * 4                   |             |            |            |        |
 
  TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    18.117ns|     1.883ns|       0|           0
 
    TS_MC_CLK * 4                           |             |            |            |        |
 
  NET "fpga_0_SysACE_CompactFlash_SysACE_CL | SETUP       |    26.887ns|     3.113ns|       0|           0
 
   HIGH 50%                                 |             |            |            |        |
 
  NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP       |    32.341ns|     7.659ns|       0|           0
 
------------------------------------------------------------------------------------------------------
 
------------------------------------------------------------------------------------------------------
 
  P "TNM_RDEN_SEL_MUX" TO TIMEGRP         " |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  s HIGH 50%                                |             |            |            |        |
 

 
Derived Constraint Report
 
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
 
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 
| TS_MC_PHY_INIT_DATA_SEL_0     |     20.000ns|      6.095ns|          N/A|            0|            0|           21|            0|
 
| TS_MC_GATE_DLY                |     20.000ns|      2.294ns|          N/A|            0|            0|           40|            0|
 
| TS_MC_CAL_RDEN_DLY            |     20.000ns|      1.885ns|          N/A|            0|            0|            5|            0|
 
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 
Derived Constraints for TS_sys_clk_pin
 
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
 
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
 
|TS_sys_clk_pin                 |     10.000ns|      4.000ns|      9.965ns|            0|            0|            0|      1090426|
 
| erator_0_PLL0_CLK_OUT_0_      |             |             |             |             |             |             |             |
 
| erator_0_PLL0_CLK_OUT_1_      |             |             |             |             |             |             |             |
 
| erator_0_PLL0_CLK_OUT_2_      |             |             |             |             |             |             |             |
 
| erator_0_PLL0_CLK_OUT_3_      |             |             |             |             |             |             |             |
 
| erator_0_PLL0_CLK_OUT_4_      |             |             |             |             |             |             |             |
 

 
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
 

 
Generating Pad Report.
 
All signals are completely routed.
 
WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
 
Loading device for application Rf_Device from file '5vlx50t.nph' in environment
 
INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 128
 
   found: 128, number successful: 128
 
Total CPU time to PAR completion: 7 mins 9 secs
 
Peak Memory Usage:  705 MB
 
Placer: Placement generated during map.
 
Timing: Completed - No errors found.
 
Number of error messages: 0
 
Number of info messages: 4
 
Writing design to file system.ncd
 

 
PAR done!
 

 
#----------------------------------------------#
 
# trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf
 
Release 11.2 - Trace  (nt)
 

 
PMSPEC -- Overriding Xilinx file
 

 
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
 
WARNING:ConstraintSystem:65 - Constraint 
 
   "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(78661)].
 
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM
 
   ignored during timing analysis.
 
   information, see the TSI report.  Please consult the Xilinx Command Line
 
--------------------------------------------------------------------------------
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf
 

 
Physical constraint file: system.pcf
 
level 0)
 
--------------------------------------------------------------------------------
 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
 
   unconstrained paths section(s) of the report.
 
   50 Ohm transmission line loading model.  For the details of this model, and
 
   see the device datasheet.
 

 
---------------
 
Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)
 
Constraints cover 1280410 paths, 18 nets, and 87141 connections
 
Design statistics:
 
   Maximum path delay from/to any node:   7.813ns
 
   Maximum net skew:   0.545ns
 

 
--------------------------------------------------------------------------------
 
Generating Report ...
 
Number of warnings: 2
 
Total time: 1 mins 34 secs
 

 
touch __xps/system_routed
 
Analyzing implementation/system.par
 
Running Bitgen..
 
cd implementation; bitgen -w -f bitgen.ut system; cd ..
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
 with local file
 
Loading device for application Rf_Device from file '5vfx70t.nph' in environment
 
   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
 

 

 
WARNING:PhysDesignRules:1842 - One or more GTXs are being used in this design.
 
   Transceiver User Guide to ensure that the design SelectIO usage meets the
 
WARNING:PhysDesignRules:372 - Gated clock. Clock net
 
   rapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not good
 
   flip-flop.
 
   Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.
 
   data into the flip-flop.
 
   > is incomplete. The signal does
 
WARNING:PhysDesignRules:367 - The signal
 
   drive any load pins in the design.
 
   > is incomplete. The signal does not
 
WARNING:PhysDesignRules:367 - The signal
 
   drive any load pins in the design.
 
   is incomplete. The signal does not drive any load pins in the design.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
individual error or warning messages for more details.
 
Saving bit stream in "system.bit".
 

 
Done!
 
At Local date and time: Sat Jul 04 08:21:51 2009
 

 
*********************************************
 
*********************************************
 
-bt implementation/system.bit -o implementation/download.bit
 
bitinit version Xilinx EDK 11.2 Build EDK_LS3.47
 

 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
 
   hs line 253 - deprecated core for architecture 'virtex5fx'!
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m
 

 

 

 
Address Map for Processor ppc440_0
 
  (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC
 
  (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0
 
  (0x81440000-0x8144ffff) LEDs_8Bit     plb_v46_0
 
  (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0
 
  (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0
 
  (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0
 
  (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0
 
  (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
 
   C_SPLB0_P2P value to 0
 
Computing clock values...
 
   'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be
 
   through the clock generator IP.
 
INFO:EDK:1432 - Frequency for Top-Level Input Clock
 
   performed for IPs connected to that clock port, unless they are connected
 

 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_SLAVES value to 12
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   value to 0x2000
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   C_PORT_DWIDTH value to 64
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   value to 8
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01
 
 
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
 
 
   value to 128
 
 
 
   value to 128
 
 
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
 
   value to 128
 
 
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
 
   C_SPLB_SMALLEST_MASTER value to 128
 
 
 
   C_MPLB_DWIDTH value to 128
 
 
 
   C_MPLB_SMALLEST_SLAVE value to 128
 
 
 
 
 
 
 
   C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_SLAVES value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
 
   PARAMETER C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
 
   value to 128
 
Checking platform address map ...
 
Initializing Memory...
 
data2mem -bm "implementation/system_bd" -bt "implementation/system.bit"  -bd
 
Memory Initialization completed successfully.
 
*********************************************
 
*********************************************
 
Release 11.2 - iMPACT L.46 (nt)
 
Preference Table
 
StartupClock         Auto_Correction
 
KeepSVF              False
 
UseHighz             False
 
UserLevel            Novice
 
svfUseTime           false
 
AutoDetecting cable. Please wait.
 
Checking cable driver.
 
 Driver version: src=2301, dest=2301.
 
13:58:07, version = 900.
 
 Max current requested during enumeration is 300 mA.
 
write (count, cmdBuffer, dataBuffer) failed C0000004.
 
 Setting cable speed to 6 MHz.
 
Firmware version = 2301.
 
Firmware hex file version = 2401.
 
Downloaded firmware version = 2401.
 
 PLD version = 200Dh.
 
INFO:iMPACT:1777 -
 

 
----------------------------------------------------------------------
 
INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.
 
----------------------------------------------------------------------
 
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
 
   Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...
 

 
----------------------------------------------------------------------
 
INFO:iMPACT:1777 -
 
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
 
----------------------------------------------------------------------
 
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
 
----------------------------------------------------------------------
 
   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
 
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
 
done.
 
Elapsed time =      0 sec.
 
done.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
Validating chain...
 
5: Device Temperature: Current Reading:   30.69 C, Min. Reading:   27.24 C, Max.
 
5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.
 
5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.505 V, Max.
 
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
 
'5': Programming device...
 
done.
 
CRC error                                         :         0
 
DCM locked                                        :         1
 
End of startup signal from Startup block          :         1
 
status of GWE                                     :         1
 
value of MODE pin M0                              :         1
 
Value of MODE pin M2                              :         1
 
Value driver in from INIT pad                     :         1
 
Value of DONE pin                                 :         1
 
Decryptor error Signal                            :         0
 
startup_state[18] CFG startup state machine       :         0
 
startup_state[20] CFG startup state machine       :         1
 
SPI Flash Type[22] Select                         :         1
 
SPI Flash Type[24] Select                         :         1
 
CFG bus width auto detection result               :         0
 
BPI address wrap around error                     :         0
 
read back crc error                               :         0
 
 Match_cycle = 2.
 
Elapsed time =     10 sec.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
 
INFO:iMPACT - '5': Programing completed successfully.
 

 

 

 
 make -f system.make program started...
 
*********************************************
 
*********************************************
 
libgen
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg
 

 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
 
   hs line 298 - deprecated core for architecture 'virtex5fx'!
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
 
   hs line 298 - deprecated core for architecture 'virtex5fx'!
 
Checking platform configuration ...
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
 
line 290 - 1 master(s) : 1 slave(s)
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
 

 
WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
 
   hs line 462 - floating connection!
 
Performing Clock DRCs...
 
Performing Reset DRCs...
 
Overriding system level properties...
 
Running system level update procedures...
 
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
 
Running system level DRCs...
 
Performing System level DRCs on properties...
 
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m
 
WARNING:EDK:411 - emaclite -
 
   ss line 83 - deprecated driver!
 
  - DDR2_SDRAM
 
  - Ethernet_MAC
 
  - LEDs_8Bit
 
  - PCIe_Bridge
 
  - RS232_Uart_1
 
  - SysACE_CompactFlash
 
  - xps_bram_if_cntlr_1
 

 

 
Staging source files.
 
Running generate.
 
Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"
 
"EXTRA_COMPILER_FLAGS=-g"'.
 
Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"
 
"EXTRA_COMPILER_FLAGS=-g"'.
 
powerpc-eabi-ar: creating ../../../lib/libxil.a
 
Compiling lldma
 
Compiling gpio
 
Compiling iic
 
Compiling uartlite
 
Compiling intc
 
 
 
    -mfpu=sp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
powerpc-eabi-size RTOSDemo/executable.elf
 
 
 

 

 

 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
 
Done writing Tab View settings to:
 

 

 

 

 

 
 
 
 
 
rm -f __xps/ise/_xmsgs/platgen.xmsgs
 
rm -f implementation/system.bit
 
rm -f implementation/system_bd.bmm
 
rm -f __xps/system_routed
 
rm -rf xst.srp system.srp
 

 
Done!
 
At Local date and time: Sun Jul 05 09:36:23 2009
 

 
rm -f libgen.log
 
rm -f RTOSDemo/executable.elf
 

 

 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
 
Done writing Tab View settings to:
 

 
Line No.	Rev	Author	Line
1	586	jeremybenn	`No logfile was found.`
2
3			`WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!`
4
5			`WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!`
6
7			`Generating Block Diagram to Buffer`
8
9			`Generated Block Diagram SVG`
10
11			`The project file (XMP) has changed on disk.`
12
13			`WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!`
14
15			`WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!`
16
17			`WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!`
18
19			`WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!`
20
21			`At Local date and time: Tue Jun 30 18:34:41 2009`
22			`make -f system.make hwclean started...`
23
24			`rm -f implementation/system.ngc`
25			`rm -f platgen.log`
26			`rm -f __xps/ise/_xmsgs/platgen.xmsgs`
27			`rm -f implementation/system.bmm`
28			`rm -f implementation/system.bit`
29			`rm -f implementation/system.ncd`
30			`rm -f implementation/system_bd.bmm`
31			`rm -f implementation/system_map.ncd`
32			`rm -f __xps/system_routed`
33			`rm -rf implementation synthesis xst hdl`
34			`rm -rf xst.srp system.srp`
35			`rm -f __xps/ise/_xmsgs/bitinit.xmsgs`
36
37
38			`Done!`
39
40			`At Local date and time: Tue Jun 30 18:34:46 2009`
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