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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC440_SP_FPU_Xilinx_Virtex5_GCC/] [system.log] - Blame information for rev 591

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Line No. Rev Author Line
1 586 jeremybenn
No logfile was found.
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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
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WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
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Generating Block Diagram to Buffer
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Generated Block Diagram SVG
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The project file (XMP) has changed on disk.
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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 253 - deprecated core for architecture 'virtex5fx'!
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WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs line 298 - deprecated core for architecture 'virtex5fx'!
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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
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WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
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At Local date and time: Tue Jun 30 18:34:41 2009
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 make -f system.make hwclean started...
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rm -f implementation/system.ngc
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rm -f platgen.log
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rm -f __xps/ise/_xmsgs/platgen.xmsgs
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rm -f implementation/system.bmm
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rm -f implementation/system.bit
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rm -f implementation/system.ncd
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rm -f implementation/system_bd.bmm
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rm -f implementation/system_map.ncd
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rm -f __xps/system_routed
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rm -rf implementation synthesis xst hdl
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rm -rf xst.srp system.srp
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rm -f __xps/ise/_xmsgs/bitinit.xmsgs
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Done!
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40
At Local date and time: Tue Jun 30 18:34:46 2009
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 make -f system.make bitsclean started...
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rm -f implementation/system.bit
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rm -f implementation/system.ncd
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rm -f implementation/system_bd.bmm
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rm -f implementation/system_map.ncd
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rm -f __xps/system_routed
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49
 
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Done!
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52
At Local date and time: Tue Jun 30 18:34:52 2009
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 make -f system.make netlistclean started...
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55
rm -f implementation/system.ngc
56
rm -f platgen.log
57
rm -f __xps/ise/_xmsgs/platgen.xmsgs
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rm -f implementation/system.bmm
59
 
60
 
61
Done!
62
 
63
At Local date and time: Tue Jun 30 18:34:57 2009
64
 make -f system.make libsclean started...
65
 
66
rm -rf ppc440_0/
67
rm -f libgen.log
68
rm -f __xps/ise/_xmsgs/libgen.xmsgs
69
 
70
 
71
Done!
72
 
73
At Local date and time: Tue Jun 30 18:35:02 2009
74
 make -f system.make programclean started...
75
 
76
rm -f RTOSDemo/executable.elf
77
 
78
 
79
Done!
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81
At Local date and time: Tue Jun 30 18:35:08 2009
82
 make -f system.make swclean started...
83
 
84
rm -rf ppc440_0/
85
rm -f libgen.log
86
rm -f __xps/ise/_xmsgs/libgen.xmsgs
87
rm -f RTOSDemo/executable.elf
88
 
89
 
90
Done!
91
 
92
Writing filter settings....
93
 
94
Done writing filter settings to:
95
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
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97
Done writing Tab View settings to:
98
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.gui
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100
Xilinx Platform Studio (XPS)
101
Xilinx EDK 11.2 Build EDK_LS3.47
102
 
103
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
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105
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 239 - deprecated core for architecture 'virtex5fx'!
106
 
107
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 284 - deprecated core for architecture 'virtex5fx'!
108
 
109
Generating Block Diagram to Buffer
110
 
111
Generated Block Diagram SVG
112
 
113
At Local date and time: Fri Jul 03 21:23:32 2009
114
 make -f system.make bits started...
115
 
116
****************************************************
117
Creating system netlist for hardware specification..
118
****************************************************
119
platgen -p xc5vfx70tff1136-1 -lang vhdl   -msg __xps/ise/xmsgprops.lst system.mhs
120
 
121
 
122
 (nt)
123
 
124
125
 
126
Command Line: platgen -p xc5vfx70tff1136-1 -lang vhdl -msg
127
 
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129
 
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131
 
132
133
 
134
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
135
 
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138
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m
139
 
140
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
141
 
142
   hs line 253 - deprecated core for architecture 'virtex5fx'!
143
 
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145
 
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147
 
148
149
 
150
151
 
152
Address Map for Processor ppc440_0
153
 
154
  (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC
155
 
156
  (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0
157
 
158
  (0x81440000-0x8144ffff) LEDs_8Bit     plb_v46_0
159
 
160
  (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0
161
 
162
  (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0
163
 
164
  (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0
165
 
166
  (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0
167
 
168
  (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0
169
 
170
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
171
 
172
 
173
 
174
Computing clock values...
175
 
176
 
177
 
178
   through the clock generator IP.
179
 
180
 
181
 
182
   performed for IPs connected to that clock port, unless they are connected
183
 
184
185
 
186
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
187
 
188
   C_PLBV46_NUM_MASTERS value to 1
189
 
190
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
191
 
192
   C_PLBV46_NUM_SLAVES value to 12
193
 
194
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
195
 
196
   C_PLBV46_MID_WIDTH value to 1
197
 
198
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
199
 
200
   value to 128
201
 
202
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
203
 
204
   PARAMETER C_SPLB_DWIDTH value to 128
205
 
206
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
207
 
208
   PARAMETER C_SPLB_NUM_MASTERS value to 1
209
 
210
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
211
 
212
   PARAMETER C_SPLB_SMALLEST_MASTER value to 128
213
 
214
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
215
 
216
   value to 0x2000
217
 
218
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
219
 
220
   C_PORT_DWIDTH value to 64
221
 
222
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
223
 
224
   value to 8
225
 
226
 
227
 
228
   C_SPLB_DWIDTH value to 128
229
 
230
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
231
 
232
   value to 128
233
 
234
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
235
 
236
   value to 128
237
 
238
 
239
 
240
   value to 128
241
 
242
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
243
 
244
   value to 128
245
 
246
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
247
 
248
 
249
 
250
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
251
 
252
   C_SPLB_DWIDTH value to 128
253
 
254
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
255
 
256
   C_SPLB_SMALLEST_MASTER value to 128
257
 
258
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
259
 
260
   C_MPLB_DWIDTH value to 128
261
 
262
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
263
 
264
   C_MPLB_SMALLEST_SLAVE value to 128
265
 
266
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
267
 
268
   C_SPLB_MID_WIDTH value to 1
269
 
270
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
271
 
272
   C_SPLB_NUM_MASTERS value to 1
273
 
274
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
275
 
276
   C_SPLB_SMALLEST_MASTER value to 128
277
 
278
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
279
 
280
   C_SPLB_DWIDTH value to 128
281
 
282
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
283
 
284
   C_PLBV46_NUM_MASTERS value to 1
285
 
286
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
287
 
288
   C_PLBV46_NUM_SLAVES value to 1
289
 
290
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
291
 
292
   C_PLBV46_MID_WIDTH value to 1
293
 
294
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
295
 
296
   value to 128
297
 
298
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
299
 
300
   PARAMETER C_SPLB_DWIDTH value to 128
301
 
302
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
303
 
304
   C_SPLB_DWIDTH value to 128
305
 
306
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
307
 
308
   C_SPLB_MID_WIDTH value to 1
309
 
310
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
311
 
312
   C_SPLB_NUM_MASTERS value to 1
313
 
314
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
315
 
316
   value to 128
317
 
318
Checking platform address map ...
319
 
320
Checking platform configuration ...
321
 
322
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m
323
 
324
   performance.
325
 
326
   The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs
327
 
328
   operation.
329
 
330
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
331
 
332
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
333
 
334
line 290 - 1 master(s) : 1 slave(s)
335
 
336
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
337
 
338
339
 
340
WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
341
 
342
   hs line 462 - floating connection!
343
 
344
Performing Clock DRCs...
345
 
346
Performing Reset DRCs...
347
 
348
Overriding system level properties...
349
 
350
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
351
 
352
   C_PPC440MC_ADDR_BASE value to 0x00000000
353
 
354
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
355
 
356
   C_PPC440MC_ADDR_HIGH value to 0x0fffffff
357
 
358
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\jtagppc_cntlr_v2_0
359
 
360
   C_NUM_PPC_USED value to 1
361
 
362
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
363
 
364
   value to 0b00000000000000000000000000000001
365
 
366
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
367
 
368
   value to 0b00000000000000000000000000000001
369
 
370
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
371
 
372
   value to 0b00000000000000000000000000000000
373
 
374
Running system level update procedures...
375
 
376
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
377
 
378
Running system level DRCs...
379
 
380
Performing System level DRCs on properties...
381
 
382
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
383
 
384
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
385
 
386
implementation/pcie_bridge_wrapper/pcie_bridge_wrapper.ucf.
387
 
388
389
 
390
391
 
392
implementation/ethernet_mac_wrapper/ethernet_mac_wrapper.ucf.
393
 
394
395
 
396
397
 
398
implementation/ddr2_sdram_wrapper/ddr2_sdram_wrapper.ucf.
399
 
400
401
 
402
403
 
404
Modify defaults ...
405
 
406
Creating stub ...
407
 
408
Processing licensed instances ...
409
 
410
411
 
412
413
 
414
IPNAME:plbv46_pcie INSTANCE:pcie_bridge -
415
 
416
line 253 - Copying (BBD-specified) netlist files.
417
 
418
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
419
 
420
IPNAME:apu_fpu_virtex5 INSTANCE:ppc440_0_apu_fpu_virtex5 -
421
 
422
line 401 - Copying (BBD-specified) netlist files.
423
 
424
Managing cache ...
425
 
426
Elaborating instances ...
427
 
428
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
429
 
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432
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434
Completion time: 2.00 seconds
435
 
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Constructing platform-level connectivity ...
437
 
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439
 
440
441
 
442
443
 
444
445
 
446
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448
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
449
 
450
INSTANCE:ppc440_0 -
451
 
452
line 78 - Running XST synthesis
453
 
454
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
455
 
456
INSTANCE:xps_bram_if_cntlr_1 -
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line 118 - Running XST synthesis
459
 
460
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
461
 
462
INSTANCE:rs232_uart_1 -
463
 
464
line 138 - Running XST synthesis
465
 
466
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
467
 
468
INSTANCE:leds_positions -
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470
line 168 - Running XST synthesis
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472
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
473
 
474
INSTANCE:dip_switches_8bit -
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476
line 196 - Running XST synthesis
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478
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
479
 
480
INSTANCE:sram -
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line 223 - Running XST synthesis
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484
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
485
 
486
INSTANCE:ppc440_0_splb0 -
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488
line 290 - Running XST synthesis
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490
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
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492
INSTANCE:ddr2_sdram -
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494
line 317 - Running XST synthesis
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496
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
497
 
498
INSTANCE:ppc440_0_fcb_v20 -
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500
line 394 - Running XST synthesis
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502
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
503
 
504
INSTANCE:clock_generator_0 -
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506
line 408 - Running XST synthesis
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C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
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INSTANCE:proc_sys_reset_0 -
511
 
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line 453 - Running XST synthesis
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520
line 78 - Running NGCBUILD
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 with local file
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526
xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..
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"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa
531
 
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536
-------------------------------
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538
  No Partitions were found in this design.
539
 
540
-------------------------------
541
 
542
NGCBUILD Design Results Summary:
543
 
544
  Number of warnings:   0
545
 
546
Writing NGC file "../ppc440_0_wrapper.ngc" ...
547
 
548
Total CPU time to NGCBUILD completion:   5 sec
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550
Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...
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552
NGCBUILD done.
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554
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
555
 
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560
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
561
 
562
../rs232_uart_1_wrapper.ngc
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Reading NGO file
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566
 
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568
Partition Implementation Status
569
 
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576
  Number of errors:     0
577
 
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Total REAL time to NGCBUILD completion:  2 sec
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586
IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -
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line 253 - Running NGCBUILD
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 with local file
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594
xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..
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"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa
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Executing edif2ngd -noa
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tion\pcie_bridge_wrapper_fifo_generator_v4_3.edn"
603
 
604
Release 11.2 - edif2ngd L.46 (nt)
605
 
606
INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)
607
 
608
PMSPEC -- Overriding Xilinx file 
609
 
610
Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...
611
 
612
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa
613
 
614
Loading design module
615
 
616
Loading design module
617
 
618
tion\pcie_bridge_wrapper/dpram_70_512.ngc"...
619
 
620
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa
621
 
622
623
 
624
625
 
626
 
627
 
628
  No Partitions were found in this design.
629
 
630
 
631
 
632
NGCBUILD Design Results Summary:
633
 
634
 
635
 
636
Writing NGC file "../pcie_bridge_wrapper.ngc" ...
637
 
638
 
639
 
640
Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...
641
 
642
 
643
 
644
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
645
 
646
 
647
 
648
649
 
650
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
651
 
652
ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc
653
 
654
 
655
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa
656
 
657
 
658
 
659
 
660
 
661
 
662
 
663
 
664
 
665
Writing module to "ethernetlite_v1_01_b_dmem_v2.ngo"...
666
 
667
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\implementa
668
 
669
 
670
Applying constraints in "ethernet_mac_wrapper.ucf" to the design...
671
 
672
 
673
 
674
 
675
 
676
 
677
 
678
 
679
 
680
  Number of errors:     0
681
 
682
683
 
684
 
685
Total CPU time to NGCBUILD completion:   5 sec
686
 
687
 
688
 
689
 
690
 
691
 
692
 
693
 
694
 
695
 
696
 
697
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
698
 
699
 
700
 
701
Reading NGO file
702
 
703
 
704
 
705
Applying constraints in "ddr2_sdram_wrapper.ucf" to the design...
706
 
707
Partition Implementation Status
708
 
709
 
710
 
711
712
 
713
 
714
 
715
  Number of errors:     0
716
 
717
718
 
719
Total REAL time to NGCBUILD completion:  6 sec
720
 
721
722
 
723
724
 
725
IPNAME:ppc440_0_apu_fpu_virtex5_wrapper INSTANCE:ppc440_0_apu_fpu_virtex5 -
726
 
727
line 401 - Running NGCBUILD
728
 
729
 with local file
730
 
731
732
 
733
xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_apu_fpu_virtex5_wrapper.ucf -sd
734
 
735
 
736
 
737
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa
738
 
739
 
740
 
741
tion\ppc440_0_apu_fpu_virtex5_wrapper/apu_fpu_sp_lo.ngc"...
742
 
743
Applying constraints in "ppc440_0_apu_fpu_virtex5_wrapper.ucf" to the design...
744
 
745
Partition Implementation Status
746
 
747
748
 
749
 
750
 
751
752
 
753
 
754
 
755
756
 
757
Total REAL time to NGCBUILD completion:  6 sec
758
 
759
 
760
 
761
762
 
763
IPNAME:xps_intc_0_wrapper INSTANCE:xps_intc_0 -
764
 
765
 
766
 
767
 with local file
768
 
769
 
770
 
771
xc5vfx70tff1136-1 -intstyle silent -sd .. xps_intc_0_wrapper.ngc
772
 
773
 
774
 
775
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa
776
 
777
 
778
 
779
-------------------------------
780
 
781
 
782
 
783
-------------------------------
784
 
785
NGCBUILD Design Results Summary:
786
 
787
  Number of warnings:   0
788
 
789
Writing NGC file "../xps_intc_0_wrapper.ngc" ...
790
 
791
Total CPU time to NGCBUILD completion:   1 sec
792
 
793
Writing NGCBUILD log file "../xps_intc_0_wrapper.blc"...
794
 
795
NGCBUILD done.
796
 
797
Rebuilding cache ...
798
 
799
Total run time: 1330.00 seconds
800
 
801
bash -c "cd synthesis; ./synthesis.sh"
802
 
803
Running XST synthesis ...
804
 
805
Release 11.2 - ngcbuild L.46 (nt)
806
 
807
Overriding Xilinx file  with local file
808
 
809
810
 
811
./system.ngc ../implementation/system.ngc -sd ../implementation -i -ise
812
 
813
814
 
815
"c:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/synthesis/
816
 
817
Loading design module "../implementation/ppc440_0_wrapper.ngc"...
818
 
819
Loading design module "../implementation/xps_bram_if_cntlr_1_wrapper.ngc"...
820
 
821
"../implementation/xps_bram_if_cntlr_1_bram_wrapper.ngc"...
822
 
823
Loading design module "../implementation/leds_8bit_wrapper.ngc"...
824
 
825
Loading design module "../implementation/push_buttons_5bit_wrapper.ngc"...
826
 
827
Loading design module "../implementation/iic_eeprom_wrapper.ngc"...
828
 
829
Loading design module "../implementation/pcie_bridge_wrapper.ngc"...
830
 
831
Loading design module "../implementation/ethernet_mac_wrapper.ngc"...
832
 
833
Loading design module "../implementation/sysace_compactflash_wrapper.ngc"...
834
 
835
Loading design module
836
 
837
Loading design module "../implementation/clock_generator_0_wrapper.ngc"...
838
 
839
Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...
840
 
841
842
 
843
-------------------------------
844
 
845
  No Partitions were found in this design.
846
 
847
-------------------------------
848
 
849
NGCBUILD Design Results Summary:
850
 
851
  Number of warnings:   0
852
 
853
Writing NGC file "../implementation/system.ngc" ...
854
 
855
Total CPU time to NGCBUILD completion:   11 sec
856
 
857
Writing NGCBUILD log file "../implementation/system.blc"...
858
 
859
NGCBUILD done.
860
 
861
Running Xilinx Implementation tools..
862
 
863
xflow -wd implementation -p xc5vfx70tff1136-1 -implement xflow.opt -ise ../__xps/ise/system.ise system.ngc
864
 
865
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
866
 
867
../__xps/ise/system.ise system.ngc
868
 
869
 with local file
870
 
871
.... Copying flowfile c:/devtools/Xilinx/11.1/ISE/xilinx/data/fpga.flw into
872
 
873
C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementat
874
 
875
876
 
877
C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementat
878
 
879
Using Option File(s):
880
 
881
tion/xflow.opt
882
 
883
Creating Script File ...
884
 
885
#----------------------------------------------#
886
 
887
# ngdbuild -ise ../__xps/ise/system.ise -p xc5vfx70tff1136-1 -nt timestamp -bm
888
 
889
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/implementa
890
 
891
#----------------------------------------------#
892
 
893
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
894
 
895
 with local file
896
 
897
898
 
899
timestamp -bm system.bmm
900
 
901
ion/system.ngc -uc system.ucf system.ngd
902
 
903
Reading NGO file
904
 
905
tion/system.ngc" ...
906
 
907
Done.
908
 
909
Applying constraints in "system.ucf" to the design...
910
 
911
   'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_
912
 
913
   'VIRTEX5' to correct post-ngdbuild and timing simulation for this primitive.
914
 
915
   should be changed in this same manner in the source netlist or constraint
916
 
917
Resolving constraint associations...
918
 
919
WARNING:ConstraintSystem:3 - Constraint 
920
 
921
 
922
 
923
   found.
924
 
925
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
926
 
927
   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
928
 
929
   PLL_ADV output(s):
930
 
931
   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *
932
 
933
934
 
935
   'TS_sys_clk_pin', was traced into PLL_ADV instance
936
 
937
 
938
 
939
   CLKOUT1: 
940
 
941
   1.25 HIGH 50%>
942
 
943
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
944
 
945
 
946
 
947
   PLL_ADV output(s):
948
 
949
   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *
950
 
951
952
 
953
 
954
 
955
   The following new TNM groups and period specifications were generated at the
956
 
957
 
958
 
959
   2 HIGH 50%>
960
 
961
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
962
 
963
 
964
 
965
   PLL_ADV output(s):
966
 
967
 
968
 
969
970
 
971
 
972
 
973
Processing BMM file ...
974
 
975
WARNING:NgdBuild:1212 - User specified non-default attribute value
976
 
977
   "clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".
978
 
979
 
980
 
981
Checking expanded design ...
982
 
983
   'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_
984
 
985
   has unconnected output pin
986
 
987
 
988
 
989
WARNING:NgdBuild:443 - SFF primitive
990
 
991
 
992
 
993
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
994
 
995
   has unconnected output pin
996
 
997
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
998
 
999
   has unconnected output pin
1000
 
1001
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1002
 
1003
   RE_I' has unconnected output pin
1004
 
1005
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1006
 
1007
 
1008
 
1009
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1010
 
1011
   ' has unconnected output pin
1012
 
1013
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1014
 
1015
 
1016
 
1017
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1018
 
1019
   ' has unconnected output pin
1020
 
1021
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1022
 
1023
 
1024
 
1025
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1026
 
1027
   has unconnected output pin
1028
 
1029
 
1030
 
1031
   ' has unconnected output pin
1032
 
1033
 
1034
 
1035
WARNING:NgdBuild:443 - SFF primitive
1036
 
1037
 
1038
 
1039
WARNING:NgdBuild:443 - SFF primitive
1040
 
1041
   URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has
1042
 
1043
WARNING:NgdBuild:443 - SFF primitive
1044
 
1045
 
1046
 
1047
WARNING:NgdBuild:443 - SFF primitive
1048
 
1049
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
1050
 
1051
WARNING:NgdBuild:443 - SFF primitive
1052
 
1053
 
1054
 
1055
WARNING:NgdBuild:443 - SFF primitive
1056
 
1057
 
1058
 
1059
WARNING:NgdBuild:443 - SFF primitive
1060
 
1061
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B
1062
 
1063
WARNING:NgdBuild:443 - SFF primitive
1064
 
1065
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B
1066
 
1067
WARNING:NgdBuild:443 - SFF primitive
1068
 
1069
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B
1070
 
1071
WARNING:NgdBuild:443 - SFF primitive
1072
 
1073
 
1074
 
1075
WARNING:NgdBuild:443 - SFF primitive
1076
 
1077
   _H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin
1078
 
1079
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S
1080
 
1081
 
1082
 
1083
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected
1084
 
1085
WARNING:NgdBuild:443 - SFF primitive
1086
 
1087
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected
1088
 
1089
WARNING:NgdBuild:443 - SFF primitive
1090
 
1091
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected
1092
 
1093
WARNING:NgdBuild:443 - SFF primitive
1094
 
1095
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected
1096
 
1097
WARNING:NgdBuild:443 - SFF primitive
1098
 
1099
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected
1100
 
1101
WARNING:NgdBuild:443 - SFF primitive
1102
 
1103
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected
1104
 
1105
WARNING:NgdBuild:443 - SFF primitive
1106
 
1107
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected
1108
 
1109
WARNING:NgdBuild:443 - SFF primitive
1110
 
1111
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected
1112
 
1113
WARNING:NgdBuild:443 - SFF primitive
1114
 
1115
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected
1116
 
1117
WARNING:NgdBuild:443 - SFF primitive
1118
 
1119
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected
1120
 
1121
WARNING:NgdBuild:443 - SFF primitive
1122
 
1123
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected
1124
 
1125
WARNING:NgdBuild:443 - SFF primitive
1126
 
1127
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected
1128
 
1129
WARNING:NgdBuild:443 - SFF primitive
1130
 
1131
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected
1132
 
1133
 
1134
 
1135
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected
1136
 
1137
 
1138
 
1139
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected
1140
 
1141
WARNING:NgdBuild:443 - SFF primitive
1142
 
1143
 
1144
 
1145
WARNING:NgdBuild:443 - SFF primitive
1146
 
1147
 
1148
 
1149
WARNING:NgdBuild:443 - SFF primitive
1150
 
1151
 
1152
 
1153
WARNING:NgdBuild:443 - SFF primitive
1154
 
1155
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected
1156
 
1157
WARNING:NgdBuild:443 - SFF primitive
1158
 
1159
 
1160
 
1161
WARNING:NgdBuild:443 - SFF primitive
1162
 
1163
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected
1164
 
1165
WARNING:NgdBuild:443 - SFF primitive
1166
 
1167
 
1168
 
1169
WARNING:NgdBuild:443 - SFF primitive
1170
 
1171
 
1172
 
1173
WARNING:NgdBuild:443 - SFF primitive
1174
 
1175
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_WRCE_REG' has unconnected
1176
 
1177
WARNING:NgdBuild:443 - SFF primitive
1178
 
1179
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_CE_REG' has unconnected
1180
 
1181
WARNING:NgdBuild:443 - SFF primitive
1182
 
1183
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected
1184
 
1185
WARNING:NgdBuild:443 - SFF primitive
1186
 
1187
 
1188
 
1189
WARNING:NgdBuild:443 - SFF primitive
1190
 
1191
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected
1192
 
1193
WARNING:NgdBuild:443 - SFF primitive
1194
 
1195
 
1196
 
1197
WARNING:NgdBuild:443 - SFF primitive
1198
 
1199
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_WRCE_REG' has unconnected
1200
 
1201
WARNING:NgdBuild:443 - SFF primitive
1202
 
1203
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected
1204
 
1205
WARNING:NgdBuild:443 - SFF primitive
1206
 
1207
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has
1208
 
1209
WARNING:NgdBuild:443 - SFF primitive
1210
 
1211
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has
1212
 
1213
WARNING:NgdBuild:443 - SFF primitive
1214
 
1215
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_CE_REG' has unconnected
1216
 
1217
WARNING:NgdBuild:443 - SFF primitive
1218
 
1219
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has
1220
 
1221
WARNING:NgdBuild:443 - SFF primitive
1222
 
1223
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_WRCE_REG' has
1224
 
1225
WARNING:NgdBuild:443 - SFF primitive
1226
 
1227
 
1228
 
1229
WARNING:NgdBuild:443 - SFF primitive
1230
 
1231
 
1232
 
1233
WARNING:NgdBuild:443 - SFF primitive
1234
 
1235
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has
1236
 
1237
 
1238
 
1239
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected
1240
 
1241
 
1242
 
1243
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has
1244
 
1245
 
1246
 
1247
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has
1248
 
1249
WARNING:NgdBuild:443 - SFF primitive
1250
 
1251
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected
1252
 
1253
 
1254
 
1255
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has
1256
 
1257
WARNING:NgdBuild:443 - SFF primitive
1258
 
1259
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has
1260
 
1261
 
1262
 
1263
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected
1264
 
1265
 
1266
 
1267
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has
1268
 
1269
WARNING:NgdBuild:443 - SFF primitive
1270
 
1271
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has
1272
 
1273
WARNING:NgdBuild:443 - SFF primitive
1274
 
1275
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected
1276
 
1277
WARNING:NgdBuild:443 - SFF primitive
1278
 
1279
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has
1280
 
1281
 
1282
 
1283
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has
1284
 
1285
WARNING:NgdBuild:443 - SFF primitive
1286
 
1287
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected
1288
 
1289
 
1290
 
1291
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has
1292
 
1293
WARNING:NgdBuild:443 - SFF primitive
1294
 
1295
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has
1296
 
1297
 
1298
 
1299
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected
1300
 
1301
 
1302
 
1303
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has
1304
 
1305
WARNING:NgdBuild:443 - SFF primitive
1306
 
1307
 
1308
 
1309
WARNING:NgdBuild:443 - SFF primitive
1310
 
1311
 
1312
 
1313
WARNING:NgdBuild:443 - SFF primitive
1314
 
1315
 
1316
 
1317
WARNING:NgdBuild:443 - SFF primitive
1318
 
1319
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has
1320
 
1321
WARNING:NgdBuild:443 - SFF primitive
1322
 
1323
 
1324
 
1325
WARNING:NgdBuild:443 - SFF primitive
1326
 
1327
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has
1328
 
1329
WARNING:NgdBuild:443 - SFF primitive
1330
 
1331
 
1332
 
1333
WARNING:NgdBuild:443 - SFF primitive
1334
 
1335
 
1336
 
1337
WARNING:NgdBuild:443 - SFF primitive
1338
 
1339
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has
1340
 
1341
WARNING:NgdBuild:443 - SFF primitive
1342
 
1343
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has
1344
 
1345
WARNING:NgdBuild:443 - SFF primitive
1346
 
1347
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected
1348
 
1349
WARNING:NgdBuild:443 - SFF primitive
1350
 
1351
 
1352
 
1353
WARNING:NgdBuild:443 - SFF primitive
1354
 
1355
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_WRCE_REG' has
1356
 
1357
WARNING:NgdBuild:443 - SFF primitive
1358
 
1359
 
1360
 
1361
WARNING:NgdBuild:443 - SFF primitive
1362
 
1363
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has
1364
 
1365
WARNING:NgdBuild:443 - SFF primitive
1366
 
1367
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_WRCE_REG' has
1368
 
1369
WARNING:NgdBuild:443 - SFF primitive
1370
 
1371
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected
1372
 
1373
 
1374
 
1375
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_RDCE_REG' has
1376
 
1377
 
1378
 
1379
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_WRCE_REG' has
1380
 
1381
WARNING:NgdBuild:443 - SFF primitive
1382
 
1383
 
1384
 
1385
WARNING:NgdBuild:443 - SFF primitive
1386
 
1387
 
1388
 
1389
WARNING:NgdBuild:443 - SFF primitive
1390
 
1391
 
1392
 
1393
WARNING:NgdBuild:443 - SFF primitive
1394
 
1395
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_CE_REG' has unconnected
1396
 
1397
WARNING:NgdBuild:443 - SFF primitive
1398
 
1399
 
1400
 
1401
WARNING:NgdBuild:443 - SFF primitive
1402
 
1403
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_WRCE_REG' has
1404
 
1405
WARNING:NgdBuild:443 - SFF primitive
1406
 
1407
 
1408
 
1409
WARNING:NgdBuild:443 - SFF primitive
1410
 
1411
 
1412
 
1413
WARNING:NgdBuild:443 - SFF primitive
1414
 
1415
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has
1416
 
1417
WARNING:NgdBuild:443 - SFF primitive
1418
 
1419
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected
1420
 
1421
WARNING:NgdBuild:443 - SFF primitive
1422
 
1423
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has
1424
 
1425
WARNING:NgdBuild:443 - SFF primitive
1426
 
1427
 
1428
 
1429
WARNING:NgdBuild:443 - SFF primitive
1430
 
1431
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected
1432
 
1433
WARNING:NgdBuild:443 - SFF primitive
1434
 
1435
 
1436
 
1437
WARNING:NgdBuild:443 - SFF primitive
1438
 
1439
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_WRCE_REG' has
1440
 
1441
WARNING:NgdBuild:443 - SFF primitive
1442
 
1443
 
1444
 
1445
WARNING:NgdBuild:443 - SFF primitive
1446
 
1447
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has
1448
 
1449
 
1450
 
1451
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has
1452
 
1453
 
1454
 
1455
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected
1456
 
1457
 
1458
 
1459
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has
1460
 
1461
WARNING:NgdBuild:443 - SFF primitive
1462
 
1463
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has
1464
 
1465
 
1466
 
1467
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected
1468
 
1469
WARNING:NgdBuild:443 - SFF primitive
1470
 
1471
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected
1472
 
1473
 
1474
 
1475
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected
1476
 
1477
 
1478
 
1479
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected
1480
 
1481
 
1482
 
1483
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected
1484
 
1485
 
1486
 
1487
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected
1488
 
1489
WARNING:NgdBuild:443 - SFF primitive
1490
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1491
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected
1492
   output pin
1493
WARNING:NgdBuild:443 - SFF primitive
1494
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1495
 
1496
   output pin
1497
 
1498
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1499
 
1500
   output pin
1501
 
1502
 
1503
 
1504
   output pin
1505
 
1506
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1507
 
1508
   output pin
1509
 
1510
 
1511
 
1512
   output pin
1513
 
1514
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1515
 
1516
   output pin
1517
 
1518
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1519
 
1520
   unconnected output pin
1521
 
1522
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1523
 
1524
   unconnected output pin
1525
 
1526
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1527
 
1528
   output pin
1529
 
1530
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1531
 
1532
   unconnected output pin
1533
 
1534
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1535
 
1536
   unconnected output pin
1537
 
1538
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1539
 
1540
   output pin
1541
 
1542
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1543
 
1544
   unconnected output pin
1545
 
1546
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1547
 
1548
   unconnected output pin
1549
 
1550
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1551
 
1552
   output pin
1553
 
1554
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1555
 
1556
   unconnected output pin
1557
 
1558
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1559
 
1560
   unconnected output pin
1561
 
1562
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1563
 
1564
   output pin
1565
 
1566
 
1567
 
1568
   unconnected output pin
1569
 
1570
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1571
 
1572
 
1573
 
1574
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1575
 
1576
 
1577
 
1578
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1579
 
1580
 
1581
 
1582
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1583
 
1584
   unconnected output pin
1585
 
1586
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1587
 
1588
 
1589
 
1590
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1591
 
1592
   unconnected output pin
1593
 
1594
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1595
 
1596
 
1597
 
1598
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1599
 
1600
 
1601
 
1602
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1603
 
1604
   unconnected output pin
1605
WARNING:NgdBuild:443 - SFF primitive
1606
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1607
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has
1608
   unconnected output pin
1609
 
1610
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1611
 
1612
   output pin
1613
 
1614
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1615
 
1616
   unconnected output pin
1617
 
1618
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1619
 
1620
   unconnected output pin
1621
 
1622
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1623
 
1624
   output pin
1625
 
1626
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1627
 
1628
   unconnected output pin
1629
 
1630
 
1631
 
1632
   unconnected output pin
1633
 
1634
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1635
 
1636
   output pin
1637
 
1638
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1639
 
1640
   unconnected output pin
1641
 
1642
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1643
 
1644
 
1645
 
1646
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1647
 
1648
 
1649
 
1650
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1651
 
1652
   unconnected output pin
1653
 
1654
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1655
 
1656
   unconnected output pin
1657
 
1658
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1659
 
1660
   output pin
1661
 
1662
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1663
 
1664
   output pin
1665
 
1666
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1667
 
1668
   output pin
1669
 
1670
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1671
 
1672
   output pin
1673
 
1674
 
1675
 
1676
   output pin
1677
 
1678
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1679
 
1680
   output pin
1681
 
1682
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1683
 
1684
 
1685
 
1686
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1687
 
1688
   unconnected output pin
1689
 
1690
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1691
 
1692
   output pin
1693
 
1694
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1695
 
1696
 
1697
 
1698
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1699
 
1700
   unconnected output pin
1701
 
1702
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1703
 
1704
   output pin
1705
 
1706
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1707
 
1708
   unconnected output pin
1709
 
1710
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1711
 
1712
   unconnected output pin
1713
 
1714
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1715
 
1716
   output pin
1717
 
1718
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1719
 
1720
   unconnected output pin
1721
 
1722
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1723
 
1724
   unconnected output pin
1725
 
1726
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1727
 
1728
 
1729
 
1730
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1731
 
1732
   unconnected output pin
1733
 
1734
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1735
 
1736
   unconnected output pin
1737
 
1738
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1739
 
1740
   unconnected output pin
1741
 
1742
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1743
 
1744
   unconnected output pin
1745
 
1746
 
1747
 
1748
   unconnected output pin
1749
 
1750
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1751
 
1752
   unconnected output pin
1753
 
1754
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1755
 
1756
   unconnected output pin
1757
 
1758
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1759
 
1760
   unconnected output pin
1761
 
1762
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1763
 
1764
 
1765
 
1766
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1767
 
1768
   unconnected output pin
1769
 
1770
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1771
 
1772
   unconnected output pin
1773
 
1774
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1775
 
1776
   unconnected output pin
1777
 
1778
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1779
 
1780
   unconnected output pin
1781
 
1782
 
1783
 
1784
   unconnected output pin
1785
 
1786
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1787
 
1788
   unconnected output pin
1789
 
1790
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1791
 
1792
   unconnected output pin
1793
 
1794
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1795
 
1796
   unconnected output pin
1797
 
1798
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1799
 
1800
 
1801
 
1802
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1803
 
1804
   unconnected output pin
1805
 
1806
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1807
 
1808
   unconnected output pin
1809
 
1810
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1811
 
1812
   unconnected output pin
1813
 
1814
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1815
 
1816
   unconnected output pin
1817
 
1818
 
1819
 
1820
   unconnected output pin
1821
 
1822
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1823
 
1824
 
1825
 
1826
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1827
 
1828
 
1829
 
1830
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1831
 
1832
   unconnected output pin
1833
 
1834
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1835
 
1836
   unconnected output pin
1837
 
1838
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1839
 
1840
   unconnected output pin
1841
 
1842
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1843
 
1844
   unconnected output pin
1845
 
1846
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1847
 
1848
   unconnected output pin
1849
 
1850
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1851
 
1852
   unconnected output pin
1853
 
1854
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1855
 
1856
   unconnected output pin
1857
 
1858
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1859
 
1860
   unconnected output pin
1861
 
1862
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1863
 
1864
   unconnected output pin
1865
 
1866
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1867
 
1868
   unconnected output pin
1869
 
1870
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1871
 
1872
WARNING:NgdBuild:443 - SFF primitive
1873
 
1874
   E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin
1875
 
1876
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1877
 
1878
   output pin
1879
 
1880
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1881
 
1882
   unconnected output pin
1883
 
1884
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1885
 
1886
   unconnected output pin
1887
 
1888
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1889
 
1890
   output pin
1891
 
1892
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1893
 
1894
   unconnected output pin
1895
 
1896
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1897
 
1898
   unconnected output pin
1899
 
1900
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
1901
 
1902
WARNING:NgdBuild:443 - SFF primitive
1903
 
1904
   SIZE2_REG1' has unconnected output pin
1905
 
1906
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
1907
 
1908
WARNING:NgdBuild:443 - SFF primitive
1909
 
1910
   unconnected output pin
1911
 
1912
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected
1913
 
1914
WARNING:NgdBuild:440 - FF primitive
1915
 
1916
   has unconnected output pin
1917
 
1918
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'
1919
 
1920
WARNING:NgdBuild:440 - FF primitive
1921
 
1922
   has unconnected output pin
1923
 
1924
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU25'
1925
 
1926
WARNING:NgdBuild:440 - FF primitive
1927
 
1928
   has unconnected output pin
1929
 
1930
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'
1931
 
1932
WARNING:NgdBuild:440 - FF primitive
1933
 
1934
   has unconnected output pin
1935
 
1936
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'
1937
 
1938
WARNING:NgdBuild:440 - FF primitive
1939
 
1940
   has unconnected output pin
1941
 
1942
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU15'
1943
 
1944
WARNING:NgdBuild:440 - FF primitive
1945
 
1946
   has unconnected output pin
1947
 
1948
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU25'
1949
 
1950
WARNING:NgdBuild:440 - FF primitive
1951
 
1952
   has unconnected output pin
1953
 
1954
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'
1955
 
1956
WARNING:NgdBuild:440 - FF primitive
1957
 
1958
   has unconnected output pin
1959
 
1960
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'
1961
 
1962
WARNING:NgdBuild:440 - FF primitive
1963
 
1964
   /gen_rden[1].u_calib_rden_r' has unconnected output pin
1965
 
1966
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
1967
 
1968
WARNING:NgdBuild:440 - FF primitive
1969
 
1970
   /gen_rden[3].u_calib_rden_r' has unconnected output pin
1971
 
1972
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
1973
 
1974
WARNING:NgdBuild:440 - FF primitive
1975
 
1976
   /gen_rden[5].u_calib_rden_r' has unconnected output pin
1977
 
1978
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
1979
 
1980
WARNING:NgdBuild:440 - FF primitive
1981
 
1982
   /gen_rden[7].u_calib_rden_r' has unconnected output pin
1983
 
1984
   "clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"
1985
 
1986
WARNING:NgdBuild:452 - logical net 'N194' has no driver
1987
 
1988
WARNING:NgdBuild:452 - logical net 'N196' has no driver
1989
 
1990
WARNING:NgdBuild:452 - logical net 'N198' has no driver
1991
 
1992
WARNING:NgdBuild:452 - logical net 'N200' has no driver
1993
 
1994
WARNING:NgdBuild:452 - logical net 'N202' has no driver
1995
 
1996
WARNING:NgdBuild:452 - logical net 'N204' has no driver
1997
 
1998
WARNING:NgdBuild:452 - logical net 'N206' has no driver
1999
 
2000
WARNING:NgdBuild:452 - logical net 'N208' has no driver
2001
 
2002
WARNING:NgdBuild:452 - logical net 'N210' has no driver
2003
 
2004
WARNING:NgdBuild:452 - logical net 'N212' has no driver
2005
 
2006
WARNING:NgdBuild:452 - logical net 'N214' has no driver
2007
 
2008
WARNING:NgdBuild:452 - logical net 'N216' has no driver
2009
 
2010
WARNING:NgdBuild:452 - logical net 'N218' has no driver
2011
 
2012
WARNING:NgdBuild:452 - logical net 'N220' has no driver
2013
 
2014
WARNING:NgdBuild:452 - logical net 'N222' has no driver
2015
 
2016
WARNING:NgdBuild:452 - logical net 'N224' has no driver
2017
 
2018
WARNING:NgdBuild:452 - logical net 'N226' has no driver
2019
 
2020
WARNING:NgdBuild:452 - logical net 'N228' has no driver
2021
 
2022
WARNING:NgdBuild:452 - logical net 'N230' has no driver
2023
 
2024
WARNING:NgdBuild:452 - logical net 'N232' has no driver
2025
 
2026
WARNING:NgdBuild:452 - logical net 'N234' has no driver
2027
 
2028
WARNING:NgdBuild:452 - logical net 'N236' has no driver
2029
 
2030
WARNING:NgdBuild:452 - logical net 'N238' has no driver
2031
 
2032
WARNING:NgdBuild:452 - logical net 'N240' has no driver
2033
 
2034
WARNING:NgdBuild:452 - logical net 'N242' has no driver
2035
 
2036
WARNING:NgdBuild:452 - logical net 'N244' has no driver
2037
 
2038
WARNING:NgdBuild:452 - logical net 'N246' has no driver
2039
 
2040
WARNING:NgdBuild:452 - logical net 'N248' has no driver
2041
 
2042
WARNING:NgdBuild:452 - logical net 'N250' has no driver
2043
 
2044
WARNING:NgdBuild:452 - logical net 'N252' has no driver
2045
 
2046
WARNING:NgdBuild:452 - logical net 'N254' has no driver
2047
 
2048
WARNING:NgdBuild:452 - logical net 'N256' has no driver
2049
 
2050
WARNING:NgdBuild:452 - logical net 'N266' has no driver
2051
 
2052
WARNING:NgdBuild:452 - logical net 'N268' has no driver
2053
 
2054
WARNING:NgdBuild:452 - logical net 'N270' has no driver
2055
 
2056
WARNING:NgdBuild:452 - logical net 'N272' has no driver
2057
 
2058
WARNING:NgdBuild:452 - logical net 'N306' has no driver
2059
 
2060
WARNING:NgdBuild:452 - logical net 'N308' has no driver
2061
 
2062
WARNING:NgdBuild:452 - logical net 'N310' has no driver
2063
 
2064
WARNING:NgdBuild:452 - logical net 'N312' has no driver
2065
 
2066
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'
2067
 
2068
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'
2069
 
2070
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'
2071
 
2072
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'
2073
 
2074
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'
2075
 
2076
2077
 
2078
-------------------------------
2079
 
2080
  No Partitions were found in this design.
2081
 
2082
-------------------------------
2083
 
2084
NGDBUILD Design Results Summary:
2085
 
2086
  Number of warnings: 348
2087
 
2088
Writing NGD file "system.ngd" ...
2089
 
2090
Total CPU time to NGDBUILD completion:  1 min  21 sec
2091
 
2092
Writing NGDBUILD log file "system.bld"...
2093
 
2094
NGDBUILD done.
2095
 
2096
2097
 
2098
#----------------------------------------------#
2099
 
2100
# map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing
2101
 
2102
#----------------------------------------------#
2103
 
2104
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
2105
 
2106
 with local file
2107
 
2108
Using target part "5vfx70tff1136-1".
2109
 
2110
WARNING:LIT:395 - The above warning message is repeated 1028 more times for the
2111
 
2112
   N195,
2113
 
2114
   N197,
2115
 
2116
   N199
2117
 
2118
Mapping design into LUTs...
2119
 
2120
   connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has
2121
 
2122
WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top
2123
 
2124
WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been
2125
 
2126
Writing file system_map.ngm...
2127
 
2128
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
2129
 
2130
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig
2131
 
2132
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
2133
 
2134
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig
2135
 
2136
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
2137
 
2138
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig
2139
 
2140
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
2141
 
2142
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig
2143
 
2144
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
2145
 
2146
   of frag REGCLKAU connected to power/ground net
2147
 
2148
   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig
2149
 
2150
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
2151
 
2152
   of frag REGCLKAL connected to power/ground net
2153
 
2154
   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig
2155
 
2156
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
2157
 
2158
   of frag REGCLKAU connected to power/ground net
2159
 
2160
   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig
2161
 
2162
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
2163
 
2164
   of frag REGCLKAL connected to power/ground net
2165
 
2166
   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig
2167
 
2168
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
2169
 
2170
   of frag RDRCLKU connected to power/ground net
2171
 
2172
   x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig
2173
 
2174
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
2175
 
2176
   of frag RDRCLKL connected to power/ground net
2177
 
2178
   x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig
2179
 
2180
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
2181
 
2182
   noeccerr.SDP
2183
 
2184
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
2185
 
2186
   noeccerr.SDP_RDRCLKU_tiesig
2187
 
2188
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
2189
 
2190
   noeccerr.SDP
2191
 
2192
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
2193
 
2194
   noeccerr.SDP_RDRCLKL_tiesig
2195
 
2196
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
2197
 
2198
   ram/SDP.WIDE_PRIM36.noeccerr.SDP
2199
 
2200
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
2201
 
2202
   ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
2203
 
2204
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
2205
 
2206
   ram/SDP.WIDE_PRIM36.noeccerr.SDP
2207
 
2208
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
2209
 
2210
   ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
2211
 
2212
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
2213
 
2214
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
2215
 
2216
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
2217
 
2218
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
2219
 
2220
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
2221
 
2222
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
2223
 
2224
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
2225
 
2226
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
2227
 
2228
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
2229
 
2230
   36.noeccerr.SDP
2231
 
2232
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
2233
 
2234
   36.noeccerr.SDP_RDRCLKU_tiesig
2235
 
2236
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
2237
 
2238
   36.noeccerr.SDP
2239
 
2240
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
2241
 
2242
   36.noeccerr.SDP_RDRCLKL_tiesig
2243
 
2244
Running delay-based LUT packing...
2245
 
2246
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM
2247
 
2248
   timing analysis.
2249
 
2250
   (.mrp).
2251
 
2252
Total REAL time at the beginning of Placer: 2 mins 41 secs
2253
 
2254
2255
 
2256
Phase 1.1  Initial Placement Analysis (Checksum:9d0c7baf) REAL time: 3 mins 15 secs
2257
 
2258
Phase 2.7  Design Feasibility Check
2259
 
2260
   Components associated with this bus are as follows:
2261
 
2262
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6>   IOSTANDARD = LVCMOS25
2263
 
2264
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4>   IOSTANDARD = LVCMOS18
2265
 
2266
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2>   IOSTANDARD = LVCMOS18
2267
 
2268
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0>   IOSTANDARD = LVCMOS18
2269
 
2270
2271
 
2272
   Components associated with this bus are as follows:
2273
 
2274
         Comp: fpga_0_SRAM_Mem_DQ_pin<30>   IOSTANDARD = LVDCI_33
2275
 
2276
         Comp: fpga_0_SRAM_Mem_DQ_pin<28>   IOSTANDARD = LVDCI_33
2277
 
2278
         Comp: fpga_0_SRAM_Mem_DQ_pin<26>   IOSTANDARD = LVDCI_33
2279
 
2280
         Comp: fpga_0_SRAM_Mem_DQ_pin<24>   IOSTANDARD = LVDCI_33
2281
 
2282
         Comp: fpga_0_SRAM_Mem_DQ_pin<22>   IOSTANDARD = LVDCI_33
2283
 
2284
         Comp: fpga_0_SRAM_Mem_DQ_pin<20>   IOSTANDARD = LVDCI_33
2285
 
2286
         Comp: fpga_0_SRAM_Mem_DQ_pin<18>   IOSTANDARD = LVDCI_33
2287
 
2288
         Comp: fpga_0_SRAM_Mem_DQ_pin<16>   IOSTANDARD = LVDCI_33
2289
 
2290
         Comp: fpga_0_SRAM_Mem_DQ_pin<14>   IOSTANDARD = LVCMOS33
2291
 
2292
         Comp: fpga_0_SRAM_Mem_DQ_pin<12>   IOSTANDARD = LVCMOS33
2293
 
2294
         Comp: fpga_0_SRAM_Mem_DQ_pin<10>   IOSTANDARD = LVCMOS33
2295
 
2296
         Comp: fpga_0_SRAM_Mem_DQ_pin<8>   IOSTANDARD = LVCMOS33
2297
 
2298
         Comp: fpga_0_SRAM_Mem_DQ_pin<6>   IOSTANDARD = LVCMOS33
2299
 
2300
         Comp: fpga_0_SRAM_Mem_DQ_pin<4>   IOSTANDARD = LVCMOS33
2301
 
2302
         Comp: fpga_0_SRAM_Mem_DQ_pin<2>   IOSTANDARD = LVCMOS33
2303
 
2304
         Comp: fpga_0_SRAM_Mem_DQ_pin<0>   IOSTANDARD = LVCMOS33
2305
 
2306
2307
 
2308
2309
 
2310
Phase 3.31  Local Placement Optimization (Checksum:dec56134) REAL time: 3 mins 16 secs
2311
 
2312
Phase 4.37  Local Placement Optimization
2313
 
2314
2315
 
2316
Phase 5.33  Local Placement Optimization (Checksum:dec56134) REAL time: 13 mins
2317
 
2318
Phase 6.32  Local Placement Optimization
2319
 
2320
2321
 
2322
2323
 
2324
2325
 
2326
|------------------------------------------|------------------------------------------|
2327
 
2328
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2329
 
2330
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
2331
 
2332
|                                          |                                          |
2333
 
2334
| CLOCKREGION_X0Y6:                        | CLOCKREGION_X1Y6:                        |
2335
 
2336
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
2337
 
2338
|   0 center BUFIOs available, 0 in use    |                                          |
2339
 
2340
|------------------------------------------|------------------------------------------|
2341
 
2342
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2343
 
2344
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
2345
 
2346
|                                          |                                          |
2347
 
2348
| CLOCKREGION_X0Y4:                        | CLOCKREGION_X1Y4:                        |
2349
 
2350
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
2351
 
2352
|   2 center BUFIOs available, 0 in use    |                                          |
2353
 
2354
|------------------------------------------|------------------------------------------|
2355
 
2356
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2357
 
2358
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
2359
 
2360
|                                          |                                          |
2361
 
2362
| CLOCKREGION_X0Y2:                        | CLOCKREGION_X1Y2:                        |
2363
 
2364
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
2365
 
2366
|   2 center BUFIOs available, 0 in use    |                                          |
2367
 
2368
|------------------------------------------|------------------------------------------|
2369
 
2370
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2371
 
2372
      |
2373
 
2374
|   0 center BUFIOs available, 0 in use    |                                          |
2375
 
2376
|------------------------------------------|------------------------------------------|
2377
 
2378
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2379
 
2380
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
2381
 
2382
|                                          |                                          |
2383
 
2384
2385
 
2386
Clock-Region: 
2387
 
2388
|-----------------------------------------------------------------------------------------------------------------------------------------------------------
2389
 
2390
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
2391
 
2392
|       | Upper Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region
2393
 
2394
|       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region
2395
 
2396
|       | Lower Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region
2397
 
2398
| clock |    region   |                                                                                      -----------------------------------------------
2399
 
2400
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2401
 
2402
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2403
 
2404
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2405
 
2406
2407
 
2408
  key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4
2409
 
2410
----
2411
 
2412
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
2413
 
2414
|       | Upper Region|   8  |  0  |  0 |   60   |   60   |  1280 |   640 |  1920 |   0  |   0  |  1  |   0  | <- Available resources in the upper region
2415
 
2416
|       |CurrentRegion|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region
2417
 
2418
-|-------|-------|-------|------|------|-----|------|----------------------------------------------
2419
 
2420
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2421
 
2422
|  type |  expansion  |                                                                                      | 
2423
 
2424
| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>"
2425
 
2426
| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>"
2427
 
2428
| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>"
2429
 
2430
2431
 
2432
Clock-Region: 
2433
 
2434
|-----------------------------------------------------------------------------------------------------------------------------------------------------------
2435
 
2436
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
2437
 
2438
|       | Upper Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region
2439
 
2440
|       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region
2441
 
2442
|       | Lower Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region
2443
 
2444
| clock |    region   |                                                                                      -----------------------------------------------
2445
 
2446
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2447
 
2448
    0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>"
2449
 
2450
| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>"
2451
 
2452
| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |     0 |   0  |   0  |  0  |   0  | "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>"
2453
 
2454
2455
 
2456
2457
 
2458
######################################################################################
2459
 
2460
#
2461
 
2462
# Number of Regional Clock Networks used in this design: 8 (each network can be
2463
 
2464
#
2465
 
2466
2467
 
2468
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_bufio_dqs" LOC =
2469
 
2470
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" TNM_NET =
2471
 
2472
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" AREA_GROUP =
2473
 
2474
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" RANGE =
2475
 
2476
2477
 
2478
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" driven by "BUFIO_X0Y9"
2479
 
2480
"BUFIO_X0Y9" ;
2481
 
2482
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;
2483
 
2484
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" ;
2485
 
2486
CLOCKREGION_X0Y2;
2487
 
2488
2489
 
2490
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_bufio_dqs" LOC =
2491
 
2492
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" TNM_NET =
2493
 
2494
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" AREA_GROUP =
2495
 
2496
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" RANGE =
2497
 
2498
2499
 
2500
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" driven by "BUFIO_X0Y4"
2501
 
2502
"BUFIO_X0Y4" ;
2503
 
2504
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;
2505
 
2506
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" ;
2507
 
2508
CLOCKREGION_X0Y1;
2509
 
2510
2511
 
2512
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_bufio_dqs" LOC =
2513
 
2514
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" TNM_NET =
2515
 
2516
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" AREA_GROUP =
2517
 
2518
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" RANGE =
2519
 
2520
2521
 
2522
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" driven by "BUFIO_X0Y7"
2523
 
2524
"BUFIO_X0Y7" ;
2525
 
2526
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;
2527
 
2528
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" ;
2529
 
2530
CLOCKREGION_X0Y1;
2531
 
2532
2533
 
2534
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_bufio_dqs" LOC =
2535
 
2536
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" TNM_NET =
2537
 
2538
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" AREA_GROUP =
2539
 
2540
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" RANGE =
2541
 
2542
2543
 
2544
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" driven by "BUFIO_X0Y10"
2545
 
2546
"BUFIO_X0Y10" ;
2547
 
2548
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;
2549
 
2550
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" ;
2551
 
2552
CLOCKREGION_X0Y2;
2553
 
2554
2555
 
2556
2557
 
2558
Phase 8.36  Local Placement Optimization (Checksum:e5ad4bb9) REAL time: 13 mins 24 secs
2559
 
2560
.........................
2561
 
2562
.
2563
 
2564
.....
2565
 
2566
.....
2567
 
2568
......
2569
 
2570
.......
2571
 
2572
.......
2573
 
2574
........
2575
 
2576
........
2577
 
2578
Phase 9.30  Global Clock Region Assignment
2579
 
2580
2581
 
2582
# GLOBAL CLOCK NET DISTRIBUTION UCF REPORT:
2583
 
2584
# Number of Global Clock Regions : 16
2585
 
2586
#
2587
 
2588
2589
 
2590
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT1.CLKOUT1_BUFG_INST" LOC = "BUFGCTRL_X0Y1" ;
2591
 
2592
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.gtxclk_pll_bufg" LOC = "BUFGCTRL_X0Y29" ;
2593
 
2594
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT2.CLKOUT2_BUFG_INST" LOC = "BUFGCTRL_X0Y2" ;
2595
 
2596
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/notsame.usrclk_pll_bufg" LOC = "BUFGCTRL_X0Y28" ;
2597
 
2598
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.clkfbin_pll_bufg" LOC = "BUFGCTRL_X0Y26" ;
2599
 
2600
INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/Using_BUFG_for_CLK0.CLK0_BUFG_INST" LOC = "BUFGCTRL_X0Y7" ;
2601
 
2602
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT0.CLKOUT0_BUFG_INST" LOC = "BUFGCTRL_X0Y5" ;
2603
 
2604
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/bufg2" LOC = "BUFGCTRL_X0Y0" ;
2605
 
2606
INST "fpga_0_SRAM_ZBT_CLK_FB_pin" LOC = "IOB_X1Y111" ;
2607
 
2608
INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin" LOC = "IOB_X1Y219" ;
2609
 
2610
INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin" LOC = "IOB_X1Y105" ;
2611
 
2612
INST "fpga_0_PCIe_Bridge_RXP_pin" LOC = "IPAD_X1Y13" ;
2613
 
2614
INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin" LOC = "IPAD_X1Y17" ;
2615
 
2616
INST "fpga_0_PCIe_Bridge_TXP_pin" LOC = "OPAD_X0Y9" ;
2617
 
2618
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y0" ;
2619
 
2620
INST "ibufgds_76" LOC = "BUFDS_X0Y2" ;
2621
 
2622
# clk_125_0000MHzPLL0 driven by BUFGCTRL_X0Y1
2623
 
2624
TIMEGRP "TN_clk_125_0000MHzPLL0" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0" ;
2625
 
2626
2627
 
2628
NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;
2629
 
2630
AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X0Y1, CLOCKREGION_X0Y2, CLOCKREGION_X0Y3, CLOCKREGION_X0Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
2631
 
2632
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk driven by BUFGCTRL_X0Y29
2633
 
2634
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;
2635
 
2636
2637
 
2638
NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;
2639
 
2640
AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
2641
 
2642
# clk_125_0000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y2
2643
 
2644
TIMEGRP "TN_clk_125_0000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHzPLL0_ADJUST" ;
2645
 
2646
2647
 
2648
NET "clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" TNM_NET = "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;
2649
 
2650
AREA_GROUP "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X0Y1 ;
2651
 
2652
# PCIe_Bridge/Bridge_Clk driven by BUFGCTRL_X0Y28
2653
 
2654
TIMEGRP "TN_PCIe_Bridge/Bridge_Clk" AREA_GROUP = "CLKAG_PCIe_Bridge/Bridge_Clk" ;
2655
 
2656
2657
 
2658
NET "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" TNM_NET = "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;
2659
 
2660
AREA_GROUP "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" RANGE =   CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X1Y2, CLOCKREGION_X1Y3, CLOCKREGION_X1Y4 ;
2661
 
2662
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin driven by BUFGCTRL_X0Y26
2663
 
2664
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;
2665
 
2666
2667
 
2668
NET "clk_200_0000MHz" TNM_NET = "TN_clk_200_0000MHz" ;
2669
 
2670
AREA_GROUP "CLKAG_clk_200_0000MHz" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
2671
 
2672
# fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF driven by BUFGCTRL_X0Y7
2673
 
2674
TIMEGRP "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" AREA_GROUP = "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;
2675
 
2676
2677
 
2678
NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" TNM_NET = "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;
2679
 
2680
AREA_GROUP "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" RANGE =   CLOCKREGION_X1Y0, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;
2681
 
2682
# clk_125_0000MHz90PLL0_ADJUST driven by BUFGCTRL_X0Y5
2683
 
2684
TIMEGRP "TN_clk_125_0000MHz90PLL0_ADJUST" AREA_GROUP = "CLKAG_clk_125_0000MHz90PLL0_ADJUST" ;
2685
 
2686
2687
 
2688
NET "clk_62_5000MHzPLL0_ADJUST" TNM_NET = "TN_clk_62_5000MHzPLL0_ADJUST" ;
2689
 
2690
AREA_GROUP "CLKAG_clk_62_5000MHzPLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
2691
 
2692
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg driven by BUFGCTRL_X0Y0
2693
 
2694
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;
2695
 
2696
2697
 
2698
# This report is provided to help reproduce successful clock-region
2699
 
2700
# clock networks, in a format that is directly usable in ucf files.
2701
 
2702
#END of Global Clock Net Distribution UCF Constraints
2703
 
2704
2705
 
2706
######################################################################################
2707
 
2708
2709
 
2710
Number of Global Clock Networks: 15
2711
 
2712
Clock Region Assignment: SUCCESSFUL
2713
 
2714
Clock-Region: 
2715
 
2716
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2717
 
2718
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2719
 
2720
     12 |      0 |      0 |      0 |     80 |     80 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
2721
 
2722
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2723
 
2724
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     17 |    656 |PCIe_Bridge/Bridge_Clk
2725
 
2726
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2727
 
2728
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2729
 
2730
2731
 
2732
 key resource utilizations (used/available): global-clocks - 2/10 ;
2733
 
2734
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2735
 
2736
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2737
 
2738
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2739
 
2740
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2741
 
2742
      4 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |     24 |     52 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
2743
 
2744
      8 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |      0 |      0 |    104 |   1315 | Total
2745
 
2746
2747
 
2748
Clock-Region: 
2749
 
2750
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2751
 
2752
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2753
 
2754
     12 |      4 |      2 |      0 |     40 |     40 |      0 |      0 |      0 |      0 |      1 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
2755
 
2756
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2757
 
2758
      2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      6 |    156 |PCIe_Bridge/Bridge_Clk
2759
 
2760
      2 |      1 |      0 |      0 |      0 |     17 |      0 |      0 |      0 |      0 |      0 |      0 |     10 |    991 |clk_125_0000MHzPLL0_ADJUST
2761
 
2762
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      8 |clk_62_5000MHzPLL0_ADJUST
2763
 
2764
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2765
 
2766
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2767
 
2768
2769
 
2770
 key resource utilizations (used/available): global-clocks - 4/10 ;
2771
 
2772
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2773
 
2774
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2775
 
2776
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2777
 
2778
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2779
 
2780
      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     11 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
2781
 
2782
      0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP
2783
 
2784
      2 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |    240 |   1203 | Total
2785
 
2786
2787
 
2788
Clock-Region: 
2789
 
2790
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2791
 
2792
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2793
 
2794
     12 |      2 |      1 |      0 |     60 |     60 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
2795
 
2796
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2797
 
2798
      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     12 |clk_125_0000MHz90PLL0_ADJUST
2799
 
2800
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz
2801
 
2802
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2803
 
2804
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2805
 
2806
2807
 
2808
 key resource utilizations (used/available): global-clocks - 4/10 ;
2809
 
2810
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2811
 
2812
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2813
 
2814
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2815
 
2816
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2817
 
2818
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     90 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
2819
 
2820
      3 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     48 |    725 |clk_125_0000MHzPLL0_ADJUST
2821
 
2822
      5 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     76 |   1199 | Total
2823
 
2824
2825
 
2826
Clock-Region: 
2827
 
2828
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2829
 
2830
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2831
 
2832
      4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)
2833
 
2834
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2835
 
2836
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     86 |clk_125_0000MHz90PLL0_ADJUST
2837
 
2838
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      3 |clk_200_0000MHz
2839
 
2840
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2841
 
2842
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2843
 
2844
2845
 
2846
 key resource utilizations (used/available): global-clocks - 2/10 ;
2847
 
2848
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2849
 
2850
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2851
 
2852
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2853
 
2854
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2855
 
2856
      4 |      0 |      0 |      0 |      0 |      0 |      3 |      0 |      0 |      0 |      0 |      0 |     99 |   1148 |clk_125_0000MHzPLL0_ADJUST
2857
 
2858
      4 |      0 |      0 |      0 |      0 |      0 |      3 |      0 |      0 |      0 |      0 |      0 |     99 |   1191 | Total
2859
 
2860
2861
 
2862
Clock-Region: 
2863
 
2864
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2865
 
2866
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2867
 
2868
      4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)
2869
 
2870
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2871
 
2872
      2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     36 |clk_125_0000MHz90PLL0_ADJUST
2873
 
2874
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    219 |clk_62_5000MHzPLL0_ADJUST
2875
 
2876
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2877
 
2878
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2879
 
2880
2881
 
2882
 key resource utilizations (used/available): global-clocks - 4/10 ;
2883
 
2884
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2885
 
2886
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2887
 
2888
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2889
 
2890
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2891
 
2892
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     83 |    834 |clk_125_0000MHzPLL0_ADJUST
2893
 
2894
      0 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     37 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP
2895
 
2896
      0 |      0 |      0 |      0 |     16 |     26 |      0 |      0 |      0 |      0 |      0 |      0 |     83 |    892 | Total
2897
 
2898
2899
 
2900
Clock-Region: 
2901
 
2902
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2903
 
2904
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2905
 
2906
     12 |      2 |      1 |      0 |     60 |     60 |      0 |      0 |      0 |      0 |      2 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
2907
 
2908
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2909
 
2910
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     48 |clk_125_0000MHz90PLL0_ADJUST
2911
 
2912
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      8 |    227 |clk_62_5000MHzPLL0_ADJUST
2913
 
2914
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2915
 
2916
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2917
 
2918
2919
 
2920
 key resource utilizations (used/available): global-clocks - 1/10 ;
2921
 
2922
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2923
 
2924
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2925
 
2926
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2927
 
2928
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2929
 
2930
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2931
 
2932
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2933
 
2934
2935
 
2936
 key resource utilizations (used/available): global-clocks - 7/10 ;
2937
 
2938
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2939
 
2940
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2941
 
2942
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2943
 
2944
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2945
 
2946
      0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin
2947
 
2948
      0 |      0 |      0 |      0 |      0 |      8 |      0 |      0 |      0 |      0 |      0 |      0 |     65 |    555 |clk_125_0000MHzPLL0_ADJUST
2949
 
2950
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |    100 |clk_62_5000MHzPLL0_ADJUST
2951
 
2952
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2953
 
2954
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2955
 
2956
2957
 
2958
 key resource utilizations (used/available): global-clocks - 1/10 ;
2959
 
2960
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2961
 
2962
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2963
 
2964
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2965
 
2966
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2967
 
2968
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2969
 
2970
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2971
 
2972
2973
 
2974
 key resource utilizations (used/available): global-clocks - 2/10 ;
2975
 
2976
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2977
 
2978
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2979
 
2980
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2981
 
2982
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2983
 
2984
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |clk_62_5000MHzPLL0_ADJUST
2985
 
2986
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      8 |    347 | Total
2987
 
2988
2989
 
2990
Clock-Region: 
2991
 
2992
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2993
 
2994
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2995
 
2996
      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
2997
 
2998
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2999
 
3000
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     34 |    208 |clk_125_0000MHzPLL0_ADJUST
3001
 
3002
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     34 |    208 | Total
3003
 
3004
3005
 
3006
The above detailed report is the initial placement of the logic after the clock region assignment. The final placement
3007
 
3008
maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.
3009
 
3010
3011
 
3012
######################################################################################
3013
 
3014
3015
 
3016
3017
 
3018
Phase 10.3  Local Placement Optimization (Checksum:e5ad4bb9) REAL time: 14 mins 49 secs
3019
 
3020
Phase 11.5  Local Placement Optimization
3021
 
3022
3023
 
3024
....
3025
 
3026
.....
3027
 
3028
........
3029
 
3030
.......
3031
 
3032
.......
3033
 
3034
......
3035
 
3036
.......
3037
 
3038
......
3039
 
3040
.......
3041
 
3042
.........
3043
 
3044
.........
3045
 
3046
....
3047
 
3048
.......
3049
 
3050
.........
3051
 
3052
.....
3053
 
3054
.......
3055
 
3056
.......
3057
 
3058
.
3059
 
3060
......
3061
 
3062
.....
3063
 
3064
.....
3065
 
3066
..
3067
 
3068
.....
3069
 
3070
..
3071
 
3072
......
3073
 
3074
........
3075
 
3076
......
3077
 
3078
.
3079
 
3080
....
3081
 
3082
.....
3083
 
3084
...
3085
 
3086
......
3087
 
3088
....
3089
 
3090
...
3091
 
3092
.....
3093
 
3094
.
3095
 
3096
.....
3097
 
3098
.....
3099
 
3100
.
3101
 
3102
..
3103
 
3104
......
3105
 
3106
.
3107
 
3108
.....
3109
 
3110
.....
3111
 
3112
.....
3113
 
3114
......
3115
 
3116
Phase 12.8  Global Placement (Checksum:651fc219) REAL time: 20 mins 14 secs
3117
 
3118
Phase 13.29  Local Placement Optimization
3119
 
3120
3121
 
3122
Phase 14.5  Local Placement Optimization (Checksum:651fc219) REAL time: 20 mins 19 secs
3123
 
3124
Phase 15.18  Placement Optimization
3125
 
3126
3127
 
3128
Phase 16.5  Local Placement Optimization (Checksum:11e1af7) REAL time: 23 mins 46 secs
3129
 
3130
Phase 17.34  Placement Validation
3131
 
3132
3133
 
3134
Total CPU  time to Placer completion: 21 mins
3135
 
3136
Writing output files...
3137
 
3138
Design Summary:
3139
 
3140
Number of warnings:   50
3141
 
3142
  Number of Slice Registers:                13,531 out of  44,800   30%
3143
 
3144
    Number used as Latches:                      1
3145
 
3146
  Number of Slice LUTs:                     14,602 out of  44,800   32%
3147
 
3148
      Number using O6 output only:          12,711
3149
 
3150
      Number using O5 and O6:                  919
3151
 
3152
      Number used as Dual Port RAM:            164
3153
 
3154
        Number using O5 output only:            32
3155
 
3156
      Number used as Single Port RAM:            4
3157
 
3158
      Number used as Shift Register:           373
3159
 
3160
    Number used as exclusive route-thru:       113
3161
 
3162
    Number using O6 output only:               417
3163
 
3164
    Number using O5 and O6:                     10
3165
 
3166
Slice Logic Distribution:
3167
 
3168
  Number of LUT Flip Flop pairs used:       19,423
3169
 
3170
    Number with an unused LUT:               4,821 out of  19,423   24%
3171
 
3172
    Number of unique control sets:           1,396
3173
 
3174
      to control set restrictions:           3,277 out of  44,800    7%
3175
 
3176
  A LUT Flip Flop pair for this architecture represents one LUT paired with
3177
 
3178
  clock, reset, set, and enable signals for a registered element.
3179
 
3180
  over-mapped for a non-slice resource or if Placement fails.
3181
 
3182
  over-mapped for a non-BRAM resource or if placement fails.
3183
 
3184
IO Utilization:
3185
 
3186
    Number of LOCed IOBs:                      255 out of     255  100%
3187
 
3188
    Number of bonded IPADs:                      4 out of      50    8%
3189
 
3190
3191
 
3192
  Number of BlockRAM/FIFO:                      22 out of     148   14%
3193
 
3194
    Number using FIFO only:                      2
3195
 
3196
      Number of 36k BlockRAM used:              16
3197
 
3198
      Number of 36k FIFO used:                   2
3199
 
3200
  Number of BUFG/BUFGCTRLs:                     15 out of      32   46%
3201
 
3202
  Number of IDELAYCTRLs:                         3 out of      22   13%
3203
 
3204
  Number of BUFIOs:                              8 out of      80   10%
3205
 
3206
  Number of DSP48Es:                             3 out of     128    2%
3207
 
3208
  Number of PCIEs:                               1 out of       3   33%
3209
 
3210
  Number of PLL_ADVs:                            2 out of       6   33%
3211
 
3212
3213
 
3214
Average Fanout of Non-Clock Nets:                3.81
3215
 
3216
Peak Memory Usage:  789 MB
3217
 
3218
Total CPU time to MAP completion:   21 mins 42 secs
3219
 
3220
Mapping completed.
3221
 
3222
3223
 
3224
3225
 
3226
# Starting program par
3227
 
3228
system.pcf
3229
 
3230
Release 11.2 - par L.46 (nt)
3231
 
3232
PMSPEC -- Overriding Xilinx file  with local file
3233
 
3234
3235
 
3236
Loading device for application Rf_Device from file '5vfx70t.nph' in environment
3237
 
3238
   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
3239
 
3240
Constraints file: system.pcf.
3241
 
3242
WARNING:ConstraintSystem:65 - Constraint  [system.pcf(78662)]
3243
 
3244
3245
 
3246
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
3247
 
3248
3249
 
3250
   "TNM_CLK0" TS_MC_CLK * 4; ignored during timing analysis.
3251
 
3252
   consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.
3253
 
3254
Device speed data version:  "PRODUCTION 1.65 2009-06-01".
3255
 
3256
3257
 
3258
Device Utilization Summary:
3259
 
3260
   Number of BUFDSs                          1 out of 8      12%
3261
 
3262
   Number of BUFIOs                          8 out of 80     10%
3263
 
3264
   Number of DSP48Es                         3 out of 128     2%
3265
 
3266
      Number of LOCed FIFO36_72_EXPs         2 out of 2     100%
3267
 
3268
   Number of GTX_DUALs                       1 out of 8      12%
3269
 
3270
      Number of LOCed IDELAYCTRLs            3 out of 3     100%
3271
 
3272
   Number of ILOGICs                       131 out of 800    16%
3273
 
3274
3275
 
3276
      Number of LOCed IOBs                 255 out of 255   100%
3277
 
3278
   Number of IODELAYs                       80 out of 800    10%
3279
 
3280
3281
 
3282
      Number of LOCed IPADs                  4 out of 4     100%
3283
 
3284
   Number of JTAGPPCs                        1 out of 1     100%
3285
 
3286
   Number of External OPADs                  2 out of 32      6%
3287
 
3288
3289
 
3290
      Number of LOCed PCIEs                  1 out of 1     100%
3291
 
3292
   Number of PLL_ADVs                        2 out of 6      33%
3293
 
3294
   Number of RAMB18X2SDPs                    4 out of 148     2%
3295
 
3296
      Number of LOCed RAMB36SDP_EXPs         1 out of 6      16%
3297
 
3298
   Number of RAMB36_EXPs                    10 out of 148     6%
3299
 
3300
3301
 
3302
      Number used as Flip Flops          13529
3303
 
3304
      Number used as LatchThrus              1
3305
 
3306
   Number of Slice LUTS                  14602 out of 44800  32%
3307
 
3308
3309
 
3310
Overall effort level (-ol):   High
3311
 
3312
3313
 
3314
Finished initial Timing Analysis.  REAL time: 1 mins 5 secs
3315
 
3316
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0> has no load.  PAR will not attempt to route this
3317
 
3318
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0> has no load.  PAR will not attempt to route this
3319
 
3320
WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<31> has no load.  PAR will not attempt to route this
3321
 
3322
WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<30> has no load.  PAR will not attempt to route this
3323
 
3324
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull has no load.  PAR will not attempt to route this
3325
 
3326
Starting Router
3327
 
3328
INFO:Route:501 - One or more directed routing (DIRT) constraints generated for a specific device have been found. Note
3329
 
3330
   verify that the same connectivity is available in the target device for this implementation.
3331
 
3332
Phase  1  : 95521 unrouted;      REAL time: 1 mins 22 secs
3333
 
3334
Phase  2  : 84728 unrouted;      REAL time: 1 mins 35 secs
3335
 
3336
Phase  3  : 34551 unrouted;      REAL time: 3 mins 59 secs
3337
 
3338
Phase  4  : 34616 unrouted; (Setup:0, Hold:93713, Component Switching Limit:0)     REAL time: 4 mins 32 secs
3339
 
3340
Updating file: system.ncd with current fully routed design.
3341
 
3342
Phase  5  : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0)     REAL time: 5 mins 40 secs
3343
 
3344
Phase  6  : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0)     REAL time: 5 mins 40 secs
3345
 
3346
Phase  7  : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0)     REAL time: 5 mins 40 secs
3347
 
3348
Phase  8  : 0 unrouted; (Setup:0, Hold:92310, Component Switching Limit:0)     REAL time: 5 mins 40 secs
3349
 
3350
Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 6 mins 40 secs
3351
 
3352
Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 6 mins 55 secs
3353
 
3354
Total CPU time to Router completion: 6 mins 44 secs
3355
 
3356
Partition Implementation Status
3357
 
3358
3359
 
3360
3361
 
3362
3363
 
3364
3365
 
3366
Generating Clock Report
3367
 
3368
3369
 
3370
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
3371
 
3372
|clk_125_0000MHzPLL0_ |              |      |      |            |             |
3373
 
3374
+---------------------+--------------+------+------+------------+-------------+
3375
 
3376
|                  lk |BUFGCTRL_X0Y28| No   | 1452 |  0.412     |  2.085      |
3377
 
3378
|clk_62_5000MHzPLL0_A |              |      |      |            |             |
3379
 
3380
+---------------------+--------------+------+------+------------+-------------+
3381
 
3382
|dge/comp_block_plus/ |              |      |      |            |             |
3383
 
3384
|                  lk |BUFGCTRL_X0Y27| No   |   93 |  0.266     |  2.085      |
3385
 
3386
|fpga_0_SysACE_Compac |              |      |      |            |             |
3387
 
3388
|             n_BUFGP | BUFGCTRL_X0Y8| No   |   55 |  0.163     |  1.770      |
3389
 
3390
|fpga_0_Ethernet_MAC_ |              |      |      |            |             |
3391
 
3392
|                     |BUFGCTRL_X0Y30| No   |   12 |  0.038     |  1.879      |
3393
 
3394
|clk_125_0000MHz90PLL |              |      |      |            |             |
3395
 
3396
+---------------------+--------------+------+------+------------+-------------+
3397
 
3398
|dge/comp_block_plus/ |              |      |      |            |             |
3399
 
3400
|        lk/gt_usrclk |BUFGCTRL_X0Y29| No   |    6 |  0.058     |  1.886      |
3401
 
3402
|     clk_200_0000MHz | BUFGCTRL_X0Y4| No   |    4 |  0.100     |  1.879      |
3403
 
3404
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
3405
 
3406
|f_top/u_phy_top/u_ph |              |      |      |            |             |
3407
 
3408
+---------------------+--------------+------+------+------------+-------------+
3409
 
3410
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
3411
 
3412
| y_io/delayed_dqs<1> |        IO Clk| No   |   18 |  0.083     |  0.380      |
3413
 
3414
|fpga_0_Ethernet_MAC_ |              |      |      |            |             |
3415
 
3416
|                     |BUFGCTRL_X0Y31| No   |    6 |  0.004     |  1.941      |
3417
 
3418
|DDR2_SDRAM/DDR2_SDRA |              |      |
3419
 
3420
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
3421
 
3422
| y_io/delayed_dqs<2> |        IO Clk| No   |   18 |  0.101     |  0.425      |
3423
 
3424
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
3425
 
3426
|f_top/u_phy_top/u_ph |              |      |      |            |             |
3427
 
3428
+---------------------+--------------+------+------+------------+-------------+
3429
 
3430
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
3431
 
3432
| y_io/delayed_dqs<5> |        IO Clk| No   |   18 |  0.101     |  0.425      |
3433
 
3434
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
3435
 
3436
|f_top/u_phy_top/u_ph |              |      |      |            |             |
3437
 
3438
+---------------------+--------------+------+------+------------+-------------+
3439
 
3440
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
3441
 
3442
| y_io/delayed_dqs<6> |        IO Clk| No   |   18 |  0.096     |  0.393      |
3443
 
3444
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
3445
 
3446
|f_top/u_phy_top/u_ph |              |      |      |            |             |
3447
 
3448
+---------------------+--------------+------+------+------------+-------------+
3449
 
3450
+---------------------+--------------+------+------+------------+-------------+
3451
 
3452
|dge/comp_block_plus/ |              |      |      |            |             |
3453
 
3454
|lk/SIO/.pcie_gt_wrap |              |      |      |            |             |
3455
 
3456
+---------------------+--------------+------+------+------------+-------------+
3457
 
3458
|  t_MAC/phy_tx_clk_i |         Local|      |    9 |  2.887     |  3.720      |
3459
 
3460
|RS232_Uart_1_Interru |              |      |      |            |             |
3461
 
3462
+---------------------+--------------+------+------+------------+-------------+
3463
 
3464
|         _JTGC405TCK |         Local|      |    1 |  0.000     |  1.526      |
3465
 
3466
3467
 
3468
only delays for the net. Note this is different from Clock Skew which
3469
 
3470
the minimum and maximum path delays which includes logic delays.
3471
 
3472
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
3473
 
3474
Number of Timing Constraints that were not applied: 5
3475
 
3476
Asterisk (*) preceding a constraint indicates it was not met.
3477
 
3478
3479
 
3480
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
3481
 
3482
----------------------------------------------------------------------------------------------------------
3483
 
3484
  s HIGH 50%                                | HOLD        |     0.035ns|            |       0|           0
3485
 
3486
------------------------------------------------------------------------------------------------------
3487
 
3488
  lus/comp_endpoint/core_clk" PERIOD =      | HOLD        |     0.349ns|            |       0|           0
3489
 
3490
------------------------------------------------------------------------------------------------------
3491
 
3492
  L0_CLK_OUT_2_ = PERIOD TIMEGRP         "c | HOLD        |     0.021ns|            |       0|           0
3493
 
3494
  LK_OUT_2_" TS_sys_clk_pin *         1.25  |             |            |            |        |
3495
 
3496
------------------------------------------------------------------------------------------------------
3497
 
3498
  CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS"       | HOLD        |     1.027ns|            |       0|           0
3499
 
3500
------------------------------------------------------------------------------------------------------
3501
 
3502
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
3503
 
3504
  DELAY = 0.85 ns                           |             |            |            |        |
3505
 
3506
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0
3507
 
3508
  dqs[1].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
3509
 
3510
------------------------------------------------------------------------------------------------------
3511
 
3512
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
3513
 
3514
  DELAY = 0.85 ns                           |             |            |            |        |
3515
 
3516
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0
3517
 
3518
  dqs[2].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
3519
 
3520
------------------------------------------------------------------------------------------------------
3521
 
3522
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
3523
 
3524
  DELAY = 0.85 ns                           |             |            |            |        |
3525
 
3526
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0
3527
 
3528
  dqs[4].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
3529
 
3530
------------------------------------------------------------------------------------------------------
3531
 
3532
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
3533
 
3534
  DELAY = 0.85 ns                           |             |            |            |        |
3535
 
3536
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0
3537
 
3538
  dqs[7].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
3539
 
3540
------------------------------------------------------------------------------------------------------
3541
 
3542
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3543
 
3544
------------------------------------------------------------------------------------------------------
3545
 
3546
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3547
 
3548
------------------------------------------------------------------------------------------------------
3549
 
3550
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3551
 
3552
------------------------------------------------------------------------------------------------------
3553
 
3554
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3555
 
3556
------------------------------------------------------------------------------------------------------
3557
 
3558
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3559
 
3560
------------------------------------------------------------------------------------------------------
3561
 
3562
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3563
 
3564
------------------------------------------------------------------------------------------------------
3565
 
3566
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3567
 
3568
------------------------------------------------------------------------------------------------------
3569
 
3570
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3571
 
3572
------------------------------------------------------------------------------------------------------
3573
 
3574
  ge_Clk" TO TIMEGRP "SPLB_Clk" 8 ns        | HOLD        |     0.502ns|            |       0|           0
3575
 
3576
------------------------------------------------------------------------------------------------------
3577
 
3578
  _Clk" TO TIMEGRP "Bridge_Clk" 8 ns        | HOLD        |     0.456ns|            |       0|           0
3579
 
3580
------------------------------------------------------------------------------------------------------
3581
 
3582
  HIGH 50%                                  |             |            |            |        |
3583
 
3584
  TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | MAXDELAY    |     1.695ns|     4.305ns|       0|           0
3585
 
3586
  thernet_MAC" 6 ns                         |             |            |            |        |
3587
 
3588
  TS_clock_generator_0_clock_generator_0_PL | SETUP       |     2.151ns|     4.917ns|       0|           0
3589
 
3590
  lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |
3591
 
3592
  PHASE 2 ns HIGH 50%                       |             |            |            |        |
3593
 
3594
  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |     6.000ns|     4.000ns|       0|           0
3595
 
3596
------------------------------------------------------------------------------------------------------
3597
 
3598
  L0_CLK_OUT_3_ = PERIOD TIMEGRP         "c | HOLD        |     0.465ns|            |       0|           0
3599
 
3600
  LK_OUT_3_" TS_sys_clk_pin *         2 HIG |             |            |            |        |
3601
 
3602
------------------------------------------------------------------------------------------------------
3603
 
3604
  L0_CLK_OUT_4_ = PERIOD TIMEGRP         "c | HOLD        |     0.116ns|            |       0|           0
3605
 
3606
  LK_OUT_4_" TS_sys_clk_pin *         0.625 |             |            |            |        |
3607
 
3608
------------------------------------------------------------------------------------------------------
3609
 
3610
  UFGP" MAXSKEW = 5 ns                      |             |            |            |        |
3611
 
3612
  NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW     |     4.833ns|     0.167ns|       0|           0
3613
 
3614
------------------------------------------------------------------------------------------------------
3615
 
3616
  L0_CLK_OUT_1_ = PERIOD TIMEGRP         "c |             |            |            |        |
3617
 
3618
  LK_OUT_1_" TS_sys_clk_pin *         1.25  |             |            |            |        |
3619
 
3620
------------------------------------------------------------------------------------------------------
3621
 
3622
  GRP "TXCLK_GRP_Ethernet_MAC" TO         T |             |            |            |        |
3623
 
3624
------------------------------------------------------------------------------------------------------
3625
 
3626
  UFGP" PERIOD = 40 ns HIGH 14 ns           | HOLD        |     0.458ns|            |       0|           0
3627
 
3628
  TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM | SETUP       |    13.905ns|     6.095ns|       0|           0
3629
 
3630
     TIMEGRP "TNM_CLK0" TS_MC_CLK * 4       |             |            |            |        |
3631
 
3632
  TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FRO | SETUP       |    14.527ns|     5.473ns|       0|           0
3633
 
3634
      TIMEGRP "TNM_CLK90" TS_MC_CLK * 4     |             |            |            |        |
3635
 
3636
  TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    17.706ns|     2.294ns|       0|           0
3637
 
3638
    TS_MC_CLK * 4                           |             |            |            |        |
3639
 
3640
  TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGR | SETUP       |    18.115ns|     1.885ns|       0|           0
3641
 
3642
  TNM_CLK0" TS_MC_CLK * 4                   |             |            |            |        |
3643
 
3644
  TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    18.117ns|     1.883ns|       0|           0
3645
 
3646
    TS_MC_CLK * 4                           |             |            |            |        |
3647
 
3648
  NET "fpga_0_SysACE_CompactFlash_SysACE_CL | SETUP       |    26.887ns|     3.113ns|       0|           0
3649
 
3650
   HIGH 50%                                 |             |            |            |        |
3651
 
3652
  NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP       |    32.341ns|     7.659ns|       0|           0
3653
 
3654
------------------------------------------------------------------------------------------------------
3655
 
3656
------------------------------------------------------------------------------------------------------
3657
 
3658
  P "TNM_RDEN_SEL_MUX" TO TIMEGRP         " |             |            |            |        |
3659
 
3660
------------------------------------------------------------------------------------------------------
3661
 
3662
  s HIGH 50%                                |             |            |            |        |
3663
 
3664
3665
 
3666
Derived Constraint Report
3667
 
3668
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
3669
 
3670
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
3671
 
3672
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
3673
 
3674
| TS_MC_PHY_INIT_DATA_SEL_0     |     20.000ns|      6.095ns|          N/A|            0|            0|           21|            0|
3675
 
3676
| TS_MC_GATE_DLY                |     20.000ns|      2.294ns|          N/A|            0|            0|           40|            0|
3677
 
3678
| TS_MC_CAL_RDEN_DLY            |     20.000ns|      1.885ns|          N/A|            0|            0|            5|            0|
3679
 
3680
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
3681
 
3682
Derived Constraints for TS_sys_clk_pin
3683
 
3684
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
3685
 
3686
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
3687
 
3688
|TS_sys_clk_pin                 |     10.000ns|      4.000ns|      9.965ns|            0|            0|            0|      1090426|
3689
 
3690
| erator_0_PLL0_CLK_OUT_0_      |             |             |             |             |             |             |             |
3691
 
3692
| erator_0_PLL0_CLK_OUT_1_      |             |             |             |             |             |             |             |
3693
 
3694
| erator_0_PLL0_CLK_OUT_2_      |             |             |             |             |             |             |             |
3695
 
3696
| erator_0_PLL0_CLK_OUT_3_      |             |             |             |             |             |             |             |
3697
 
3698
| erator_0_PLL0_CLK_OUT_4_      |             |             |             |             |             |             |             |
3699
 
3700
3701
 
3702
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
3703
 
3704
3705
 
3706
Generating Pad Report.
3707
 
3708
All signals are completely routed.
3709
 
3710
WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
3711
 
3712
Loading device for application Rf_Device from file '5vlx50t.nph' in environment
3713
 
3714
INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 128
3715
 
3716
   found: 128, number successful: 128
3717
 
3718
Total CPU time to PAR completion: 7 mins 9 secs
3719
 
3720
Peak Memory Usage:  705 MB
3721
 
3722
Placer: Placement generated during map.
3723
 
3724
Timing: Completed - No errors found.
3725
 
3726
Number of error messages: 0
3727
 
3728
Number of info messages: 4
3729
 
3730
Writing design to file system.ncd
3731
 
3732
3733
 
3734
PAR done!
3735
 
3736
3737
 
3738
#----------------------------------------------#
3739
 
3740
# trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf
3741
 
3742
Release 11.2 - Trace  (nt)
3743
 
3744
3745
 
3746
PMSPEC -- Overriding Xilinx file
3747
 
3748
3749
 
3750
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
3751
 
3752
WARNING:ConstraintSystem:65 - Constraint 
3753
 
3754
   "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(78661)].
3755
 
3756
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM
3757
 
3758
   ignored during timing analysis.
3759
 
3760
   information, see the TSI report.  Please consult the Xilinx Command Line
3761
 
3762
--------------------------------------------------------------------------------
3763
 
3764
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
3765
 
3766
trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf
3767
 
3768
3769
 
3770
Physical constraint file: system.pcf
3771
 
3772
level 0)
3773
 
3774
--------------------------------------------------------------------------------
3775
 
3776
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
3777
 
3778
   unconstrained paths section(s) of the report.
3779
 
3780
   50 Ohm transmission line loading model.  For the details of this model, and
3781
 
3782
   see the device datasheet.
3783
 
3784
3785
 
3786
---------------
3787
 
3788
Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)
3789
 
3790
Constraints cover 1280410 paths, 18 nets, and 87141 connections
3791
 
3792
Design statistics:
3793
 
3794
   Maximum path delay from/to any node:   7.813ns
3795
 
3796
   Maximum net skew:   0.545ns
3797
 
3798
3799
 
3800
--------------------------------------------------------------------------------
3801
 
3802
Generating Report ...
3803
 
3804
Number of warnings: 2
3805
 
3806
Total time: 1 mins 34 secs
3807
 
3808
3809
 
3810
touch __xps/system_routed
3811
 
3812
Analyzing implementation/system.par
3813
 
3814
Running Bitgen..
3815
 
3816
cd implementation; bitgen -w -f bitgen.ut system; cd ..
3817
 
3818
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
3819
 
3820
 with local file
3821
 
3822
Loading device for application Rf_Device from file '5vfx70t.nph' in environment
3823
 
3824
   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
3825
 
3826
3827
 
3828
3829
 
3830
WARNING:PhysDesignRules:1842 - One or more GTXs are being used in this design.
3831
 
3832
   Transceiver User Guide to ensure that the design SelectIO usage meets the
3833
 
3834
WARNING:PhysDesignRules:372 - Gated clock. Clock net
3835
 
3836
   rapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not good
3837
 
3838
   flip-flop.
3839
 
3840
   Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.
3841
 
3842
   data into the flip-flop.
3843
 
3844
   > is incomplete. The signal does
3845
 
3846
WARNING:PhysDesignRules:367 - The signal
3847
 
3848
   drive any load pins in the design.
3849
 
3850
   > is incomplete. The signal does not
3851
 
3852
WARNING:PhysDesignRules:367 - The signal
3853
 
3854
   drive any load pins in the design.
3855
 
3856
   is incomplete. The signal does not drive any load pins in the design.
3857
 
3858
   block:
3859
 
3860
   used.
3861
 
3862
   block:
3863
 
3864
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
3865
 
3866
   block:
3867
 
3868
   used.
3869
 
3870
   block:
3871
 
3872
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
3873
 
3874
   block:
3875
 
3876
   used.
3877
 
3878
   block:
3879
 
3880
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
3881
 
3882
   block:
3883
 
3884
   used.
3885
 
3886
   block:
3887
 
3888
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
3889
 
3890
   block:
3891
 
3892
   used.
3893
 
3894
   block:
3895
 
3896
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
3897
 
3898
   block:
3899
 
3900
   used.
3901
 
3902
   block:
3903
 
3904
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
3905
 
3906
   block:
3907
 
3908
   used.
3909
 
3910
   block:
3911
 
3912
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
3913
 
3914
   block:
3915
 
3916
   used.
3917
 
3918
   block:
3919
 
3920
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
3921
 
3922
individual error or warning messages for more details.
3923
 
3924
Saving bit stream in "system.bit".
3925
 
3926
3927
 
3928
Done!
3929
 
3930
At Local date and time: Sat Jul 04 08:21:51 2009
3931
 
3932
3933
 
3934
*********************************************
3935
 
3936
*********************************************
3937
 
3938
-bt implementation/system.bit -o implementation/download.bit
3939
 
3940
bitinit version Xilinx EDK 11.2 Build EDK_LS3.47
3941
 
3942
3943
 
3944
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
3945
 
3946
   hs line 253 - deprecated core for architecture 'virtex5fx'!
3947
 
3948
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m
3949
 
3950
3951
 
3952
3953
 
3954
3955
 
3956
Address Map for Processor ppc440_0
3957
 
3958
  (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC
3959
 
3960
  (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0
3961
 
3962
  (0x81440000-0x8144ffff) LEDs_8Bit     plb_v46_0
3963
 
3964
  (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0
3965
 
3966
  (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0
3967
 
3968
  (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0
3969
 
3970
  (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0
3971
 
3972
  (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0
3973
 
3974
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
3975
 
3976
   C_SPLB0_P2P value to 0
3977
 
3978
Computing clock values...
3979
 
3980
   'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be
3981
 
3982
   through the clock generator IP.
3983
 
3984
INFO:EDK:1432 - Frequency for Top-Level Input Clock
3985
 
3986
   performed for IPs connected to that clock port, unless they are connected
3987
 
3988
3989
 
3990
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
3991
 
3992
   C_PLBV46_NUM_MASTERS value to 1
3993
 
3994
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
3995
 
3996
   C_PLBV46_NUM_SLAVES value to 12
3997
 
3998
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
3999
 
4000
   C_PLBV46_MID_WIDTH value to 1
4001
 
4002
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4003
 
4004
   value to 128
4005
 
4006
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
4007
 
4008
   PARAMETER C_SPLB_DWIDTH value to 128
4009
 
4010
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
4011
 
4012
   PARAMETER C_SPLB_NUM_MASTERS value to 1
4013
 
4014
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
4015
 
4016
   PARAMETER C_SPLB_SMALLEST_MASTER value to 128
4017
 
4018
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
4019
 
4020
   value to 0x2000
4021
 
4022
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
4023
 
4024
   C_PORT_DWIDTH value to 64
4025
 
4026
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
4027
 
4028
   value to 8
4029
 
4030
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01
4031
 
4032
 
4033
 
4034
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
4035
 
4036
   value to 128
4037
 
4038
 
4039
 
4040
   value to 128
4041
 
4042
 
4043
 
4044
   value to 128
4045
 
4046
 
4047
 
4048
   value to 128
4049
 
4050
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
4051
 
4052
   value to 128
4053
 
4054
 
4055
 
4056
   C_SPLB_DWIDTH value to 128
4057
 
4058
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
4059
 
4060
   C_SPLB_SMALLEST_MASTER value to 128
4061
 
4062
 
4063
 
4064
   C_MPLB_DWIDTH value to 128
4065
 
4066
 
4067
 
4068
   C_MPLB_SMALLEST_SLAVE value to 128
4069
 
4070
 
4071
 
4072
 
4073
 
4074
 
4075
 
4076
   C_SPLB_NUM_MASTERS value to 1
4077
 
4078
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
4079
 
4080
   C_SPLB_SMALLEST_MASTER value to 128
4081
 
4082
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
4083
 
4084
   C_SPLB_DWIDTH value to 128
4085
 
4086
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4087
 
4088
   C_PLBV46_NUM_MASTERS value to 1
4089
 
4090
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4091
 
4092
   C_PLBV46_NUM_SLAVES value to 1
4093
 
4094
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4095
 
4096
   C_PLBV46_MID_WIDTH value to 1
4097
 
4098
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4099
 
4100
   value to 128
4101
 
4102
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
4103
 
4104
   PARAMETER C_SPLB_DWIDTH value to 128
4105
 
4106
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
4107
 
4108
   C_SPLB_DWIDTH value to 128
4109
 
4110
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
4111
 
4112
   C_SPLB_MID_WIDTH value to 1
4113
 
4114
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
4115
 
4116
   C_SPLB_NUM_MASTERS value to 1
4117
 
4118
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
4119
 
4120
   value to 128
4121
 
4122
Checking platform address map ...
4123
 
4124
Initializing Memory...
4125
 
4126
data2mem -bm "implementation/system_bd" -bt "implementation/system.bit"  -bd
4127
 
4128
Memory Initialization completed successfully.
4129
 
4130
*********************************************
4131
 
4132
*********************************************
4133
 
4134
Release 11.2 - iMPACT L.46 (nt)
4135
 
4136
Preference Table
4137
 
4138
StartupClock         Auto_Correction
4139
 
4140
KeepSVF              False
4141
 
4142
UseHighz             False
4143
 
4144
UserLevel            Novice
4145
 
4146
svfUseTime           false
4147
 
4148
AutoDetecting cable. Please wait.
4149
 
4150
Checking cable driver.
4151
 
4152
 Driver version: src=2301, dest=2301.
4153
 
4154
13:58:07, version = 900.
4155
 
4156
 Max current requested during enumeration is 300 mA.
4157
 
4158
write (count, cmdBuffer, dataBuffer) failed C0000004.
4159
 
4160
 Setting cable speed to 6 MHz.
4161
 
4162
Firmware version = 2301.
4163
 
4164
Firmware hex file version = 2401.
4165
 
4166
Downloaded firmware version = 2401.
4167
 
4168
 PLD version = 200Dh.
4169
 
4170
INFO:iMPACT:1777 -
4171
 
4172
4173
 
4174
----------------------------------------------------------------------
4175
 
4176
INFO:iMPACT:501 - '1': Added Device xc5vfx70t successfully.
4177
 
4178
----------------------------------------------------------------------
4179
 
4180
'2': : Manufacturer's ID = Xilinx xc95144xl, Version : 5
4181
 
4182
   Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...
4183
 
4184
4185
 
4186
----------------------------------------------------------------------
4187
 
4188
INFO:iMPACT:1777 -
4189
 
4190
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
4191
 
4192
----------------------------------------------------------------------
4193
 
4194
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
4195
 
4196
----------------------------------------------------------------------
4197
 
4198
   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
4199
 
4200
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
4201
 
4202
done.
4203
 
4204
Elapsed time =      0 sec.
4205
 
4206
done.
4207
 
4208
----------------------------------------------------------------------
4209
 
4210
----------------------------------------------------------------------
4211
 
4212
Validating chain...
4213
 
4214
5: Device Temperature: Current Reading:   30.69 C, Min. Reading:   27.24 C, Max.
4215
 
4216
5: VCCINT Supply: Current Reading:   0.999 V, Min. Reading:   0.999 V, Max.
4217
 
4218
5: VCCAUX Supply: Current Reading:   2.505 V, Min. Reading:   2.505 V, Max.
4219
 
4220
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
4221
 
4222
'5': Programming device...
4223
 
4224
done.
4225
 
4226
CRC error                                         :         0
4227
 
4228
DCM locked                                        :         1
4229
 
4230
End of startup signal from Startup block          :         1
4231
 
4232
status of GWE                                     :         1
4233
 
4234
value of MODE pin M0                              :         1
4235
 
4236
Value of MODE pin M2                              :         1
4237
 
4238
Value driver in from INIT pad                     :         1
4239
 
4240
Value of DONE pin                                 :         1
4241
 
4242
Decryptor error Signal                            :         0
4243
 
4244
startup_state[18] CFG startup state machine       :         0
4245
 
4246
startup_state[20] CFG startup state machine       :         1
4247
 
4248
SPI Flash Type[22] Select                         :         1
4249
 
4250
SPI Flash Type[24] Select                         :         1
4251
 
4252
CFG bus width auto detection result               :         0
4253
 
4254
BPI address wrap around error                     :         0
4255
 
4256
read back crc error                               :         0
4257
 
4258
 Match_cycle = 2.
4259
 
4260
Elapsed time =     10 sec.
4261
 
4262
----------------------------------------------------------------------
4263
 
4264
----------------------------------------------------------------------
4265
 
4266
----------------------------------------------------------------------
4267
 
4268
----------------------------------------------------------------------
4269
 
4270
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
4271
 
4272
INFO:iMPACT - '5': Programing completed successfully.
4273
 
4274
4275
 
4276
4277
 
4278
4279
 
4280
 make -f system.make program started...
4281
 
4282
*********************************************
4283
 
4284
*********************************************
4285
 
4286
libgen
4287
 
4288
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
4289
 
4290
Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg
4291
 
4292
4293
 
4294
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
4295
 
4296
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m
4297
 
4298
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
4299
 
4300
   hs line 298 - deprecated core for architecture 'virtex5fx'!
4301
 
4302
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m
4303
 
4304
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
4305
 
4306
   hs line 298 - deprecated core for architecture 'virtex5fx'!
4307
 
4308
Checking platform configuration ...
4309
 
4310
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
4311
 
4312
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
4313
 
4314
line 290 - 1 master(s) : 1 slave(s)
4315
 
4316
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.mhs
4317
 
4318
4319
 
4320
WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
4321
 
4322
   hs line 462 - floating connection!
4323
 
4324
Performing Clock DRCs...
4325
 
4326
Performing Reset DRCs...
4327
 
4328
Overriding system level properties...
4329
 
4330
Running system level update procedures...
4331
 
4332
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
4333
 
4334
Running system level DRCs...
4335
 
4336
Performing System level DRCs on properties...
4337
 
4338
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
4339
 
4340
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\system.m
4341
 
4342
WARNING:EDK:411 - emaclite -
4343
 
4344
   ss line 83 - deprecated driver!
4345
 
4346
  - DDR2_SDRAM
4347
 
4348
  - Ethernet_MAC
4349
 
4350
  - LEDs_8Bit
4351
 
4352
  - PCIe_Bridge
4353
 
4354
  - RS232_Uart_1
4355
 
4356
  - SysACE_CompactFlash
4357
 
4358
  - xps_bram_if_cntlr_1
4359
 
4360
4361
 
4362
4363
 
4364
Staging source files.
4365
 
4366
Running generate.
4367
 
4368
Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"
4369
 
4370
"EXTRA_COMPILER_FLAGS=-g"'.
4371
 
4372
Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"
4373
 
4374
"EXTRA_COMPILER_FLAGS=-g"'.
4375
 
4376
powerpc-eabi-ar: creating ../../../lib/libxil.a
4377
 
4378
Compiling lldma
4379
 
4380
Compiling gpio
4381
 
4382
Compiling iic
4383
 
4384
Compiling uartlite
4385
 
4386
Compiling intc
4387
 
4388
 
4389
 
4390
    -mfpu=sp_full -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_SP_FPU_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../../Source/portable/GCC/PPC440_Xilinx -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
4391
 
4392
powerpc-eabi-size RTOSDemo/executable.elf
4393
 
4394
 
4395
 
4396
4397
 
4398
4399
 
4400
4401
 
4402
4403
 
4404
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
4405
 
4406
Done writing Tab View settings to:
4407
 
4408
4409
 
4410
4411
 
4412
4413
 
4414
4415
 
4416
4417
 
4418
 
4419
 
4420
 
4421
 
4422
rm -f __xps/ise/_xmsgs/platgen.xmsgs
4423
 
4424
rm -f implementation/system.bit
4425
 
4426
rm -f implementation/system_bd.bmm
4427
 
4428
rm -f __xps/system_routed
4429
 
4430
rm -rf xst.srp system.srp
4431
 
4432
4433
 
4434
Done!
4435
 
4436
At Local date and time: Sun Jul 05 09:36:23 2009
4437
 
4438
4439
 
4440
rm -f libgen.log
4441
 
4442
rm -f RTOSDemo/executable.elf
4443
 
4444
4445
 
4446
4447
 
4448
4449
 
4450
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_SP_FPU_Xilinx_Virtex5_GCC\__xps\system.filters
4451
 
4452
Done writing Tab View settings to:
4453
 
4454
4455
 

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