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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC440_SP_FPU_Xilinx_Virtex5_GCC/] [system.mhs] - Blame information for rev 659

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# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 11.1 Build EDK_L.29.1
# Sat Jun 13 13:14:11 2009
# Target Board:  Xilinx Virtex 5 ML507 Evaluation Platform Rev A
# Family:    virtex5
# Device:    xc5vfx70t
# Package:   ff1136
# Speed Grade:  -1
# Processor number: 1
# Processor 1: ppc440_0
# Processor clock frequency: 125.0
# Bus clock frequency: 125.0
# Debug Interface: FPGA JTAG
# ##############################################################################
 PARAMETER VERSION = 2.1.0
 
 
 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
 PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]
 PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO_pin, DIR = IO, VEC = [0:4]
 PORT fpga_0_Push_Buttons_5Bit_GPIO_IO_pin = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin, DIR = IO, VEC = [0:4]
 PORT fpga_0_DIP_Switches_8Bit_GPIO_IO_pin = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]
 PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda_pin, DIR = IO
 PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl_pin, DIR = IO
 PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat, DIR = O, VEC = [7:30]
 PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN_pin, DIR = O
 PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN_pin, DIR = O
 PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN_pin, DIR = O
 PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN_pin, DIR = O, VEC = [0:3]
 PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN_pin, DIR = O
 PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ_pin, DIR = IO, VEC = [0:31]
 PORT fpga_0_SRAM_ZBT_CLK_OUT_pin = SRAM_CLK_OUT_s, DIR = O
 PORT fpga_0_SRAM_ZBT_CLK_FB_pin = SRAM_CLK_FB_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000
 PORT fpga_0_PCIe_Bridge_RXN_pin = fpga_0_PCIe_Bridge_RXN_pin, DIR = I
 PORT fpga_0_PCIe_Bridge_RXP_pin = fpga_0_PCIe_Bridge_RXP_pin, DIR = I
 PORT fpga_0_PCIe_Bridge_TXN_pin = fpga_0_PCIe_Bridge_TXN_pin, DIR = O
 PORT fpga_0_PCIe_Bridge_TXP_pin = fpga_0_PCIe_Bridge_TXP_pin, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk_pin, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk_pin, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs_pin, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv_pin, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data_pin, DIR = I, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col_pin, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er_pin, DIR = I
 PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n_pin, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en_pin, DIR = O
 PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data_pin, DIR = O, VEC = [3:0]
 PORT fpga_0_Ethernet_MAC_MDINT_pin = fpga_0_Ethernet_MAC_MDINT_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM
 PORT fpga_0_DDR2_SDRAM_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DIR = IO, VEC = [63:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DIR = IO, VEC = [7:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin, DIR = IO, VEC = [7:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_A_pin = fpga_0_DDR2_SDRAM_DDR2_A_pin, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_BA_pin = fpga_0_DDR2_SDRAM_DDR2_BA_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_WE_N_pin = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_CS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_CKE_pin = fpga_0_DDR2_SDRAM_DDR2_CKE_pin, DIR = O
 PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM_pin, DIR = O, VEC = [7:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_CK_pin = fpga_0_DDR2_SDRAM_DDR2_CK_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR2_SDRAM_DDR2_CK_N_pin = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin, DIR = O, VEC = [1:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin, DIR = O, VEC = [6:0]
 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR = I
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR = I
 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR = O
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR = IO, VEC = [15:0]
 PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
 PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK
 PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK
 
 
BEGIN ppc440_virtex5
 PARAMETER INSTANCE = ppc440_0
 PARAMETER C_IDCR_BASEADDR = 0b0000000000
 PARAMETER C_IDCR_HIGHADDR = 0b0011111111
 PARAMETER C_APU_CONTROL = 0b00000010000000001
 PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x003FFE00
 PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00C00000
 PARAMETER C_PPC440MC_CONTROL = 0xF810008F
 PARAMETER C_SPLB0_USE_MPLB_ADDR = 1
 PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 1
 PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_SPLB0_RNG0_MPLB_BASEADDR = 0x80000000
 PARAMETER C_SPLB0_RNG0_MPLB_HIGHADDR = 0xffffffff
 PARAMETER C_SPLB0_RNG_MC_BASEADDR = 0x00000000
 PARAMETER C_SPLB0_RNG_MC_HIGHADDR = 0x0fffffff
 BUS_INTERFACE MPLB = plb_v46_0
 BUS_INTERFACE SPLB0 = ppc440_0_SPLB0
 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
 BUS_INTERFACE MFCB = ppc440_0_fcb_v20
 BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
 BUS_INTERFACE RESETPPC = ppc_reset_bus
 PORT CPMC440CLK = clk_125_0000MHzPLL0
 PORT CPMINTERCONNECTCLK = clk_125_0000MHzPLL0
 PORT CPMINTERCONNECTCLKNTO1 = net_vcc
 PORT EICC440EXTIRQ = ppc440_0_EICC440EXTIRQ
 PORT CPMMCCLK = clk_125_0000MHzPLL0_ADJUST
 PORT CPMPPCMPLBCLK = clk_125_0000MHzPLL0_ADJUST
 PORT CPMPPCS0PLBCLK = clk_125_0000MHzPLL0_ADJUST
END
 
BEGIN plb_v46
 PARAMETER INSTANCE = plb_v46_0
 PARAMETER C_DCR_INTFCE = 0
 PARAMETER C_FAMILY = virtex5
 PARAMETER HW_VER = 1.04.a
 PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST
 PORT SYS_Rst = sys_bus_reset
END
 
BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER C_SPLB_NATIVE_DWIDTH = 64
 PARAMETER C_SPLB_SUPPORT_BURSTS = 1
 PARAMETER C_SPLB_P2P = 0
 PARAMETER C_FAMILY = virtex5
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0xffffe000
 PARAMETER C_HIGHADDR = 0xffffffff
 BUS_INTERFACE SPLB = plb_v46_0
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END
 
BEGIN bram_block
 PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
 PARAMETER C_FAMILY = virtex5
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END
 
BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_Uart_1
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT RX = fpga_0_RS232_Uart_1_RX_pin
 PORT TX = fpga_0_RS232_Uart_1_TX_pin
 PORT Interrupt = RS232_Uart_1_Interrupt
END
 
BEGIN xps_gpio
 PARAMETER INSTANCE = LEDs_8Bit
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81440000
 PARAMETER C_HIGHADDR = 0x8144ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO_pin
END
 
BEGIN xps_gpio
 PARAMETER INSTANCE = LEDs_Positions
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_ALL_INPUTS = 0
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81420000
 PARAMETER C_HIGHADDR = 0x8142ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO_pin
END
 
BEGIN xps_gpio
 PARAMETER INSTANCE = Push_Buttons_5Bit
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_GPIO_WIDTH = 5
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81400000
 PARAMETER C_HIGHADDR = 0x8140ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin
END
 
BEGIN xps_gpio
 PARAMETER INSTANCE = DIP_Switches_8Bit
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_ALL_INPUTS = 1
 PARAMETER C_GPIO_WIDTH = 8
 PARAMETER C_INTERRUPT_PRESENT = 0
 PARAMETER C_IS_DUAL = 0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81460000
 PARAMETER C_HIGHADDR = 0x8146ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT GPIO_IO = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin
END
 
BEGIN xps_iic
 PARAMETER INSTANCE = IIC_EEPROM
 PARAMETER C_IIC_FREQ = 100000
 PARAMETER C_TEN_BIT_ADR = 0
 PARAMETER C_FAMILY = virtex5
 PARAMETER HW_VER = 2.01.a
 PARAMETER C_BASEADDR = 0x81600000
 PARAMETER C_HIGHADDR = 0x8160ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT Sda = fpga_0_IIC_EEPROM_Sda_pin
 PORT Scl = fpga_0_IIC_EEPROM_Scl_pin
END
 
BEGIN xps_mch_emc
 PARAMETER INSTANCE = SRAM
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_NUM_CHANNELS = 0
 PARAMETER C_MEM0_WIDTH = 32
 PARAMETER C_MAX_MEM_WIDTH = 32
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
 PARAMETER C_SYNCH_MEM_0 = 1
 PARAMETER C_TCEDV_PS_MEM_0 = 0
 PARAMETER C_TAVDV_PS_MEM_0 = 0
 PARAMETER C_THZCE_PS_MEM_0 = 0
 PARAMETER C_THZOE_PS_MEM_0 = 0
 PARAMETER C_TWC_PS_MEM_0 = 0
 PARAMETER C_TWP_PS_MEM_0 = 0
 PARAMETER C_TLZWE_PS_MEM_0 = 0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_MEM0_BASEADDR = 0xf8000000
 PARAMETER C_MEM0_HIGHADDR = 0xf80fffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT RdClk = clk_125_0000MHzPLL0_ADJUST
 PORT Mem_A = 0b0000000 & fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat & 0b0
 PORT Mem_CEN = fpga_0_SRAM_Mem_CEN_pin
 PORT Mem_OEN = fpga_0_SRAM_Mem_OEN_pin
 PORT Mem_WEN = fpga_0_SRAM_Mem_WEN_pin
 PORT Mem_BEN = fpga_0_SRAM_Mem_BEN_pin
 PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN_pin
 PORT Mem_DQ = fpga_0_SRAM_Mem_DQ_pin
END
 
BEGIN plbv46_pcie
 PARAMETER INSTANCE = PCIe_Bridge
 PARAMETER C_FAMILY = virtex5
 PARAMETER C_IPIFBAR_NUM = 2
 PARAMETER C_PCIBAR_NUM = 1
 PARAMETER C_DEVICE_ID = 0x0505
 PARAMETER C_VENDOR_ID = 0x10EE
 PARAMETER C_CLASS_CODE = 0x058000
 PARAMETER C_REV_ID = 0x00
 PARAMETER C_SUBSYSTEM_ID = 0x0000
 PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x0000
 PARAMETER C_COMP_TIMEOUT = 1
 PARAMETER C_IPIFBAR2PCIBAR_0 = 0x00000000
 PARAMETER C_IPIFBAR2PCIBAR_1 = 0x00000000
 PARAMETER C_PCIBAR2IPIFBAR_0 = 0xf8000000
 PARAMETER C_PCIBAR2IPIFBAR_1 = 0x00000000
 PARAMETER C_PCIBAR_LEN_0 = 20
 PARAMETER C_PCIBAR_LEN_1 = 28
 PARAMETER C_BOARD = ml507
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x85c00000
 PARAMETER C_HIGHADDR = 0x85c0ffff
 PARAMETER C_IPIFBAR_0 = 0xc0000000
 PARAMETER C_IPIFBAR_HIGHADDR_0 = 0xdfffffff
 PARAMETER C_IPIFBAR_1 = 0xe0000000
 PARAMETER C_IPIFBAR_HIGHADDR_1 = 0xefffffff
 BUS_INTERFACE SPLB = plb_v46_0
 BUS_INTERFACE MPLB = ppc440_0_SPLB0
 PORT PERSTN = net_vcc
 PORT REFCLK = PCIe_Diff_Clk
 PORT RXN = fpga_0_PCIe_Bridge_RXN_pin
 PORT RXP = fpga_0_PCIe_Bridge_RXP_pin
 PORT TXN = fpga_0_PCIe_Bridge_TXN_pin
 PORT TXP = fpga_0_PCIe_Bridge_TXP_pin
 PORT MSI_request = net_gnd
END
 
BEGIN plb_v46
 PARAMETER INSTANCE = ppc440_0_SPLB0
 PARAMETER C_FAMILY = virtex5
 PARAMETER HW_VER = 1.04.a
 PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST
 PORT SYS_Rst = sys_bus_reset
END
 
BEGIN xps_ethernetlite
 PARAMETER INSTANCE = Ethernet_MAC
 PARAMETER C_FAMILY = virtex5
 PARAMETER HW_VER = 2.01.a
 PARAMETER C_BASEADDR = 0x81000000
 PARAMETER C_HIGHADDR = 0x8100ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk_pin
 PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk_pin
 PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs_pin
 PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv_pin
 PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data_pin
 PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col_pin
 PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er_pin
 PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n_pin
 PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en_pin
 PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data_pin
END
 
BEGIN ppc440mc_ddr2
 PARAMETER INSTANCE = DDR2_SDRAM
 PARAMETER C_DDR_BAWIDTH = 2
 PARAMETER C_NUM_CLK_PAIRS = 2
 PARAMETER C_DDR_DWIDTH = 64
 PARAMETER C_DDR_CAWIDTH = 10
 PARAMETER C_NUM_RANKS_MEM = 1
 PARAMETER C_CS_BITS = 0
 PARAMETER C_DDR_DM_WIDTH = 8
 PARAMETER C_DQ_BITS = 8
 PARAMETER C_DDR2_ODT_WIDTH = 2
 PARAMETER C_DDR2_ADDT_LAT = 0
 PARAMETER C_INCLUDE_ECC_SUPPORT = 0
 PARAMETER C_DDR2_ODT_SETTING = 1
 PARAMETER C_DQS_BITS = 3
 PARAMETER C_DDR_DQS_WIDTH = 8
 PARAMETER C_DDR_RAWIDTH = 13
 PARAMETER C_DDR_BURST_LENGTH = 4
 PARAMETER C_DDR_CAS_LAT = 4
 PARAMETER C_REG_DIMM = 0
 PARAMETER C_MIB_MC_CLOCK_RATIO = 1
 PARAMETER C_DDR_TREFI = 3900
 PARAMETER C_DDR_TRAS = 40000
 PARAMETER C_DDR_TRCD = 15000
 PARAMETER C_DDR_TRFC = 75000
 PARAMETER C_DDR_TRP = 15000
 PARAMETER C_DDR_TRTP = 7500
 PARAMETER C_DDR_TWR = 15000
 PARAMETER C_DDR_TWTR = 7500
 PARAMETER C_MC_MIBCLK_PERIOD_PS = 8000
 PARAMETER C_IDEL_HIGH_PERF = TRUE
 PARAMETER C_NUM_IDELAYCTRL = 3
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1
 PARAMETER C_DQS_IO_COL = 0b000000000000000000
 PARAMETER C_DQ_IO_MS = 0b000000000111010100111101000011110001111000101110110000111100000110111100
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_MEM_BASEADDR = 0x00000000
 PARAMETER C_MEM_HIGHADDR = 0x0fffffff
 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
 PORT mc_mibclk = clk_125_0000MHzPLL0_ADJUST
 PORT mi_mcclk90 = clk_125_0000MHz90PLL0_ADJUST
 PORT mi_mcreset = sys_bus_reset
 PORT mi_mcclkdiv2 = clk_62_5000MHzPLL0_ADJUST
 PORT mi_mcclk_200 = clk_200_0000MHz
 PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ_pin
 PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS_pin
 PORT DDR2_DQS_N = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin
 PORT DDR2_A = fpga_0_DDR2_SDRAM_DDR2_A_pin
 PORT DDR2_BA = fpga_0_DDR2_SDRAM_DDR2_BA_pin
 PORT DDR2_RAS_N = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin
 PORT DDR2_CAS_N = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin
 PORT DDR2_WE_N = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin
 PORT DDR2_CS_N = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin
 PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT_pin
 PORT DDR2_CKE = fpga_0_DDR2_SDRAM_DDR2_CKE_pin
 PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM_pin
 PORT DDR2_CK = fpga_0_DDR2_SDRAM_DDR2_CK_pin
 PORT DDR2_CK_N = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin
END
 
BEGIN xps_sysace
 PARAMETER INSTANCE = SysACE_CompactFlash
 PARAMETER C_MEM_WIDTH = 16
 PARAMETER C_FAMILY = virtex5
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x83600000
 PARAMETER C_HIGHADDR = 0x8360ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin
 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin
 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin
 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin
 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin
END
 
BEGIN fcb_v20
 PARAMETER INSTANCE = ppc440_0_fcb_v20
 PARAMETER HW_VER = 1.00.a
 PORT FCB_CLK = clk_125_0000MHzPLL0_ADJUST
 PORT SYS_RST = sys_bus_reset
END
 
BEGIN apu_fpu_virtex5
 PARAMETER INSTANCE = ppc440_0_apu_fpu_virtex5
 PARAMETER C_DOUBLE_PRECISION = 0
 PARAMETER HW_VER = 1.01.a
 BUS_INTERFACE SFCB2 = ppc440_0_fcb_v20
END
 
BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER C_CLKIN_FREQ = 100000000
 PARAMETER C_CLKFBIN_FREQ = 125000000
 PARAMETER C_CLKOUT0_FREQ = 125000000
 PARAMETER C_CLKOUT0_PHASE = 90
 PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT0_BUF = TRUE
 PARAMETER C_CLKOUT1_FREQ = 125000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = PLL0
 PARAMETER C_CLKOUT1_BUF = TRUE
 PARAMETER C_CLKOUT2_FREQ = 125000000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT2_BUF = TRUE
 PARAMETER C_CLKOUT3_FREQ = 200000000
 PARAMETER C_CLKOUT3_PHASE = 0
 PARAMETER C_CLKOUT3_GROUP = NONE
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER C_CLKOUT4_FREQ = 62500000
 PARAMETER C_CLKOUT4_PHASE = 0
 PARAMETER C_CLKOUT4_GROUP = PLL0_ADJUST
 PARAMETER C_CLKOUT4_BUF = TRUE
 PARAMETER C_CLKFBOUT_FREQ = 125000000
 PARAMETER C_CLKFBOUT_BUF = TRUE
 PARAMETER HW_VER = 3.01.a
 PORT CLKIN = dcm_clk_s
 PORT CLKFBIN = SRAM_CLK_FB_s
 PORT CLKOUT0 = clk_125_0000MHz90PLL0_ADJUST
 PORT CLKOUT1 = clk_125_0000MHzPLL0
 PORT CLKOUT2 = clk_125_0000MHzPLL0_ADJUST
 PORT CLKOUT3 = clk_200_0000MHz
 PORT CLKOUT4 = clk_62_5000MHzPLL0_ADJUST
 PORT CLKFBOUT = SRAM_CLK_OUT_s
 PORT RST = net_gnd
 PORT LOCKED = Dcm_all_locked
END
 
BEGIN jtagppc_cntlr
 PARAMETER INSTANCE = jtagppc_cntlr_inst
 PARAMETER HW_VER = 2.01.c
 BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus
END
 
BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 0
 PARAMETER HW_VER = 2.00.a
 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
 PORT Slowest_sync_clk = clk_125_0000MHzPLL0_ADJUST
 PORT Ext_Reset_In = sys_rst_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END
 
BEGIN xps_intc
 PARAMETER INSTANCE = xps_intc_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_BASEADDR = 0x81800000
 PARAMETER C_HIGHADDR = 0x8180ffff
 BUS_INTERFACE SPLB = plb_v46_0
 PORT Intr = fpga_0_Ethernet_MAC_MDINT_pin&RS232_Uart_1_Interrupt
 PORT Irq = ppc440_0_EICC440EXTIRQ
END
 

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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC440_SP_FPU_Xilinx_Virtex5_GCC/] [system.mhs] - Blame information for rev 659

Line No.	Rev	Author	Line
1	586	jeremybenn
2			`# ##############################################################################`
3			`# Created by Base System Builder Wizard for Xilinx EDK 11.1 Build EDK_L.29.1`
4			`# Sat Jun 13 13:14:11 2009`
5			`# Target Board: Xilinx Virtex 5 ML507 Evaluation Platform Rev A`
6			`# Family: virtex5`
7			`# Device: xc5vfx70t`
8			`# Package: ff1136`
9			`# Speed Grade: -1`
10			`# Processor number: 1`
11			`# Processor 1: ppc440_0`
12			`# Processor clock frequency: 125.0`
13			`# Bus clock frequency: 125.0`
14			`# Debug Interface: FPGA JTAG`
15			`# ##############################################################################`
16			`PARAMETER VERSION = 2.1.0`
17
18
19			`PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I`
20			`PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O`
21			`PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]`
22			`PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO_pin, DIR = IO, VEC = [0:4]`
23			`PORT fpga_0_Push_Buttons_5Bit_GPIO_IO_pin = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin, DIR = IO, VEC = [0:4]`
24			`PORT fpga_0_DIP_Switches_8Bit_GPIO_IO_pin = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]`
25			`PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda_pin, DIR = IO`
26			`PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl_pin, DIR = IO`
27			`PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat, DIR = O, VEC = [7:30]`
28			`PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN_pin, DIR = O`
29			`PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN_pin, DIR = O`
30			`PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN_pin, DIR = O`
31			`PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN_pin, DIR = O, VEC = [0:3]`
32			`PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN_pin, DIR = O`
33			`PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ_pin, DIR = IO, VEC = [0:31]`
34			`PORT fpga_0_SRAM_ZBT_CLK_OUT_pin = SRAM_CLK_OUT_s, DIR = O`
35			`PORT fpga_0_SRAM_ZBT_CLK_FB_pin = SRAM_CLK_FB_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000`
36			`PORT fpga_0_PCIe_Bridge_RXN_pin = fpga_0_PCIe_Bridge_RXN_pin, DIR = I`
37			`PORT fpga_0_PCIe_Bridge_RXP_pin = fpga_0_PCIe_Bridge_RXP_pin, DIR = I`
38			`PORT fpga_0_PCIe_Bridge_TXN_pin = fpga_0_PCIe_Bridge_TXN_pin, DIR = O`
39			`PORT fpga_0_PCIe_Bridge_TXP_pin = fpga_0_PCIe_Bridge_TXP_pin, DIR = O`
40			`PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk_pin, DIR = I`
41			`PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk_pin, DIR = I`
42			`PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs_pin, DIR = I`
43			`PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv_pin, DIR = I`
44			`PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data_pin, DIR = I, VEC = [3:0]`
45			`PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col_pin, DIR = I`
46			`PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er_pin, DIR = I`
47			`PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n_pin, DIR = O`
48			`PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en_pin, DIR = O`
49			`PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data_pin, DIR = O, VEC = [3:0]`
50			`PORT fpga_0_Ethernet_MAC_MDINT_pin = fpga_0_Ethernet_MAC_MDINT_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM`
51			`PORT fpga_0_DDR2_SDRAM_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DIR = IO, VEC = [63:0]`
52			`PORT fpga_0_DDR2_SDRAM_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DIR = IO, VEC = [7:0]`
53			`PORT fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin, DIR = IO, VEC = [7:0]`
54			`PORT fpga_0_DDR2_SDRAM_DDR2_A_pin = fpga_0_DDR2_SDRAM_DDR2_A_pin, DIR = O, VEC = [12:0]`
55			`PORT fpga_0_DDR2_SDRAM_DDR2_BA_pin = fpga_0_DDR2_SDRAM_DDR2_BA_pin, DIR = O, VEC = [1:0]`
56			`PORT fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin, DIR = O`
57			`PORT fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin, DIR = O`
58			`PORT fpga_0_DDR2_SDRAM_DDR2_WE_N_pin = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin, DIR = O`
59			`PORT fpga_0_DDR2_SDRAM_DDR2_CS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin, DIR = O`
60			`PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DIR = O, VEC = [1:0]`
61			`PORT fpga_0_DDR2_SDRAM_DDR2_CKE_pin = fpga_0_DDR2_SDRAM_DDR2_CKE_pin, DIR = O`
62			`PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM_pin, DIR = O, VEC = [7:0]`
63			`PORT fpga_0_DDR2_SDRAM_DDR2_CK_pin = fpga_0_DDR2_SDRAM_DDR2_CK_pin, DIR = O, VEC = [1:0]`
64			`PORT fpga_0_DDR2_SDRAM_DDR2_CK_N_pin = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin, DIR = O, VEC = [1:0]`
65			`PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin, DIR = O, VEC = [6:0]`
66			`PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR = I`
67			`PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR = I`
68			`PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR = O`
69			`PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR = O`
70			`PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR = O`
71			`PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR = IO, VEC = [15:0]`
72			`PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000`
73			`PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0`
74			`PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK`
75			`PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK`
76
77
78			`BEGIN ppc440_virtex5`
79			`PARAMETER INSTANCE = ppc440_0`
80			`PARAMETER C_IDCR_BASEADDR = 0b0000000000`
81			`PARAMETER C_IDCR_HIGHADDR = 0b0011111111`
82			`PARAMETER C_APU_CONTROL = 0b00000010000000001`
83			`PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x003FFE00`
84			`PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00C00000`
85			`PARAMETER C_PPC440MC_CONTROL = 0xF810008F`
86			`PARAMETER C_SPLB0_USE_MPLB_ADDR = 1`
87			`PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 1`
88			`PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0`
89			`PARAMETER HW_VER = 1.01.a`
90			`PARAMETER C_SPLB0_RNG0_MPLB_BASEADDR = 0x80000000`
91			`PARAMETER C_SPLB0_RNG0_MPLB_HIGHADDR = 0xffffffff`
92			`PARAMETER C_SPLB0_RNG_MC_BASEADDR = 0x00000000`
93			`PARAMETER C_SPLB0_RNG_MC_HIGHADDR = 0x0fffffff`
94			`BUS_INTERFACE MPLB = plb_v46_0`
95			`BUS_INTERFACE SPLB0 = ppc440_0_SPLB0`
96			`BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC`
97			`BUS_INTERFACE MFCB = ppc440_0_fcb_v20`
98			`BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus`
99			`BUS_INTERFACE RESETPPC = ppc_reset_bus`
100			`PORT CPMC440CLK = clk_125_0000MHzPLL0`
101			`PORT CPMINTERCONNECTCLK = clk_125_0000MHzPLL0`
102			`PORT CPMINTERCONNECTCLKNTO1 = net_vcc`
103			`PORT EICC440EXTIRQ = ppc440_0_EICC440EXTIRQ`
104			`PORT CPMMCCLK = clk_125_0000MHzPLL0_ADJUST`
105			`PORT CPMPPCMPLBCLK = clk_125_0000MHzPLL0_ADJUST`
106			`PORT CPMPPCS0PLBCLK = clk_125_0000MHzPLL0_ADJUST`
107			`END`
108
109			`BEGIN plb_v46`
110			`PARAMETER INSTANCE = plb_v46_0`
111			`PARAMETER C_DCR_INTFCE = 0`
112			`PARAMETER C_FAMILY = virtex5`
113			`PARAMETER HW_VER = 1.04.a`
114			`PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST`
115			`PORT SYS_Rst = sys_bus_reset`
116			`END`
117
118			`BEGIN xps_bram_if_cntlr`
119			`PARAMETER INSTANCE = xps_bram_if_cntlr_1`
120			`PARAMETER C_SPLB_NATIVE_DWIDTH = 64`
121			`PARAMETER C_SPLB_SUPPORT_BURSTS = 1`
122			`PARAMETER C_SPLB_P2P = 0`
123			`PARAMETER C_FAMILY = virtex5`
124			`PARAMETER HW_VER = 1.00.b`
125			`PARAMETER C_BASEADDR = 0xffffe000`
126			`PARAMETER C_HIGHADDR = 0xffffffff`
127			`BUS_INTERFACE SPLB = plb_v46_0`
128			`BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port`
129			`END`
130
131			`BEGIN bram_block`
132			`PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram`
133			`PARAMETER C_FAMILY = virtex5`
134			`PARAMETER HW_VER = 1.00.a`
135			`BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port`
136			`END`
137
138			`BEGIN xps_uartlite`
139			`PARAMETER INSTANCE = RS232_Uart_1`
140			`PARAMETER C_FAMILY = virtex5`
141			`PARAMETER C_BAUDRATE = 9600`
142			`PARAMETER C_DATA_BITS = 8`
143			`PARAMETER C_USE_PARITY = 0`
144			`PARAMETER C_ODD_PARITY = 0`
145			`PARAMETER HW_VER = 1.01.a`
146			`PARAMETER C_BASEADDR = 0x84000000`
147			`PARAMETER C_HIGHADDR = 0x8400ffff`
148			`BUS_INTERFACE SPLB = plb_v46_0`
149			`PORT RX = fpga_0_RS232_Uart_1_RX_pin`
150			`PORT TX = fpga_0_RS232_Uart_1_TX_pin`
151			`PORT Interrupt = RS232_Uart_1_Interrupt`
152			`END`
153
154			`BEGIN xps_gpio`
155			`PARAMETER INSTANCE = LEDs_8Bit`
156			`PARAMETER C_FAMILY = virtex5`
157			`PARAMETER C_ALL_INPUTS = 0`
158			`PARAMETER C_GPIO_WIDTH = 8`
159			`PARAMETER C_INTERRUPT_PRESENT = 0`
160			`PARAMETER C_IS_DUAL = 0`
161			`PARAMETER HW_VER = 2.00.a`
162			`PARAMETER C_BASEADDR = 0x81440000`
163			`PARAMETER C_HIGHADDR = 0x8144ffff`
164			`BUS_INTERFACE SPLB = plb_v46_0`
165			`PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO_pin`
166			`END`
167
168			`BEGIN xps_gpio`
169			`PARAMETER INSTANCE = LEDs_Positions`
170			`PARAMETER C_FAMILY = virtex5`
171			`PARAMETER C_ALL_INPUTS = 0`
172			`PARAMETER C_GPIO_WIDTH = 5`
173			`PARAMETER C_INTERRUPT_PRESENT = 0`
174			`PARAMETER C_IS_DUAL = 0`
175			`PARAMETER HW_VER = 2.00.a`
176			`PARAMETER C_BASEADDR = 0x81420000`
177			`PARAMETER C_HIGHADDR = 0x8142ffff`
178			`BUS_INTERFACE SPLB = plb_v46_0`
179			`PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO_pin`
180			`END`
181
182			`BEGIN xps_gpio`
183			`PARAMETER INSTANCE = Push_Buttons_5Bit`
184			`PARAMETER C_FAMILY = virtex5`
185			`PARAMETER C_ALL_INPUTS = 1`
186			`PARAMETER C_GPIO_WIDTH = 5`
187			`PARAMETER C_INTERRUPT_PRESENT = 0`
188			`PARAMETER C_IS_DUAL = 0`
189			`PARAMETER HW_VER = 2.00.a`
190			`PARAMETER C_BASEADDR = 0x81400000`
191			`PARAMETER C_HIGHADDR = 0x8140ffff`
192			`BUS_INTERFACE SPLB = plb_v46_0`
193			`PORT GPIO_IO = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin`
194			`END`
195
196			`BEGIN xps_gpio`
197			`PARAMETER INSTANCE = DIP_Switches_8Bit`
198			`PARAMETER C_FAMILY = virtex5`
199			`PARAMETER C_ALL_INPUTS = 1`
200			`PARAMETER C_GPIO_WIDTH = 8`
201			`PARAMETER C_INTERRUPT_PRESENT = 0`
202			`PARAMETER C_IS_DUAL = 0`
203			`PARAMETER HW_VER = 2.00.a`
204			`PARAMETER C_BASEADDR = 0x81460000`
205			`PARAMETER C_HIGHADDR = 0x8146ffff`
206			`BUS_INTERFACE SPLB = plb_v46_0`
207			`PORT GPIO_IO = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin`
208			`END`
209
210			`BEGIN xps_iic`
211			`PARAMETER INSTANCE = IIC_EEPROM`
212			`PARAMETER C_IIC_FREQ = 100000`
213			`PARAMETER C_TEN_BIT_ADR = 0`
214			`PARAMETER C_FAMILY = virtex5`
215			`PARAMETER HW_VER = 2.01.a`
216			`PARAMETER C_BASEADDR = 0x81600000`
217			`PARAMETER C_HIGHADDR = 0x8160ffff`
218			`BUS_INTERFACE SPLB = plb_v46_0`
219			`PORT Sda = fpga_0_IIC_EEPROM_Sda_pin`
220			`PORT Scl = fpga_0_IIC_EEPROM_Scl_pin`
221			`END`
222
223			`BEGIN xps_mch_emc`
224			`PARAMETER INSTANCE = SRAM`
225			`PARAMETER C_FAMILY = virtex5`
226			`PARAMETER C_NUM_BANKS_MEM = 1`
227			`PARAMETER C_NUM_CHANNELS = 0`
228			`PARAMETER C_MEM0_WIDTH = 32`
229			`PARAMETER C_MAX_MEM_WIDTH = 32`
230			`PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0`
231			`PARAMETER C_SYNCH_MEM_0 = 1`
232			`PARAMETER C_TCEDV_PS_MEM_0 = 0`
233			`PARAMETER C_TAVDV_PS_MEM_0 = 0`
234			`PARAMETER C_THZCE_PS_MEM_0 = 0`
235			`PARAMETER C_THZOE_PS_MEM_0 = 0`
236			`PARAMETER C_TWC_PS_MEM_0 = 0`
237			`PARAMETER C_TWP_PS_MEM_0 = 0`
238			`PARAMETER C_TLZWE_PS_MEM_0 = 0`
239			`PARAMETER HW_VER = 3.00.a`
240			`PARAMETER C_MEM0_BASEADDR = 0xf8000000`
241			`PARAMETER C_MEM0_HIGHADDR = 0xf80fffff`
242			`BUS_INTERFACE SPLB = plb_v46_0`
243			`PORT RdClk = clk_125_0000MHzPLL0_ADJUST`
244			`PORT Mem_A = 0b0000000 & fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat & 0b0`
245			`PORT Mem_CEN = fpga_0_SRAM_Mem_CEN_pin`
246			`PORT Mem_OEN = fpga_0_SRAM_Mem_OEN_pin`
247			`PORT Mem_WEN = fpga_0_SRAM_Mem_WEN_pin`
248			`PORT Mem_BEN = fpga_0_SRAM_Mem_BEN_pin`
249			`PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN_pin`
250			`PORT Mem_DQ = fpga_0_SRAM_Mem_DQ_pin`
251			`END`
252
253			`BEGIN plbv46_pcie`
254			`PARAMETER INSTANCE = PCIe_Bridge`
255			`PARAMETER C_FAMILY = virtex5`
256			`PARAMETER C_IPIFBAR_NUM = 2`
257			`PARAMETER C_PCIBAR_NUM = 1`
258			`PARAMETER C_DEVICE_ID = 0x0505`
259			`PARAMETER C_VENDOR_ID = 0x10EE`
260			`PARAMETER C_CLASS_CODE = 0x058000`
261			`PARAMETER C_REV_ID = 0x00`
262			`PARAMETER C_SUBSYSTEM_ID = 0x0000`
263			`PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x0000`
264			`PARAMETER C_COMP_TIMEOUT = 1`
265			`PARAMETER C_IPIFBAR2PCIBAR_0 = 0x00000000`
266			`PARAMETER C_IPIFBAR2PCIBAR_1 = 0x00000000`
267			`PARAMETER C_PCIBAR2IPIFBAR_0 = 0xf8000000`
268			`PARAMETER C_PCIBAR2IPIFBAR_1 = 0x00000000`
269			`PARAMETER C_PCIBAR_LEN_0 = 20`
270			`PARAMETER C_PCIBAR_LEN_1 = 28`
271			`PARAMETER C_BOARD = ml507`
272			`PARAMETER HW_VER = 3.00.b`
273			`PARAMETER C_BASEADDR = 0x85c00000`
274			`PARAMETER C_HIGHADDR = 0x85c0ffff`
275			`PARAMETER C_IPIFBAR_0 = 0xc0000000`
276			`PARAMETER C_IPIFBAR_HIGHADDR_0 = 0xdfffffff`
277			`PARAMETER C_IPIFBAR_1 = 0xe0000000`
278			`PARAMETER C_IPIFBAR_HIGHADDR_1 = 0xefffffff`
279			`BUS_INTERFACE SPLB = plb_v46_0`
280			`BUS_INTERFACE MPLB = ppc440_0_SPLB0`
281			`PORT PERSTN = net_vcc`
282			`PORT REFCLK = PCIe_Diff_Clk`
283			`PORT RXN = fpga_0_PCIe_Bridge_RXN_pin`
284			`PORT RXP = fpga_0_PCIe_Bridge_RXP_pin`
285			`PORT TXN = fpga_0_PCIe_Bridge_TXN_pin`
286			`PORT TXP = fpga_0_PCIe_Bridge_TXP_pin`
287			`PORT MSI_request = net_gnd`
288			`END`
289
290			`BEGIN plb_v46`
291			`PARAMETER INSTANCE = ppc440_0_SPLB0`
292			`PARAMETER C_FAMILY = virtex5`
293			`PARAMETER HW_VER = 1.04.a`
294			`PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST`
295			`PORT SYS_Rst = sys_bus_reset`
296			`END`
297
298			`BEGIN xps_ethernetlite`
299			`PARAMETER INSTANCE = Ethernet_MAC`
300			`PARAMETER C_FAMILY = virtex5`
301			`PARAMETER HW_VER = 2.01.a`
302			`PARAMETER C_BASEADDR = 0x81000000`
303			`PARAMETER C_HIGHADDR = 0x8100ffff`
304			`BUS_INTERFACE SPLB = plb_v46_0`
305			`PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk_pin`
306			`PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk_pin`
307			`PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs_pin`
308			`PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv_pin`
309			`PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data_pin`
310			`PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col_pin`
311			`PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er_pin`
312			`PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n_pin`
313			`PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en_pin`
314			`PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data_pin`
315			`END`
316
317			`BEGIN ppc440mc_ddr2`
318			`PARAMETER INSTANCE = DDR2_SDRAM`
319			`PARAMETER C_DDR_BAWIDTH = 2`
320			`PARAMETER C_NUM_CLK_PAIRS = 2`
321			`PARAMETER C_DDR_DWIDTH = 64`
322			`PARAMETER C_DDR_CAWIDTH = 10`
323			`PARAMETER C_NUM_RANKS_MEM = 1`
324			`PARAMETER C_CS_BITS = 0`
325			`PARAMETER C_DDR_DM_WIDTH = 8`
326			`PARAMETER C_DQ_BITS = 8`
327			`PARAMETER C_DDR2_ODT_WIDTH = 2`
328			`PARAMETER C_DDR2_ADDT_LAT = 0`
329			`PARAMETER C_INCLUDE_ECC_SUPPORT = 0`
330			`PARAMETER C_DDR2_ODT_SETTING = 1`
331			`PARAMETER C_DQS_BITS = 3`
332			`PARAMETER C_DDR_DQS_WIDTH = 8`
333			`PARAMETER C_DDR_RAWIDTH = 13`
334			`PARAMETER C_DDR_BURST_LENGTH = 4`
335			`PARAMETER C_DDR_CAS_LAT = 4`
336			`PARAMETER C_REG_DIMM = 0`
337			`PARAMETER C_MIB_MC_CLOCK_RATIO = 1`
338			`PARAMETER C_DDR_TREFI = 3900`
339			`PARAMETER C_DDR_TRAS = 40000`
340			`PARAMETER C_DDR_TRCD = 15000`
341			`PARAMETER C_DDR_TRFC = 75000`
342			`PARAMETER C_DDR_TRP = 15000`
343			`PARAMETER C_DDR_TRTP = 7500`
344			`PARAMETER C_DDR_TWR = 15000`
345			`PARAMETER C_DDR_TWTR = 7500`
346			`PARAMETER C_MC_MIBCLK_PERIOD_PS = 8000`
347			`PARAMETER C_IDEL_HIGH_PERF = TRUE`
348			`PARAMETER C_NUM_IDELAYCTRL = 3`
349			`PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1`
350			`PARAMETER C_DQS_IO_COL = 0b000000000000000000`
351			`PARAMETER C_DQ_IO_MS = 0b000000000111010100111101000011110001111000101110110000111100000110111100`
352			`PARAMETER HW_VER = 2.00.b`
353			`PARAMETER C_MEM_BASEADDR = 0x00000000`
354			`PARAMETER C_MEM_HIGHADDR = 0x0fffffff`
355			`BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC`
356			`PORT mc_mibclk = clk_125_0000MHzPLL0_ADJUST`
357			`PORT mi_mcclk90 = clk_125_0000MHz90PLL0_ADJUST`
358			`PORT mi_mcreset = sys_bus_reset`
359			`PORT mi_mcclkdiv2 = clk_62_5000MHzPLL0_ADJUST`
360			`PORT mi_mcclk_200 = clk_200_0000MHz`
361			`PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ_pin`
362			`PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS_pin`
363			`PORT DDR2_DQS_N = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin`
364			`PORT DDR2_A = fpga_0_DDR2_SDRAM_DDR2_A_pin`
365			`PORT DDR2_BA = fpga_0_DDR2_SDRAM_DDR2_BA_pin`
366			`PORT DDR2_RAS_N = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin`
367			`PORT DDR2_CAS_N = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin`
368			`PORT DDR2_WE_N = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin`
369			`PORT DDR2_CS_N = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin`
370			`PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT_pin`
371			`PORT DDR2_CKE = fpga_0_DDR2_SDRAM_DDR2_CKE_pin`
372			`PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM_pin`
373			`PORT DDR2_CK = fpga_0_DDR2_SDRAM_DDR2_CK_pin`
374			`PORT DDR2_CK_N = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin`
375			`END`
376
377			`BEGIN xps_sysace`
378			`PARAMETER INSTANCE = SysACE_CompactFlash`
379			`PARAMETER C_MEM_WIDTH = 16`
380			`PARAMETER C_FAMILY = virtex5`
381			`PARAMETER HW_VER = 1.01.a`
382			`PARAMETER C_BASEADDR = 0x83600000`
383			`PARAMETER C_HIGHADDR = 0x8360ffff`
384			`BUS_INTERFACE SPLB = plb_v46_0`
385			`PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin`
386			`PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin`
387			`PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin`
388			`PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin`
389			`PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin`
390			`PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin`
391			`PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin`
392			`END`
393
394			`BEGIN fcb_v20`
395			`PARAMETER INSTANCE = ppc440_0_fcb_v20`
396			`PARAMETER HW_VER = 1.00.a`
397			`PORT FCB_CLK = clk_125_0000MHzPLL0_ADJUST`
398			`PORT SYS_RST = sys_bus_reset`
399			`END`
400
401			`BEGIN apu_fpu_virtex5`
402			`PARAMETER INSTANCE = ppc440_0_apu_fpu_virtex5`
403			`PARAMETER C_DOUBLE_PRECISION = 0`
404			`PARAMETER HW_VER = 1.01.a`
405			`BUS_INTERFACE SFCB2 = ppc440_0_fcb_v20`
406			`END`
407
408			`BEGIN clock_generator`
409			`PARAMETER INSTANCE = clock_generator_0`
410			`PARAMETER C_CLKIN_FREQ = 100000000`
411			`PARAMETER C_CLKFBIN_FREQ = 125000000`
412			`PARAMETER C_CLKOUT0_FREQ = 125000000`
413			`PARAMETER C_CLKOUT0_PHASE = 90`
414			`PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST`
415			`PARAMETER C_CLKOUT0_BUF = TRUE`
416			`PARAMETER C_CLKOUT1_FREQ = 125000000`
417			`PARAMETER C_CLKOUT1_PHASE = 0`
418			`PARAMETER C_CLKOUT1_GROUP = PLL0`
419			`PARAMETER C_CLKOUT1_BUF = TRUE`
420			`PARAMETER C_CLKOUT2_FREQ = 125000000`
421			`PARAMETER C_CLKOUT2_PHASE = 0`
422			`PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST`
423			`PARAMETER C_CLKOUT2_BUF = TRUE`
424			`PARAMETER C_CLKOUT3_FREQ = 200000000`
425			`PARAMETER C_CLKOUT3_PHASE = 0`
426			`PARAMETER C_CLKOUT3_GROUP = NONE`
427			`PARAMETER C_CLKOUT3_BUF = TRUE`
428			`PARAMETER C_CLKOUT4_FREQ = 62500000`
429			`PARAMETER C_CLKOUT4_PHASE = 0`
430			`PARAMETER C_CLKOUT4_GROUP = PLL0_ADJUST`
431			`PARAMETER C_CLKOUT4_BUF = TRUE`
432			`PARAMETER C_CLKFBOUT_FREQ = 125000000`
433			`PARAMETER C_CLKFBOUT_BUF = TRUE`
434			`PARAMETER HW_VER = 3.01.a`
435			`PORT CLKIN = dcm_clk_s`
436			`PORT CLKFBIN = SRAM_CLK_FB_s`
437			`PORT CLKOUT0 = clk_125_0000MHz90PLL0_ADJUST`
438			`PORT CLKOUT1 = clk_125_0000MHzPLL0`
439			`PORT CLKOUT2 = clk_125_0000MHzPLL0_ADJUST`
440			`PORT CLKOUT3 = clk_200_0000MHz`
441			`PORT CLKOUT4 = clk_62_5000MHzPLL0_ADJUST`
442			`PORT CLKFBOUT = SRAM_CLK_OUT_s`
443			`PORT RST = net_gnd`
444			`PORT LOCKED = Dcm_all_locked`
445			`END`
446
447			`BEGIN jtagppc_cntlr`
448			`PARAMETER INSTANCE = jtagppc_cntlr_inst`
449			`PARAMETER HW_VER = 2.01.c`
450			`BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus`
451			`END`
452
453			`BEGIN proc_sys_reset`
454			`PARAMETER INSTANCE = proc_sys_reset_0`
455			`PARAMETER C_EXT_RESET_HIGH = 0`
456			`PARAMETER HW_VER = 2.00.a`
457			`BUS_INTERFACE RESETPPC0 = ppc_reset_bus`
458			`PORT Slowest_sync_clk = clk_125_0000MHzPLL0_ADJUST`
459			`PORT Ext_Reset_In = sys_rst_s`
460			`PORT Dcm_locked = Dcm_all_locked`
461			`PORT Bus_Struct_Reset = sys_bus_reset`
462			`PORT Peripheral_Reset = sys_periph_reset`
463			`END`
464
465			`BEGIN xps_intc`
466			`PARAMETER INSTANCE = xps_intc_0`
467			`PARAMETER HW_VER = 2.00.a`
468			`PARAMETER C_BASEADDR = 0x81800000`
469			`PARAMETER C_HIGHADDR = 0x8180ffff`
470			`BUS_INTERFACE SPLB = plb_v46_0`
471			`PORT Intr = fpga_0_Ethernet_MAC_MDINT_pin&RS232_Uart_1_Interrupt`
472			`PORT Irq = ppc440_0_EICC440EXTIRQ`
473			`END`
474