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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC440_Xilinx_Virtex5_GCC/] [RTOSDemo/] [RTOSDemo_linker_script.ld] - Blame information for rev 792

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Line No. Rev Author Line
1 586 jeremybenn 
/*******************************************************************/
2 
/*                                                                 */
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/* This file is automatically generated by linker script generator.*/
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/*                                                                 */
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/* Version: Xilinx EDK 11.1 EDK_L.29.1                                */
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/*                                                                 */
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/* Copyright (c) 2004 Xilinx, Inc.  All rights reserved.           */
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/*                                                                 */
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/* Description : PowerPC440 Linker Script                          */
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/*                                                                 */
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/*******************************************************************/
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_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;
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_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;
15 
 
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/* Define Memories in the system */
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MEMORY
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{
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   DDR2_SDRAM_C_MEM_BASEADDR : ORIGIN = 0x00000000, LENGTH = 0x10000000
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   SRAM_C_MEM0_BASEADDR : ORIGIN = 0xF8000000, LENGTH = 0x00100000
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   xps_bram_if_cntlr_1 : ORIGIN = 0xFFFFE000, LENGTH = 0x00001F00
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}
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25 
/* Specify the default entry point to the program */
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ENTRY(_boot)
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STARTUP(boot.o)
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/* Define the sections, and where they are mapped in memory */
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SECTIONS
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{
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.vectors : {
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   __vectors_start = .;
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   *(.vectors)
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   __vectors_end = .;
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} > SRAM_C_MEM0_BASEADDR
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.text : {
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   *(.text)
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   *(.text.*)
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   *(.gnu.linkonce.t.*)
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} > SRAM_C_MEM0_BASEADDR
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.init : {
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   KEEP (*(.init))
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} > SRAM_C_MEM0_BASEADDR
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.fini : {
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   KEEP (*(.fini))
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} > SRAM_C_MEM0_BASEADDR
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.rodata : {
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   __rodata_start = .;
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   *(.rodata)
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   *(.rodata.*)
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   *(.gnu.linkonce.r.*)
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   __rodata_end = .;
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} > SRAM_C_MEM0_BASEADDR
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.rodata1 : {
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   __rodata1_start = .;
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   *(.rodata1)
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   *(.rodata1.*)
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   __rodata1_end = .;
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} > SRAM_C_MEM0_BASEADDR
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.sdata2 : {
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   __sdata2_start = .;
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   *(.sdata2)
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   *(.sdata2.*)
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   *(.gnu.linkonce.s2.*)
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   __sdata2_end = .;
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} > SRAM_C_MEM0_BASEADDR
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.sbss2 : {
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   __sbss2_start = .;
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   *(.sbss2)
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   *(.sbss2.*)
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   *(.gnu.linkonce.sb2.*)
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   __sbss2_end = .;
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} > SRAM_C_MEM0_BASEADDR
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.data : {
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   __data_start = .;
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   *(.data)
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   *(.data.*)
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   *(.gnu.linkonce.d.*)
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   __data_end = .;
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} > SRAM_C_MEM0_BASEADDR
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.data1 : {
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   __data1_start = .;
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   *(.data1)
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   *(.data1.*)
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   __data1_end = .;
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} > SRAM_C_MEM0_BASEADDR
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.got : {
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   *(.got)
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} > SRAM_C_MEM0_BASEADDR
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.got1 : {
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   *(.got1)
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} > SRAM_C_MEM0_BASEADDR
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.got2 : {
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   *(.got2)
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} > SRAM_C_MEM0_BASEADDR
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.ctors : {
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   __CTOR_LIST__ = .;
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   ___CTORS_LIST___ = .;
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   KEEP (*crtbegin.o(.ctors))
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   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
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   KEEP (*(SORT(.ctors.*)))
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   KEEP (*(.ctors))
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   __CTOR_END__ = .;
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   ___CTORS_END___ = .;
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} > SRAM_C_MEM0_BASEADDR
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.dtors : {
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   __DTOR_LIST__ = .;
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   ___DTORS_LIST___ = .;
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   KEEP (*crtbegin.o(.dtors))
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   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
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   KEEP (*(SORT(.dtors.*)))
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   KEEP (*(.dtors))
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   __DTOR_END__ = .;
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   ___DTORS_END___ = .;
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} > SRAM_C_MEM0_BASEADDR
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.fixup : {
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   __fixup_start = .;
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   *(.fixup)
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   __fixup_end = .;
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} > SRAM_C_MEM0_BASEADDR
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.eh_frame : {
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   *(.eh_frame)
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} > SRAM_C_MEM0_BASEADDR
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.jcr : {
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   *(.jcr)
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} > SRAM_C_MEM0_BASEADDR
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.gcc_except_table : {
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   *(.gcc_except_table)
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} > SRAM_C_MEM0_BASEADDR
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.sdata : {
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   __sdata_start = .;
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   *(.sdata)
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   *(.sdata.*)
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   *(.gnu.linkonce.s.*)
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   __sdata_end = .;
158 
} > SRAM_C_MEM0_BASEADDR
159 
 
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.sbss : {
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   __sbss_start = .;
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   *(.sbss)
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   *(.sbss.*)
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   *(.gnu.linkonce.sb.*)
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   *(.scommon)
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   __sbss_end = .;
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} > SRAM_C_MEM0_BASEADDR
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.tdata : {
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   __tdata_start = .;
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   *(.tdata)
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   *(.tdata.*)
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   *(.gnu.linkonce.td.*)
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   __tdata_end = .;
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} > SRAM_C_MEM0_BASEADDR
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.tbss : {
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   __tbss_start = .;
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   *(.tbss)
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   *(.tbss.*)
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   *(.gnu.linkonce.tb.*)
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   __tbss_end = .;
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} > SRAM_C_MEM0_BASEADDR
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.bss : {
186 
   __bss_start = .;
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   *(.bss)
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   *(.bss.*)
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   *(.gnu.linkonce.b.*)
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   *(COMMON)
191 
   . = ALIGN(4);
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   __bss_end = .;
193 
} > SRAM_C_MEM0_BASEADDR
194 
 
195 
.boot0 0xFFFFFF00 : {
196 
   __boot0_start = .;
197 
   *(.boot0)
198 
   __boot0_end = .;
199 
}
200 
 
201 
.boot 0xFFFFFFFC : {
202 
   __boot_start = .;
203 
   *(.boot)
204 
   __boot_end = .;
205 
}
206 
 
207 
/* Generate Stack and Heap Sections */
208 
 
209 
.stack : {
210 
   _stack_end = .;
211 
   . += _STACK_SIZE;
212 
   . = ALIGN(16);
213 
   __stack = .;
214 
} > SRAM_C_MEM0_BASEADDR
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.heap : {
217 
   . = ALIGN(16);
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   _heap_start = .;
219 
   . += _HEAP_SIZE;
220 
   . = ALIGN(16);
221 
   _heap_end = .;
222 
   _end = .;
223 
} > SRAM_C_MEM0_BASEADDR
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225 
}
226 
 

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