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jeremybenn |
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The command line option -timing is automatically supported for this architecture. Therefore, it is not necessary to specify this option.
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| 10 |
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| 11 |
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Logical network N194 has no load.
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| 13 |
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| 14 |
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The above warning message is repeated 1200 more times for the following (max. 5 shown):
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N195,
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| 16 |
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N196,
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| 17 |
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N197,
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N198,
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| 19 |
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N199
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To see the details of these warning messages, please use the -detail switch.
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| 21 |
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| 22 |
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| 23 |
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No environment variables are currently set.
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| 24 |
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| 25 |
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| 26 |
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Net Timing constraints on signal fpga_0_SysACE_CompactFlash_SysACE_CLK_pin are pushed forward through input buffer.
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| 28 |
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| 29 |
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PLL_ADV clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst CLKIN2 pin was disconnected because a constant 1 is driving the CLKINSEL pin.
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| 30 |
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| 31 |
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| 32 |
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Signal fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has been removed.
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| 33 |
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| 34 |
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Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top level port fpga_0_Ethernet_MAC_PHY_col_pin has been removed.
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| 37 |
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| 38 |
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All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been optimized out of the design.
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| 39 |
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| 40 |
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| 41 |
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Trimming timing constraints from pin xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
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| 42 |
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of frag REGCLKAU connected to power/ground net xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig
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| 43 |
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| 44 |
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| 45 |
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Trimming timing constraints from pin xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
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| 46 |
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of frag REGCLKAL connected to power/ground net xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig
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| 47 |
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| 48 |
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| 49 |
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Trimming timing constraints from pin xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
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| 50 |
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of frag REGCLKAU connected to power/ground net xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig
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| 51 |
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| 52 |
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| 53 |
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Trimming timing constraints from pin xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
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| 54 |
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of frag REGCLKAL connected to power/ground net xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig
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| 55 |
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| 56 |
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| 57 |
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Trimming timing constraints from pin PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst
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| 58 |
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of frag REGCLKAU connected to power/ground net PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig
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| 59 |
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| 60 |
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| 61 |
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Trimming timing constraints from pin PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst
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| 62 |
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of frag REGCLKAL connected to power/ground net PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig
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| 63 |
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| 64 |
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| 65 |
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Trimming timing constraints from pin PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst
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| 66 |
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of frag REGCLKAU connected to power/ground net PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig
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| 67 |
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| 68 |
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| 69 |
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Trimming timing constraints from pin PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst
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| 70 |
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of frag REGCLKAL connected to power/ground net PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig
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| 71 |
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| 72 |
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| 73 |
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Trimming timing constraints from pin PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank
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| 74 |
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of frag RDRCLKU connected to power/ground net PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig
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| 75 |
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| 76 |
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| 77 |
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Trimming timing constraints from pin PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank
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| 78 |
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of frag RDRCLKL connected to power/ground net PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig
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| 79 |
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| 80 |
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| 81 |
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Trimming timing constraints from pin PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
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| 82 |
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of frag RDRCLKU connected to power/ground net PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
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| 83 |
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| 84 |
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| 85 |
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Trimming timing constraints from pin PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
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| 86 |
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of frag RDRCLKL connected to power/ground net PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
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| 87 |
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| 88 |
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| 89 |
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Trimming timing constraints from pin PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP
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| 90 |
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of frag RDRCLKU connected to power/ground net PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
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| 91 |
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| 92 |
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| 93 |
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Trimming timing constraints from pin PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP
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| 94 |
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of frag RDRCLKL connected to power/ground net PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
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| 95 |
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| 96 |
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| 97 |
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Trimming timing constraints from pin PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
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| 98 |
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of frag RDRCLKU connected to power/ground net PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
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| 99 |
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| 100 |
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| 101 |
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Trimming timing constraints from pin PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
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| 102 |
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of frag RDRCLKL connected to power/ground net PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COMP_TX_RAM_70.dpram/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
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| 103 |
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| 104 |
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| 105 |
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Trimming timing constraints from pin PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
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| 106 |
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of frag RDRCLKU connected to power/ground net PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
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| 107 |
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| 108 |
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| 109 |
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Trimming timing constraints from pin PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
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| 110 |
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of frag RDRCLKL connected to power/ground net PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
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| 111 |
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| 112 |
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| 113 |
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Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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| 114 |
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| 115 |
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| 116 |
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Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
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| 117 |
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| 118 |
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| 119 |
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Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4 ignored during timing analysis.
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| 120 |
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| 121 |
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Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.
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| 122 |
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| 123 |
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The Interim Design Summary has been generated in the MAP Report (.mrp).
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| 124 |
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| 125 |
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| 126 |
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An IO Bus with more than one IO standard is found.
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| 127 |
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Components associated with this bus are as follows:
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| 128 |
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD = LVCMOS25
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD = LVCMOS25
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| 130 |
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD = LVCMOS25
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| 131 |
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD = LVCMOS18
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| 132 |
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25
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| 133 |
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS18
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| 134 |
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS18
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| 135 |
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Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS18
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| 136 |
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| 137 |
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| 138 |
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| 139 |
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| 140 |
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An IO Bus with more than one IO standard is found.
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| 141 |
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Components associated with this bus are as follows:
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| 142 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVDCI_33
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| 143 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVDCI_33
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| 144 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVDCI_33
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| 145 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVDCI_33
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| 146 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVDCI_33
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| 147 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVDCI_33
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| 148 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVDCI_33
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| 149 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVDCI_33
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| 150 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVDCI_33
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| 151 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVDCI_33
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| 152 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVDCI_33
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| 153 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVDCI_33
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| 154 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVDCI_33
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| 155 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVDCI_33
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| 156 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVDCI_33
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| 157 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVDCI_33
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| 158 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33
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| 159 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33
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| 160 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33
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| 161 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33
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| 162 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33
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| 163 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33
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| 164 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33
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| 165 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33
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| 166 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33
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| 167 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33
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| 168 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33
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| 169 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33
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| 170 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33
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| 171 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33
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| 172 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33
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| 173 |
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Comp: fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33
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| 174 |
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| 175 |
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| 176 |
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| 177 |
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| 178 |
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Map created a placed design.
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| 179 |
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| 180 |
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| 181 |
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One or more GTXs are being used in this design. Evaluate the SelectIO-To-GTX Crosstalk section of the Virtex-5 RocketIO GTX Transceiver User Guide to ensure that the design SelectIO usage meets the guidelines to minimize the impact on GTX performance.
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| 182 |
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| 183 |
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| 184 |
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Gated clock. Clock net PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
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| 185 |
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| 186 |
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| 187 |
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Gated clock. Clock net Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
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| 188 |
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| 189 |
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| 190 |
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The signal <PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0>> is incomplete. The signal does not drive any load pins in the design.
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| 191 |
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| 192 |
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| 193 |
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The signal <PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0>> is incomplete. The signal does not drive any load pins in the design.
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| 194 |
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| 195 |
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| 196 |
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The signal <xps_bram_if_cntlr_1_port_BRAM_Addr<30>> is incomplete. The signal does not drive any load pins in the design.
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| 197 |
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| 198 |
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| 199 |
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The signal <xps_bram_if_cntlr_1_port_BRAM_Addr<31>> is incomplete. The signal does not drive any load pins in the design.
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| 200 |
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| 201 |
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| 202 |
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The signal <PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull> is incomplete. The signal does not drive any load pins in the design.
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| 203 |
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| 204 |
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| 205 |
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Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not used.
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| 206 |
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| 207 |
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| 208 |
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Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
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| 209 |
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| 210 |
|
|
|
| 211 |
|
|
Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not used.
|
| 212 |
|
|
|
| 213 |
|
|
|
| 214 |
|
|
Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
| 215 |
|
|
|
| 216 |
|
|
|
| 217 |
|
|
Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not used.
|
| 218 |
|
|
|
| 219 |
|
|
|
| 220 |
|
|
Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
| 221 |
|
|
|
| 222 |
|
|
|
| 223 |
|
|
Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not used.
|
| 224 |
|
|
|
| 225 |
|
|
|
| 226 |
|
|
Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
| 227 |
|
|
|
| 228 |
|
|
|
| 229 |
|
|
Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not used.
|
| 230 |
|
|
|
| 231 |
|
|
|
| 232 |
|
|
Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
| 233 |
|
|
|
| 234 |
|
|
|
| 235 |
|
|
Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not used.
|
| 236 |
|
|
|
| 237 |
|
|
|
| 238 |
|
|
Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
| 239 |
|
|
|
| 240 |
|
|
|
| 241 |
|
|
Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not used.
|
| 242 |
|
|
|
| 243 |
|
|
|
| 244 |
|
|
Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
| 245 |
|
|
|
| 246 |
|
|
|
| 247 |
|
|
Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The Q1 output pin of IFF is not used.
|
| 248 |
|
|
|
| 249 |
|
|
|
| 250 |
|
|
Dangling pins on block:<DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce>:<ILOGIC_IFF>. The SR pin is used for the IFF Flip-flop but the SRVAL_Q1 set/reset value is not configured.
|
| 251 |
|
|
|
| 252 |
|
|
|
| 253 |
|
|
|
| 254 |
|
|
|
