Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65973)] overrides constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)].
9
10
11
Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4; ignored during timing analysis.
12
13
Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.
14
15
The signal PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0> has no load. PAR will not attempt to route this signal.
16
17
18
The signal PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0> has no load. PAR will not attempt to route this signal.
19
20
21
The signal xps_bram_if_cntlr_1_port_BRAM_Addr<30> has no load. PAR will not attempt to route this signal.
22
23
24
The signal xps_bram_if_cntlr_1_port_BRAM_Addr<31> has no load. PAR will not attempt to route this signal.
25
26
27
The signal PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull has no load. PAR will not attempt to route this signal.
28
29
30
One or more directed routing (DIRT) constraints generated for a specific device have been found. Note that DIRT strings are guaranteed to work only on the same device they were created for. If the DIRT constraints fail, verify that the same connectivity is available in the target device for this implementation.
31
32
33
N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.
34
35
N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.
36
37
There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
38
39
40
41
There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
42
43
44
45
Number of "Exact" mode Directed Routing Constraints: 128
46
47
48
All "EXACT" mode Directed Routing constrained nets successfully routed. The number of constraints found: 128, number successful: 128
