Constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65973)] overrides constraint <NET "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)].
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Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "TNM_CLK0" TS_MC_CLK * 4; ignored during timing analysis.
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Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.
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To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.
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The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.
