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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC440_Xilinx_Virtex5_GCC/] [data/] [system.ucf] - Blame information for rev 606

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Line No. Rev Author Line
1 586 jeremybenn
Net fpga_0_RS232_Uart_1_RX_pin LOC = AG15  |  IOSTANDARD=LVCMOS33;
2
Net fpga_0_RS232_Uart_1_TX_pin LOC = AG20  |  IOSTANDARD=LVCMOS33;
3
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> LOC = AE24  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
4
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> LOC = AD24  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
5
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> LOC = AD25  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
6
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> LOC = G16  |  IOSTANDARD=LVCMOS25  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
7
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> LOC = AD26  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
8
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> LOC = G15  |  IOSTANDARD=LVCMOS25  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
9
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> LOC = L18  |  IOSTANDARD=LVCMOS25  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
10
Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> LOC = H18  |  IOSTANDARD=LVCMOS25  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
11
Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=E8  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
12
Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=AF23  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
13
Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=AG12  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
14
Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=AG23  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
15
Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=AF13  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
16
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<0> LOC = AJ6  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
17
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<1> LOC = AJ7  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
18
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<2> LOC = V8  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
19
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<3> LOC = AK7  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
20
Net fpga_0_Push_Buttons_5Bit_GPIO_IO_pin<4> LOC = U8  |  IOSTANDARD=LVCMOS33  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
21
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<0> LOC=U25  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
22
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<1> LOC=AG27  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
23
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<2> LOC=AF25  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
24
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<3> LOC=AF26  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
25
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<4> LOC=AE27  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
26
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<5> LOC=AE26  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
27
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<6> LOC=AC25  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
28
Net fpga_0_DIP_Switches_8Bit_GPIO_IO_pin<7> LOC=AC24  |  IOSTANDARD=LVCMOS18  |  PULLDOWN  |  SLEW=SLOW  |  DRIVE=2;
29
Net fpga_0_IIC_EEPROM_Sda_pin LOC=F8  |  SLEW = SLOW  |  DRIVE = 6  |  IOSTANDARD=LVCMOS33;
30
Net fpga_0_IIC_EEPROM_Scl_pin LOC=F9  |  SLEW = SLOW  |  DRIVE = 6  |  IOSTANDARD=LVCMOS33;
31
Net fpga_0_SRAM_Mem_A_pin<30> LOC=K12  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
32
Net fpga_0_SRAM_Mem_A_pin<29> LOC=K13  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
33
Net fpga_0_SRAM_Mem_A_pin<28> LOC=H23  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
34
Net fpga_0_SRAM_Mem_A_pin<27> LOC=G23  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
35
Net fpga_0_SRAM_Mem_A_pin<26> LOC=H12  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
36
Net fpga_0_SRAM_Mem_A_pin<25> LOC=J12  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
37
Net fpga_0_SRAM_Mem_A_pin<24> LOC=K22  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
38
Net fpga_0_SRAM_Mem_A_pin<23> LOC=K23  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
39
Net fpga_0_SRAM_Mem_A_pin<22> LOC=K14  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
40
Net fpga_0_SRAM_Mem_A_pin<21> LOC=L14  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
41
Net fpga_0_SRAM_Mem_A_pin<20> LOC=H22  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
42
Net fpga_0_SRAM_Mem_A_pin<19> LOC=G22  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
43
Net fpga_0_SRAM_Mem_A_pin<18> LOC=J15  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
44
Net fpga_0_SRAM_Mem_A_pin<17> LOC=K16  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
45
Net fpga_0_SRAM_Mem_A_pin<16> LOC=K21  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
46
Net fpga_0_SRAM_Mem_A_pin<15> LOC=J22  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
47
Net fpga_0_SRAM_Mem_A_pin<14> LOC=L16  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
48
Net fpga_0_SRAM_Mem_A_pin<13> LOC=L15  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
49
Net fpga_0_SRAM_Mem_A_pin<12> LOC=L20  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
50
Net fpga_0_SRAM_Mem_A_pin<11> LOC=L21  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
51
Net fpga_0_SRAM_Mem_A_pin<10> LOC=AE23  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
52
Net fpga_0_SRAM_Mem_A_pin<9> LOC=AE22  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
53
Net fpga_0_SRAM_Mem_A_pin<8> LOC=AE12  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
54
Net fpga_0_SRAM_Mem_A_pin<7> LOC=AE13  |  SLEW = FAST  |  DRIVE = 8  |  IOSTANDARD=LVCMOS33;
55
Net fpga_0_SRAM_Mem_CEN_pin LOC=J10  |  IOSTANDARD=LVDCI_33;
56
Net fpga_0_SRAM_Mem_OEN_pin LOC=B12  |  IOSTANDARD=LVDCI_33;
57
Net fpga_0_SRAM_Mem_WEN_pin LOC=AF20  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
58
Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=J11  |  IOSTANDARD=LVDCI_33;
59
Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=K11  |  IOSTANDARD=LVDCI_33;
60
Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=D10  |  IOSTANDARD=LVDCI_33;
61
Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=D11  |  IOSTANDARD=LVDCI_33;
62
Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=H8  |  IOSTANDARD=LVDCI_33;
63
Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=AG22  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
64
Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=AH22  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
65
Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=AH12  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
66
Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=AG13  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
67
Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=AH20  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
68
Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=AH19  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
69
Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=AH14  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
70
Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=AH13  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
71
Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=AF15  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
72
Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=AE16  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
73
Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=AE21  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
74
Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=AD20  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
75
Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=AF16  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
76
Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=AE17  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
77
Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=AE19  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
78
Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=AD19  |  PULLDOWN  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
79
Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=J9  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
80
Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=K8  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
81
Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=K9  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
82
Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=B13  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
83
Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=C13  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
84
Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=G11  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
85
Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=G12  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
86
Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=M8  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
87
Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=L8  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
88
Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=F11  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
89
Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=E11  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
90
Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=M10  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
91
Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=L9  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
92
Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=E12  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
93
Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=E13  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
94
Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=N10  |  PULLDOWN  |  IOSTANDARD=LVDCI_33;
95
Net fpga_0_SRAM_ZBT_CLK_OUT_pin LOC=G8  |  SLEW = FAST  |  DRIVE = 12  |  IOSTANDARD=LVCMOS33;
96
Net fpga_0_SRAM_ZBT_CLK_FB_pin LOC=AG21  |  IOSTANDARD=LVCMOS33;
97
Net fpga_0_PCIe_Bridge_RXN_pin LOC=AF1  |  IOSTANDARD = LVDS_25;
98
Net fpga_0_PCIe_Bridge_RXP_pin LOC=AE1  |  IOSTANDARD = LVDS_25;
99
Net fpga_0_PCIe_Bridge_TXN_pin LOC=AE2  |  IOSTANDARD = LVDS_25;
100
Net fpga_0_PCIe_Bridge_TXP_pin LOC=AD2  |  IOSTANDARD = LVDS_25;
101
Net "pcie_bridge/*SPLB_Clk" TNM_NET = "SPLB_Clk";
102
Net "pcie_bridge/*Bridge_Clk" TNM_NET = "Bridge_Clk";
103
 
104
## Timing constraints between clock-domain boundaries
105
#
106
TIMESPEC "TS_PLB_PCIe" = FROM "SPLB_Clk" TO "Bridge_Clk" 8 ns datapathonly;
107
TIMESPEC "TS_PCIe_PLB" = FROM "Bridge_Clk" TO "SPLB_Clk" 8 ns datapathonly;
108
 
109
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=K17  |  IOSTANDARD = LVCMOS25;
110
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=H17  |  IOSTANDARD = LVCMOS25;
111
Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=E34  |  IOSTANDARD = LVCMOS25;
112
Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=E32  |  IOSTANDARD = LVCMOS25;
113
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=A33  |  IOSTANDARD = LVCMOS25;
114
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=B33  |  IOSTANDARD = LVCMOS25;
115
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=C33  |  IOSTANDARD = LVCMOS25;
116
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=C32  |  IOSTANDARD = LVCMOS25;
117
Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=B32  |  IOSTANDARD = LVCMOS25;
118
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=E33  |  IOSTANDARD = LVCMOS25;
119
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=J14  |  IOSTANDARD = LVCMOS25  |  TIG;
120
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=AJ10  |  IOSTANDARD = LVDCI_33;
121
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=AH10  |  IOSTANDARD = LVDCI_33;
122
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=AH9  |  IOSTANDARD = LVDCI_33;
123
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=AE11  |  IOSTANDARD = LVDCI_33;
124
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=AF11  |  IOSTANDARD = LVDCI_33;
125
Net fpga_0_Ethernet_MAC_MDINT_pin LOC=H20  |  IOSTANDARD = LVCMOS25  |  TIG;
126
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<0> LOC=AF30  |  IOSTANDARD = SSTL18_II;
127
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<1> LOC=AK31  |  IOSTANDARD = SSTL18_II;
128
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<2> LOC=AF31  |  IOSTANDARD = SSTL18_II;
129
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<3> LOC=AD30  |  IOSTANDARD = SSTL18_II;
130
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<4> LOC=AJ30  |  IOSTANDARD = SSTL18_II;
131
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<5> LOC=AF29  |  IOSTANDARD = SSTL18_II;
132
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<6> LOC=AD29  |  IOSTANDARD = SSTL18_II;
133
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<7> LOC=AE29  |  IOSTANDARD = SSTL18_II;
134
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<8> LOC=AH27  |  IOSTANDARD = SSTL18_II;
135
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<9> LOC=AF28  |  IOSTANDARD = SSTL18_II;
136
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<10> LOC=AH28  |  IOSTANDARD = SSTL18_II;
137
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<11> LOC=AA28  |  IOSTANDARD = SSTL18_II;
138
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<12> LOC=AG25  |  IOSTANDARD = SSTL18_II;
139
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<13> LOC=AJ26  |  IOSTANDARD = SSTL18_II;
140
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<14> LOC=AG28  |  IOSTANDARD = SSTL18_II;
141
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<15> LOC=AB28  |  IOSTANDARD = SSTL18_II;
142
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<16> LOC=AC28  |  IOSTANDARD = SSTL18_II;
143
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<17> LOC=AB25  |  IOSTANDARD = SSTL18_II;
144
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<18> LOC=AC27  |  IOSTANDARD = SSTL18_II;
145
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<19> LOC=AA26  |  IOSTANDARD = SSTL18_II;
146
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<20> LOC=AB26  |  IOSTANDARD = SSTL18_II;
147
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<21> LOC=AA24  |  IOSTANDARD = SSTL18_II;
148
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<22> LOC=AB27  |  IOSTANDARD = SSTL18_II;
149
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<23> LOC=AA25  |  IOSTANDARD = SSTL18_II;
150
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<24> LOC=AC29  |  IOSTANDARD = SSTL18_II;
151
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<25> LOC=AB30  |  IOSTANDARD = SSTL18_II;
152
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<26> LOC=W31  |  IOSTANDARD = SSTL18_II;
153
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<27> LOC=V30  |  IOSTANDARD = SSTL18_II;
154
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<28> LOC=AC30  |  IOSTANDARD = SSTL18_II;
155
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<29> LOC=W29  |  IOSTANDARD = SSTL18_II;
156
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<30> LOC=V27  |  IOSTANDARD = SSTL18_II;
157
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<31> LOC=W27  |  IOSTANDARD = SSTL18_II;
158
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<32> LOC=V29  |  IOSTANDARD = SSTL18_II;
159
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<33> LOC=Y27  |  IOSTANDARD = SSTL18_II;
160
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<34> LOC=Y26  |  IOSTANDARD = SSTL18_II;
161
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<35> LOC=W24  |  IOSTANDARD = SSTL18_II;
162
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<36> LOC=V28  |  IOSTANDARD = SSTL18_II;
163
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<37> LOC=W25  |  IOSTANDARD = SSTL18_II;
164
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<38> LOC=W26  |  IOSTANDARD = SSTL18_II;
165
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<39> LOC=V24  |  IOSTANDARD = SSTL18_II;
166
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<40> LOC=R24  |  IOSTANDARD = SSTL18_II;
167
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<41> LOC=P25  |  IOSTANDARD = SSTL18_II;
168
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<42> LOC=N24  |  IOSTANDARD = SSTL18_II;
169
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<43> LOC=P26  |  IOSTANDARD = SSTL18_II;
170
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<44> LOC=T24  |  IOSTANDARD = SSTL18_II;
171
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<45> LOC=N25  |  IOSTANDARD = SSTL18_II;
172
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<46> LOC=P27  |  IOSTANDARD = SSTL18_II;
173
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<47> LOC=N28  |  IOSTANDARD = SSTL18_II;
174
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<48> LOC=M28  |  IOSTANDARD = SSTL18_II;
175
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<49> LOC=L28  |  IOSTANDARD = SSTL18_II;
176
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<50> LOC=F25  |  IOSTANDARD = SSTL18_II;
177
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<51> LOC=H25  |  IOSTANDARD = SSTL18_II;
178
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<52> LOC=K27  |  IOSTANDARD = SSTL18_II;
179
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<53> LOC=K28  |  IOSTANDARD = SSTL18_II;
180
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<54> LOC=H24  |  IOSTANDARD = SSTL18_II;
181
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<55> LOC=G26  |  IOSTANDARD = SSTL18_II;
182
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<56> LOC=G25  |  IOSTANDARD = SSTL18_II;
183
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<57> LOC=M26  |  IOSTANDARD = SSTL18_II;
184
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<58> LOC=J24  |  IOSTANDARD = SSTL18_II;
185
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<59> LOC=L26  |  IOSTANDARD = SSTL18_II;
186
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<60> LOC=J27  |  IOSTANDARD = SSTL18_II;
187
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<61> LOC=M25  |  IOSTANDARD = SSTL18_II;
188
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<62> LOC=L25  |  IOSTANDARD = SSTL18_II;
189
Net fpga_0_DDR2_SDRAM_DDR2_DQ_pin<63> LOC=L24  |  IOSTANDARD = SSTL18_II;
190
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<0> LOC=AA29  |  IOSTANDARD = DIFF_SSTL18_II;
191
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<1> LOC=AK28  |  IOSTANDARD = DIFF_SSTL18_II;
192
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<2> LOC=AK26  |  IOSTANDARD = DIFF_SSTL18_II;
193
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<3> LOC=AB31  |  IOSTANDARD = DIFF_SSTL18_II;
194
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<4> LOC=Y28  |  IOSTANDARD = DIFF_SSTL18_II;
195
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<5> LOC=E26  |  IOSTANDARD = DIFF_SSTL18_II;
196
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<6> LOC=H28  |  IOSTANDARD = DIFF_SSTL18_II;
197
Net fpga_0_DDR2_SDRAM_DDR2_DQS_pin<7> LOC=G27  |  IOSTANDARD = DIFF_SSTL18_II;
198
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<0> LOC=AA30  |  IOSTANDARD = DIFF_SSTL18_II;
199
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<1> LOC=AK27  |  IOSTANDARD = DIFF_SSTL18_II;
200
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<2> LOC=AJ27  |  IOSTANDARD = DIFF_SSTL18_II;
201
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<3> LOC=AA31  |  IOSTANDARD = DIFF_SSTL18_II;
202
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<4> LOC=Y29  |  IOSTANDARD = DIFF_SSTL18_II;
203
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<5> LOC=E27  |  IOSTANDARD = DIFF_SSTL18_II;
204
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<6> LOC=G28  |  IOSTANDARD = DIFF_SSTL18_II;
205
Net fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin<7> LOC=H27  |  IOSTANDARD = DIFF_SSTL18_II;
206
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<0> LOC=L30  |  IOSTANDARD = SSTL18_II;
207
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<1> LOC=M30  |  IOSTANDARD = SSTL18_II;
208
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<2> LOC=N29  |  IOSTANDARD = SSTL18_II;
209
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<3> LOC=P29  |  IOSTANDARD = SSTL18_II;
210
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<4> LOC=K31  |  IOSTANDARD = SSTL18_II;
211
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<5> LOC=L31  |  IOSTANDARD = SSTL18_II;
212
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<6> LOC=P31  |  IOSTANDARD = SSTL18_II;
213
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<7> LOC=P30  |  IOSTANDARD = SSTL18_II;
214
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<8> LOC=M31  |  IOSTANDARD = SSTL18_II;
215
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<9> LOC=R28  |  IOSTANDARD = SSTL18_II;
216
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<10> LOC=J31  |  IOSTANDARD = SSTL18_II;
217
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<11> LOC=R29  |  IOSTANDARD = SSTL18_II;
218
Net fpga_0_DDR2_SDRAM_DDR2_A_pin<12> LOC=T31  |  IOSTANDARD = SSTL18_II;
219
Net fpga_0_DDR2_SDRAM_DDR2_BA_pin<0> LOC=G31  |  IOSTANDARD = SSTL18_II;
220
Net fpga_0_DDR2_SDRAM_DDR2_BA_pin<1> LOC=J30  |  IOSTANDARD = SSTL18_II;
221
Net fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin LOC=H30  |  IOSTANDARD = SSTL18_II;
222
Net fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin LOC=E31  |  IOSTANDARD = SSTL18_II;
223
Net fpga_0_DDR2_SDRAM_DDR2_WE_N_pin LOC=K29  |  IOSTANDARD = SSTL18_II;
224
Net fpga_0_DDR2_SDRAM_DDR2_CS_N_pin LOC=L29  |  IOSTANDARD = SSTL18_II;
225
Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin<0> LOC=F31  |  IOSTANDARD = SSTL18_II;
226
Net fpga_0_DDR2_SDRAM_DDR2_ODT_pin<1> LOC=F30  |  IOSTANDARD = SSTL18_II;
227
Net fpga_0_DDR2_SDRAM_DDR2_CKE_pin LOC=T28  |  IOSTANDARD = SSTL18_II;
228
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<0> LOC=AJ31  |  IOSTANDARD = SSTL18_II;
229
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<1> LOC=AE28  |  IOSTANDARD = SSTL18_II;
230
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<2> LOC=Y24  |  IOSTANDARD = SSTL18_II;
231
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<3> LOC=Y31  |  IOSTANDARD = SSTL18_II;
232
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<4> LOC=V25  |  IOSTANDARD = SSTL18_II;
233
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<5> LOC=P24  |  IOSTANDARD = SSTL18_II;
234
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<6> LOC=F26  |  IOSTANDARD = SSTL18_II;
235
Net fpga_0_DDR2_SDRAM_DDR2_DM_pin<7> LOC=J25  |  IOSTANDARD = SSTL18_II;
236
Net fpga_0_DDR2_SDRAM_DDR2_CK_pin<0> LOC=AK29  |  IOSTANDARD = DIFF_SSTL18_II;
237
Net fpga_0_DDR2_SDRAM_DDR2_CK_pin<1> LOC=E28  |  IOSTANDARD = DIFF_SSTL18_II;
238
Net fpga_0_DDR2_SDRAM_DDR2_CK_N_pin<0> LOC=AJ29  |  IOSTANDARD = DIFF_SSTL18_II;
239
Net fpga_0_DDR2_SDRAM_DDR2_CK_N_pin<1> LOC=F28  |  IOSTANDARD = DIFF_SSTL18_II;
240
############################################################################
241
#
242
#  PPC440MC_DDR2 BRAM Location Constraints
243
#
244
############################################################################
245
 
246
##------------------------------------------------------------------------------
247
## MIG 2.0 Constraints
248
##------------------------------------------------------------------------------
249
###########################################################################
250
## Define multicycle paths - these paths may take longer because additional
251
## time allowed for logic to settle in calibration/initialization FSM
252
###########################################################################
253
 
254
NET "DDR2_SDRAM*/mc_mibclk" TNM = FFS "TNM_CLK0";
255
NET "DDR2_SDRAM*/mi_mcclk90" TNM = FFS "TNM_CLK90";
256
 
257
NET "DDR2_SDRAM*/mc_mibclk" TNM_NET =  "mc_clk";
258
TIMESPEC "TS_MC_CLK" = PERIOD "mc_clk" 5.000 ns;
259
 
260
 
261
## MUX Select for either rising/falling CLK0 for 2nd stage read capture
262
INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
263
TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO "TNM_CLK0"
264
"TS_clk_div_slow_0_clk_div_slow_0_DDR2_CLK_i" * 4;
265
 
266
## Calibration/Initialization complete status flag (for PHY logic only)
267
INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
268
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO
269
 "TNM_CLK0"
270
"TS_MC_CLK" * 4;
271
 
272
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO
273
  "TNM_CLK90" "TS_MC_CLK" * 4;
274
 
275
## Select (address) bits for SRL32 shift registers used in stage3/stage4
276
## calibration
277
INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
278
TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO "TNM_CLK0"
279
"TS_MC_CLK" * 4;
280
 
281
INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
282
TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO "TNM_CLK0"
283
"TS_MC_CLK" * 4;
284
 
285
INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly"
286
  TNM = "TNM_CAL_RDEN_DLY";
287
TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO "TNM_CLK0"
288
"TS_MC_CLK" * 4;
289
 
290
## MUX select for read data - optional delay on data to account for byte skews
291
INST "*/usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
292
TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO "TNM_CLK0"
293
"TS_MC_CLK" * 4;
294
 
295
###########################################################################
296
## LOC placment of DQS-squelch related IDDR and IDELAY elements
297
## Each circuit can be located at any of the following locations:
298
## 1. Ununsed "N"-side of DQS diff pair I/O
299
## 2. DM data mask (output only, input side is free for use)
300
## 3. Any output-only site
301
###########################################################################
302
 
303
INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y96";
304
INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y96";
305
INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y58";
306
INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y58";
307
INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y62";
308
INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y62";
309
INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y100";
310
INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y100";
311
INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y102";
312
INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y102";
313
INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y256";
314
INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y256";
315
INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y260";
316
INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y260";
317
INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y262";
318
INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y262";
319
 
320
###########################################################################
321
## DQS Squelch-related timing constraints
322
###########################################################################
323
 
324
###########################################################################
325
## Half-cycle path constraint from IDDR to CE pin for all DQ IDDRs
326
## for DQS Read Postamble Glitch Squelch circuit
327
###########################################################################
328
## Max delay from output of IDDR to CE input of DQ IDDRs = tRPST + some slack
329
## where slack account for rise-time of DQS on board. For now assume slack =
330
## 0.400ns (based on initial SPICE simulations, assumes use of ODT), so
331
## time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
332
INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
333
INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
334
TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 1.9 ns;
335
 
336
###########################################################################
337
## LOC and timing constraints for flop driving DQS CE enable signal
338
## from fabric logic. Even though the absolute delay on this path is
339
## calibrated out (when synchronizing this output to DQS), the delay
340
## should still be kept as low as possible to reduce post-calibration
341
## voltage/temp variations - these are roughly proportional to the
342
## absolute delay of the path
343
###########################################################################
344
 
345
INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff" LOC = SLICE_X0Y48;
346
INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff" LOC = SLICE_X0Y29;
347
INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff" LOC = SLICE_X0Y31;
348
INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff" LOC = SLICE_X0Y50;
349
INST "*/u_phy_calib/gen_gate[4].u_en_dqs_ff" LOC = SLICE_X0Y51;
350
INST "*/u_phy_calib/gen_gate[5].u_en_dqs_ff" LOC = SLICE_X0Y128;
351
INST "*/u_phy_calib/gen_gate[6].u_en_dqs_ff" LOC = SLICE_X0Y130;
352
INST "*/u_phy_calib/gen_gate[7].u_en_dqs_ff" LOC = SLICE_X0Y131;
353
 
354
###########################################################################
355
## Control for DQS gate - from fabric flop. Prevent runaway delay -
356
## two parts to this path: (1) from fabric flop to IDELAY, (2) from
357
## IDELAY to asynchronous reset of IDDR that drives the DQ CEs
358
## A single number is used for all speed grades - value based on 333MHz.
359
## This can be relaxed for lower frequencies.
360
###########################################################################
361
 
362
NET "*/u_phy_io/en_dqs*" MAXDELAY = 600 ps;
363
NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 850 ps;
364
 
365
###########################################################################
366
 
367
INST "*/gen_dq[0].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42;
368
INST "*/gen_dq[1].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y43;
369
INST "*/gen_dq[2].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y45;
370
INST "*/gen_dq[3].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46;
371
INST "*/gen_dq[4].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y41;
372
INST "*/gen_dq[5].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y42;
373
INST "*/gen_dq[6].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44;
374
INST "*/gen_dq[7].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y44;
375
INST "*/gen_dq[8].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28;
376
INST "*/gen_dq[9].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y32;
377
INST "*/gen_dq[10].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33;
378
INST "*/gen_dq[11].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34;
379
INST "*/gen_dq[12].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y26;
380
INST "*/gen_dq[13].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y28;
381
INST "*/gen_dq[14].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y33;
382
INST "*/gen_dq[15].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y34;
383
INST "*/gen_dq[16].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y35;
384
INST "*/gen_dq[17].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36;
385
INST "*/gen_dq[18].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38;
386
INST "*/gen_dq[19].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39;
387
INST "*/gen_dq[20].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y36;
388
INST "*/gen_dq[21].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y37;
389
INST "*/gen_dq[22].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y38;
390
INST "*/gen_dq[23].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y39;
391
INST "*/gen_dq[24].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y46;
392
INST "*/gen_dq[25].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49;
393
INST "*/gen_dq[26].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y53;
394
INST "*/gen_dq[27].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y55;
395
INST "*/gen_dq[28].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y49;
396
INST "*/gen_dq[29].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52;
397
INST "*/gen_dq[30].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54;
398
INST "*/gen_dq[31].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56;
399
INST "*/gen_dq[32].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y52;
400
INST "*/gen_dq[33].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y56;
401
INST "*/gen_dq[34].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58;
402
INST "*/gen_dq[35].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59;
403
INST "*/gen_dq[36].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y54;
404
INST "*/gen_dq[37].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y57;
405
INST "*/gen_dq[38].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y58;
406
INST "*/gen_dq[39].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y59;
407
INST "*/gen_dq[40].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120;
408
INST "*/gen_dq[41].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121;
409
INST "*/gen_dq[42].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y122;
410
INST "*/gen_dq[43].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123;
411
INST "*/gen_dq[44].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y120;
412
INST "*/gen_dq[45].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y121;
413
INST "*/gen_dq[46].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y123;
414
INST "*/gen_dq[47].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124;
415
INST "*/gen_dq[48].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y124;
416
INST "*/gen_dq[49].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126;
417
INST "*/gen_dq[50].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y132;
418
INST "*/gen_dq[51].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133;
419
INST "*/gen_dq[52].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y125;
420
INST "*/gen_dq[53].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y126;
421
INST "*/gen_dq[54].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y133;
422
INST "*/gen_dq[55].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134;
423
INST "*/gen_dq[56].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y134;
424
INST "*/gen_dq[57].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136;
425
INST "*/gen_dq[58].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y137;
426
INST "*/gen_dq[59].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138;
427
INST "*/gen_dq[60].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y135;
428
INST "*/gen_dq[61].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y136;
429
INST "*/gen_dq[62].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y138;
430
INST "*/gen_dq[63].u_iob_dq/gen_stg2_*.u_ff_stg2a_rise" RLOC_ORIGIN = X0Y139;
431
 
432
 
433
INST "DDR2_SDRAM/*/*u_rdf" LOC = RAMB36_X0Y19;
434
INST "DDR2_SDRAM/*/*u_rdf1" LOC = RAMB36_X0Y18;
435
INST "DDR2_SDRAM/*/*gen_wdf[0]*u_wdf" LOC = RAMB36_X0Y17;
436
INST "DDR2_SDRAM/*/*gen_wdf[1]*u_wdf" LOC = RAMB36_X0Y16;
437
 
438
 
439
###############################################################################
440
 
441
# Prevent unrelated logic from being packed into any slices used
442
 
443
# by read data capture RPM's - if unrelated logic gets packed into
444
 
445
# these slices, it could cause the DIRT strings that define the
446
 
447
# IDDR -> fabric flop routing to become unroutable during PAR stage
448
 
449
# (unrelated logic may require routing resources required by the
450
 
451
# DIRT strings - MAP does not currently take into account DIRT
452
 
453
# strings when placing logic
454
 
455
###############################################################################
456
 
457
AREA_GROUP "DDR_CAPTURE_FFS" GROUP = CLOSED;
458
 
459
 
460
 
461
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=G5  |  IOSTANDARD = LVCMOS33;
462
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=N7  |  IOSTANDARD = LVCMOS33;
463
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=N5  |  IOSTANDARD = LVCMOS33;
464
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=P5  |  IOSTANDARD = LVCMOS33;
465
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=R6  |  IOSTANDARD = LVCMOS33;
466
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=M6  |  IOSTANDARD = LVCMOS33;
467
Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=L6  |  IOSTANDARD = LVCMOS33;
468
Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AH17  |  IOSTANDARD = LVCMOS33  |  PERIOD = 30000 ps;
469
Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=M7  |  IOSTANDARD = LVCMOS33  |  TIG;
470
Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=M5  |  IOSTANDARD = LVCMOS33;
471
Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=N8  |  IOSTANDARD = LVCMOS33;
472
Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=R9  |  IOSTANDARD = LVCMOS33;
473
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=P9  |  IOSTANDARD = LVCMOS33;
474
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=T8  |  IOSTANDARD = LVCMOS33;
475
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=J7  |  IOSTANDARD = LVCMOS33;
476
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=H7  |  IOSTANDARD = LVCMOS33;
477
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=R7  |  IOSTANDARD = LVCMOS33;
478
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=U7  |  IOSTANDARD = LVCMOS33;
479
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=P7  |  IOSTANDARD = LVCMOS33;
480
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=P6  |  IOSTANDARD = LVCMOS33;
481
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=R8  |  IOSTANDARD = LVCMOS33;
482
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=L5  |  IOSTANDARD = LVCMOS33;
483
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=L4  |  IOSTANDARD = LVCMOS33;
484
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=K6  |  IOSTANDARD = LVCMOS33;
485
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=J5  |  IOSTANDARD = LVCMOS33;
486
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=T6  |  IOSTANDARD = LVCMOS33;
487
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=K7  |  IOSTANDARD = LVCMOS33;
488
Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=J6  |  IOSTANDARD = LVCMOS33;
489
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
490
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
491
Net fpga_0_clk_1_sys_clk_pin LOC = AH15  |  IOSTANDARD=LVCMOS33;
492
Net fpga_0_rst_1_sys_rst_pin TIG;
493
Net fpga_0_rst_1_sys_rst_pin LOC = E9  |  IOSTANDARD=LVCMOS33  |  PULLUP;
494
Net fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin LOC=AF4  |  IOSTANDARD = LVDS_25;
495
Net fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin LOC=AF3  |  IOSTANDARD = LVDS_25;

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