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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC440_Xilinx_Virtex5_GCC/] [revup/] [system_mhs.11.1] - Blame information for rev 595

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Line No. Rev Author Line
1 586 jeremybenn
 
2
# ##############################################################################
3
# Created by Base System Builder Wizard for Xilinx EDK 11.1 Build EDK_L.29.1
4
# Thu Jun 11 19:28:07 2009
5
# Target Board:  Xilinx Virtex 5 ML507 Evaluation Platform Rev A
6
# Family:    virtex5
7
# Device:    xc5vfx70t
8
# Package:   ff1136
9
# Speed Grade:  -1
10
# Processor number: 1
11
# Processor 1: ppc440_0
12
# Processor clock frequency: 125.0
13
# Bus clock frequency: 125.0
14
# Debug Interface: FPGA JTAG
15
# ##############################################################################
16
 PARAMETER VERSION = 2.1.0
17
 
18
 
19
 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
20
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
21
 PORT fpga_0_LEDs_8Bit_GPIO_IO_pin = fpga_0_LEDs_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]
22
 PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO_pin, DIR = IO, VEC = [0:4]
23
 PORT fpga_0_Push_Buttons_5Bit_GPIO_IO_pin = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin, DIR = IO, VEC = [0:4]
24
 PORT fpga_0_DIP_Switches_8Bit_GPIO_IO_pin = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin, DIR = IO, VEC = [0:7]
25
 PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda_pin, DIR = IO
26
 PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl_pin, DIR = IO
27
 PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat, DIR = O, VEC = [7:30]
28
 PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN_pin, DIR = O
29
 PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN_pin, DIR = O
30
 PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN_pin, DIR = O
31
 PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN_pin, DIR = O, VEC = [0:3]
32
 PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN_pin, DIR = O
33
 PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ_pin, DIR = IO, VEC = [0:31]
34
 PORT fpga_0_SRAM_ZBT_CLK_OUT_pin = SRAM_CLK_OUT_s, DIR = O
35
 PORT fpga_0_SRAM_ZBT_CLK_FB_pin = SRAM_CLK_FB_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000
36
 PORT fpga_0_PCIe_Bridge_RXN_pin = fpga_0_PCIe_Bridge_RXN_pin, DIR = I
37
 PORT fpga_0_PCIe_Bridge_RXP_pin = fpga_0_PCIe_Bridge_RXP_pin, DIR = I
38
 PORT fpga_0_PCIe_Bridge_TXN_pin = fpga_0_PCIe_Bridge_TXN_pin, DIR = O
39
 PORT fpga_0_PCIe_Bridge_TXP_pin = fpga_0_PCIe_Bridge_TXP_pin, DIR = O
40
 PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk_pin, DIR = I
41
 PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk_pin, DIR = I
42
 PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs_pin, DIR = I
43
 PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv_pin, DIR = I
44
 PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data_pin, DIR = I, VEC = [3:0]
45
 PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col_pin, DIR = I
46
 PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er_pin, DIR = I
47
 PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n_pin, DIR = O
48
 PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en_pin, DIR = O
49
 PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data_pin, DIR = O, VEC = [3:0]
50
 PORT fpga_0_Ethernet_MAC_MDINT_pin = fpga_0_Ethernet_MAC_MDINT_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM
51
 PORT fpga_0_DDR2_SDRAM_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DIR = IO, VEC = [63:0]
52
 PORT fpga_0_DDR2_SDRAM_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DIR = IO, VEC = [7:0]
53
 PORT fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin, DIR = IO, VEC = [7:0]
54
 PORT fpga_0_DDR2_SDRAM_DDR2_A_pin = fpga_0_DDR2_SDRAM_DDR2_A_pin, DIR = O, VEC = [12:0]
55
 PORT fpga_0_DDR2_SDRAM_DDR2_BA_pin = fpga_0_DDR2_SDRAM_DDR2_BA_pin, DIR = O, VEC = [1:0]
56
 PORT fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin, DIR = O
57
 PORT fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin, DIR = O
58
 PORT fpga_0_DDR2_SDRAM_DDR2_WE_N_pin = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin, DIR = O
59
 PORT fpga_0_DDR2_SDRAM_DDR2_CS_N_pin = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin, DIR = O
60
 PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DIR = O, VEC = [1:0]
61
 PORT fpga_0_DDR2_SDRAM_DDR2_CKE_pin = fpga_0_DDR2_SDRAM_DDR2_CKE_pin, DIR = O
62
 PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM_pin, DIR = O, VEC = [7:0]
63
 PORT fpga_0_DDR2_SDRAM_DDR2_CK_pin = fpga_0_DDR2_SDRAM_DDR2_CK_pin, DIR = O, VEC = [1:0]
64
 PORT fpga_0_DDR2_SDRAM_DDR2_CK_N_pin = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin, DIR = O, VEC = [1:0]
65
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin, DIR = O, VEC = [6:0]
66
 PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin, DIR = I
67
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin, DIR = I
68
 PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin, DIR = O
69
 PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin, DIR = O
70
 PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin, DIR = O
71
 PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin, DIR = IO, VEC = [15:0]
72
 PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
73
 PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
74
 PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK
75
 PORT fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin = PCIe_Diff_Clk, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK
76
 
77
 
78
BEGIN ppc440_virtex5
79
 PARAMETER INSTANCE = ppc440_0
80
 PARAMETER C_IDCR_BASEADDR = 0b0000000000
81
 PARAMETER C_IDCR_HIGHADDR = 0b0011111111
82
 PARAMETER C_PPC440MC_ROW_CONFLICT_MASK = 0x003FFE00
83
 PARAMETER C_PPC440MC_BANK_CONFLICT_MASK = 0x00C00000
84
 PARAMETER C_PPC440MC_CONTROL = 0xF810008F
85
 PARAMETER C_SPLB0_USE_MPLB_ADDR = 1
86
 PARAMETER C_SPLB0_NUM_MPLB_ADDR_RNG = 1
87
 PARAMETER C_SPLB1_NUM_MPLB_ADDR_RNG = 0
88
 PARAMETER HW_VER = 1.01.a
89
 PARAMETER C_SPLB0_RNG0_MPLB_BASEADDR = 0x80000000
90
 PARAMETER C_SPLB0_RNG0_MPLB_HIGHADDR = 0xffffffff
91
 PARAMETER C_SPLB0_RNG_MC_BASEADDR = 0x00000000
92
 PARAMETER C_SPLB0_RNG_MC_HIGHADDR = 0x0fffffff
93
 BUS_INTERFACE MPLB = plb_v46_0
94
 BUS_INTERFACE SPLB0 = ppc440_0_SPLB0
95
 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
96
 BUS_INTERFACE JTAGPPC = ppc440_0_jtagppc_bus
97
 BUS_INTERFACE RESETPPC = ppc_reset_bus
98
 PORT CPMC440CLK = clk_125_0000MHzPLL0
99
 PORT CPMINTERCONNECTCLK = clk_125_0000MHzPLL0
100
 PORT CPMINTERCONNECTCLKNTO1 = net_vcc
101
 PORT EICC440EXTIRQ = ppc440_0_EICC440EXTIRQ
102
 PORT CPMMCCLK = clk_125_0000MHzPLL0_ADJUST
103
 PORT CPMPPCMPLBCLK = clk_125_0000MHzPLL0_ADJUST
104
 PORT CPMPPCS0PLBCLK = clk_125_0000MHzPLL0_ADJUST
105
END
106
 
107
BEGIN plb_v46
108
 PARAMETER INSTANCE = plb_v46_0
109
 PARAMETER C_DCR_INTFCE = 0
110
 PARAMETER C_FAMILY = virtex5
111
 PARAMETER HW_VER = 1.04.a
112
 PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST
113
 PORT SYS_Rst = sys_bus_reset
114
END
115
 
116
BEGIN xps_bram_if_cntlr
117
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
118
 PARAMETER C_SPLB_NATIVE_DWIDTH = 64
119
 PARAMETER C_SPLB_SUPPORT_BURSTS = 1
120
 PARAMETER C_SPLB_P2P = 0
121
 PARAMETER C_FAMILY = virtex5
122
 PARAMETER HW_VER = 1.00.b
123
 PARAMETER C_BASEADDR = 0xffffe000
124
 PARAMETER C_HIGHADDR = 0xffffffff
125
 BUS_INTERFACE SPLB = plb_v46_0
126
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
127
END
128
 
129
BEGIN bram_block
130
 PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
131
 PARAMETER C_FAMILY = virtex5
132
 PARAMETER HW_VER = 1.00.a
133
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
134
END
135
 
136
BEGIN xps_uartlite
137
 PARAMETER INSTANCE = RS232_Uart_1
138
 PARAMETER C_FAMILY = virtex5
139
 PARAMETER C_BAUDRATE = 9600
140
 PARAMETER C_DATA_BITS = 8
141
 PARAMETER C_USE_PARITY = 0
142
 PARAMETER C_ODD_PARITY = 0
143
 PARAMETER HW_VER = 1.01.a
144
 PARAMETER C_BASEADDR = 0x84000000
145
 PARAMETER C_HIGHADDR = 0x8400ffff
146
 BUS_INTERFACE SPLB = plb_v46_0
147
 PORT RX = fpga_0_RS232_Uart_1_RX_pin
148
 PORT TX = fpga_0_RS232_Uart_1_TX_pin
149
 PORT Interrupt = RS232_Uart_1_Interrupt
150
END
151
 
152
BEGIN xps_gpio
153
 PARAMETER INSTANCE = LEDs_8Bit
154
 PARAMETER C_FAMILY = virtex5
155
 PARAMETER C_ALL_INPUTS = 0
156
 PARAMETER C_GPIO_WIDTH = 8
157
 PARAMETER C_INTERRUPT_PRESENT = 0
158
 PARAMETER C_IS_DUAL = 0
159
 PARAMETER HW_VER = 2.00.a
160
 PARAMETER C_BASEADDR = 0x81440000
161
 PARAMETER C_HIGHADDR = 0x8144ffff
162
 BUS_INTERFACE SPLB = plb_v46_0
163
 PORT GPIO_IO = fpga_0_LEDs_8Bit_GPIO_IO_pin
164
END
165
 
166
BEGIN xps_gpio
167
 PARAMETER INSTANCE = LEDs_Positions
168
 PARAMETER C_FAMILY = virtex5
169
 PARAMETER C_ALL_INPUTS = 0
170
 PARAMETER C_GPIO_WIDTH = 5
171
 PARAMETER C_INTERRUPT_PRESENT = 0
172
 PARAMETER C_IS_DUAL = 0
173
 PARAMETER HW_VER = 2.00.a
174
 PARAMETER C_BASEADDR = 0x81420000
175
 PARAMETER C_HIGHADDR = 0x8142ffff
176
 BUS_INTERFACE SPLB = plb_v46_0
177
 PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO_pin
178
END
179
 
180
BEGIN xps_gpio
181
 PARAMETER INSTANCE = Push_Buttons_5Bit
182
 PARAMETER C_FAMILY = virtex5
183
 PARAMETER C_ALL_INPUTS = 1
184
 PARAMETER C_GPIO_WIDTH = 5
185
 PARAMETER C_INTERRUPT_PRESENT = 0
186
 PARAMETER C_IS_DUAL = 0
187
 PARAMETER HW_VER = 2.00.a
188
 PARAMETER C_BASEADDR = 0x81400000
189
 PARAMETER C_HIGHADDR = 0x8140ffff
190
 BUS_INTERFACE SPLB = plb_v46_0
191
 PORT GPIO_IO = fpga_0_Push_Buttons_5Bit_GPIO_IO_pin
192
END
193
 
194
BEGIN xps_gpio
195
 PARAMETER INSTANCE = DIP_Switches_8Bit
196
 PARAMETER C_FAMILY = virtex5
197
 PARAMETER C_ALL_INPUTS = 1
198
 PARAMETER C_GPIO_WIDTH = 8
199
 PARAMETER C_INTERRUPT_PRESENT = 0
200
 PARAMETER C_IS_DUAL = 0
201
 PARAMETER HW_VER = 2.00.a
202
 PARAMETER C_BASEADDR = 0x81460000
203
 PARAMETER C_HIGHADDR = 0x8146ffff
204
 BUS_INTERFACE SPLB = plb_v46_0
205
 PORT GPIO_IO = fpga_0_DIP_Switches_8Bit_GPIO_IO_pin
206
END
207
 
208
BEGIN xps_iic
209
 PARAMETER INSTANCE = IIC_EEPROM
210
 PARAMETER C_IIC_FREQ = 100000
211
 PARAMETER C_TEN_BIT_ADR = 0
212
 PARAMETER C_FAMILY = virtex5
213
 PARAMETER HW_VER = 2.01.a
214
 PARAMETER C_BASEADDR = 0x81600000
215
 PARAMETER C_HIGHADDR = 0x8160ffff
216
 BUS_INTERFACE SPLB = plb_v46_0
217
 PORT Sda = fpga_0_IIC_EEPROM_Sda_pin
218
 PORT Scl = fpga_0_IIC_EEPROM_Scl_pin
219
END
220
 
221
BEGIN xps_mch_emc
222
 PARAMETER INSTANCE = SRAM
223
 PARAMETER C_FAMILY = virtex5
224
 PARAMETER C_NUM_BANKS_MEM = 1
225
 PARAMETER C_NUM_CHANNELS = 0
226
 PARAMETER C_MEM0_WIDTH = 32
227
 PARAMETER C_MAX_MEM_WIDTH = 32
228
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
229
 PARAMETER C_SYNCH_MEM_0 = 1
230
 PARAMETER C_TCEDV_PS_MEM_0 = 0
231
 PARAMETER C_TAVDV_PS_MEM_0 = 0
232
 PARAMETER C_THZCE_PS_MEM_0 = 0
233
 PARAMETER C_THZOE_PS_MEM_0 = 0
234
 PARAMETER C_TWC_PS_MEM_0 = 0
235
 PARAMETER C_TWP_PS_MEM_0 = 0
236
 PARAMETER C_TLZWE_PS_MEM_0 = 0
237
 PARAMETER HW_VER = 3.00.a
238
 PARAMETER C_MEM0_BASEADDR = 0xf8000000
239
 PARAMETER C_MEM0_HIGHADDR = 0xf80fffff
240
 BUS_INTERFACE SPLB = plb_v46_0
241
 PORT RdClk = clk_125_0000MHzPLL0_ADJUST
242
 PORT Mem_A = 0b0000000 & fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat & 0b0
243
 PORT Mem_CEN = fpga_0_SRAM_Mem_CEN_pin
244
 PORT Mem_OEN = fpga_0_SRAM_Mem_OEN_pin
245
 PORT Mem_WEN = fpga_0_SRAM_Mem_WEN_pin
246
 PORT Mem_BEN = fpga_0_SRAM_Mem_BEN_pin
247
 PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN_pin
248
 PORT Mem_DQ = fpga_0_SRAM_Mem_DQ_pin
249
END
250
 
251
BEGIN plbv46_pcie
252
 PARAMETER INSTANCE = PCIe_Bridge
253
 PARAMETER C_FAMILY = virtex5
254
 PARAMETER C_IPIFBAR_NUM = 2
255
 PARAMETER C_PCIBAR_NUM = 1
256
 PARAMETER C_DEVICE_ID = 0x0505
257
 PARAMETER C_VENDOR_ID = 0x10EE
258
 PARAMETER C_CLASS_CODE = 0x058000
259
 PARAMETER C_REV_ID = 0x00
260
 PARAMETER C_SUBSYSTEM_ID = 0x0000
261
 PARAMETER C_SUBSYSTEM_VENDOR_ID = 0x0000
262
 PARAMETER C_COMP_TIMEOUT = 1
263
 PARAMETER C_IPIFBAR2PCIBAR_0 = 0x00000000
264
 PARAMETER C_IPIFBAR2PCIBAR_1 = 0x00000000
265
 PARAMETER C_PCIBAR2IPIFBAR_0 = 0xf8000000
266
 PARAMETER C_PCIBAR2IPIFBAR_1 = 0x00000000
267
 PARAMETER C_PCIBAR_LEN_0 = 20
268
 PARAMETER C_PCIBAR_LEN_1 = 28
269
 PARAMETER C_BOARD = ml507
270
 PARAMETER HW_VER = 3.00.b
271
 PARAMETER C_BASEADDR = 0x85c00000
272
 PARAMETER C_HIGHADDR = 0x85c0ffff
273
 PARAMETER C_IPIFBAR_0 = 0xc0000000
274
 PARAMETER C_IPIFBAR_HIGHADDR_0 = 0xdfffffff
275
 PARAMETER C_IPIFBAR_1 = 0xe0000000
276
 PARAMETER C_IPIFBAR_HIGHADDR_1 = 0xefffffff
277
 BUS_INTERFACE SPLB = plb_v46_0
278
 BUS_INTERFACE MPLB = ppc440_0_SPLB0
279
 PORT PERSTN = net_vcc
280
 PORT REFCLK = PCIe_Diff_Clk
281
 PORT RXN = fpga_0_PCIe_Bridge_RXN_pin
282
 PORT RXP = fpga_0_PCIe_Bridge_RXP_pin
283
 PORT TXN = fpga_0_PCIe_Bridge_TXN_pin
284
 PORT TXP = fpga_0_PCIe_Bridge_TXP_pin
285
 PORT MSI_request = net_gnd
286
END
287
 
288
BEGIN plb_v46
289
 PARAMETER INSTANCE = ppc440_0_SPLB0
290
 PARAMETER C_FAMILY = virtex5
291
 PARAMETER HW_VER = 1.04.a
292
 PORT PLB_Clk = clk_125_0000MHzPLL0_ADJUST
293
 PORT SYS_Rst = sys_bus_reset
294
END
295
 
296
BEGIN xps_ethernetlite
297
 PARAMETER INSTANCE = Ethernet_MAC
298
 PARAMETER C_FAMILY = virtex5
299
 PARAMETER HW_VER = 2.01.a
300
 PARAMETER C_BASEADDR = 0x81000000
301
 PARAMETER C_HIGHADDR = 0x8100ffff
302
 BUS_INTERFACE SPLB = plb_v46_0
303
 PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk_pin
304
 PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk_pin
305
 PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs_pin
306
 PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv_pin
307
 PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data_pin
308
 PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col_pin
309
 PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er_pin
310
 PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n_pin
311
 PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en_pin
312
 PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data_pin
313
END
314
 
315
BEGIN ppc440mc_ddr2
316
 PARAMETER INSTANCE = DDR2_SDRAM
317
 PARAMETER C_DDR_BAWIDTH = 2
318
 PARAMETER C_NUM_CLK_PAIRS = 2
319
 PARAMETER C_DDR_DWIDTH = 64
320
 PARAMETER C_DDR_CAWIDTH = 10
321
 PARAMETER C_NUM_RANKS_MEM = 1
322
 PARAMETER C_CS_BITS = 0
323
 PARAMETER C_DDR_DM_WIDTH = 8
324
 PARAMETER C_DQ_BITS = 8
325
 PARAMETER C_DDR2_ODT_WIDTH = 2
326
 PARAMETER C_DDR2_ADDT_LAT = 0
327
 PARAMETER C_INCLUDE_ECC_SUPPORT = 0
328
 PARAMETER C_DDR2_ODT_SETTING = 1
329
 PARAMETER C_DQS_BITS = 3
330
 PARAMETER C_DDR_DQS_WIDTH = 8
331
 PARAMETER C_DDR_RAWIDTH = 13
332
 PARAMETER C_DDR_BURST_LENGTH = 4
333
 PARAMETER C_DDR_CAS_LAT = 4
334
 PARAMETER C_REG_DIMM = 0
335
 PARAMETER C_MIB_MC_CLOCK_RATIO = 1
336
 PARAMETER C_DDR_TREFI = 3900
337
 PARAMETER C_DDR_TRAS = 40000
338
 PARAMETER C_DDR_TRCD = 15000
339
 PARAMETER C_DDR_TRFC = 75000
340
 PARAMETER C_DDR_TRP = 15000
341
 PARAMETER C_DDR_TRTP = 7500
342
 PARAMETER C_DDR_TWR = 15000
343
 PARAMETER C_DDR_TWTR = 7500
344
 PARAMETER C_MC_MIBCLK_PERIOD_PS = 8000
345
 PARAMETER C_IDEL_HIGH_PERF = TRUE
346
 PARAMETER C_NUM_IDELAYCTRL = 3
347
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1
348
 PARAMETER C_DQS_IO_COL = 0b000000000000000000
349
 PARAMETER C_DQ_IO_MS = 0b000000000111010100111101000011110001111000101110110000111100000110111100
350
 PARAMETER HW_VER = 2.00.a
351
 PARAMETER C_MEM_BASEADDR = 0x00000000
352
 PARAMETER C_MEM_HIGHADDR = 0x0fffffff
353
 BUS_INTERFACE PPC440MC = ppc440_0_PPC440MC
354
 PORT mc_mibclk = clk_125_0000MHzPLL0_ADJUST
355
 PORT mi_mcclk90 = clk_125_0000MHz90PLL0_ADJUST
356
 PORT mi_mcreset = sys_bus_reset
357
 PORT mi_mcclkdiv2 = clk_62_5000MHzPLL0_ADJUST
358
 PORT mi_mcclk_200 = clk_200_0000MHz
359
 PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ_pin
360
 PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS_pin
361
 PORT DDR2_DQS_N = fpga_0_DDR2_SDRAM_DDR2_DQS_N_pin
362
 PORT DDR2_A = fpga_0_DDR2_SDRAM_DDR2_A_pin
363
 PORT DDR2_BA = fpga_0_DDR2_SDRAM_DDR2_BA_pin
364
 PORT DDR2_RAS_N = fpga_0_DDR2_SDRAM_DDR2_RAS_N_pin
365
 PORT DDR2_CAS_N = fpga_0_DDR2_SDRAM_DDR2_CAS_N_pin
366
 PORT DDR2_WE_N = fpga_0_DDR2_SDRAM_DDR2_WE_N_pin
367
 PORT DDR2_CS_N = fpga_0_DDR2_SDRAM_DDR2_CS_N_pin
368
 PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT_pin
369
 PORT DDR2_CKE = fpga_0_DDR2_SDRAM_DDR2_CKE_pin
370
 PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM_pin
371
 PORT DDR2_CK = fpga_0_DDR2_SDRAM_DDR2_CK_pin
372
 PORT DDR2_CK_N = fpga_0_DDR2_SDRAM_DDR2_CK_N_pin
373
END
374
 
375
BEGIN xps_sysace
376
 PARAMETER INSTANCE = SysACE_CompactFlash
377
 PARAMETER C_MEM_WIDTH = 16
378
 PARAMETER C_FAMILY = virtex5
379
 PARAMETER HW_VER = 1.01.a
380
 PARAMETER C_BASEADDR = 0x83600000
381
 PARAMETER C_HIGHADDR = 0x8360ffff
382
 BUS_INTERFACE SPLB = plb_v46_0
383
 PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_pin
384
 PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK_pin
385
 PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin
386
 PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN_pin
387
 PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN_pin
388
 PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN_pin
389
 PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD_pin
390
END
391
 
392
BEGIN clock_generator
393
 PARAMETER INSTANCE = clock_generator_0
394
 PARAMETER C_CLKIN_FREQ = 100000000
395
 PARAMETER C_CLKFBIN_FREQ = 125000000
396
 PARAMETER C_CLKOUT0_FREQ = 125000000
397
 PARAMETER C_CLKOUT0_PHASE = 90
398
 PARAMETER C_CLKOUT0_GROUP = PLL0_ADJUST
399
 PARAMETER C_CLKOUT0_BUF = TRUE
400
 PARAMETER C_CLKOUT1_FREQ = 125000000
401
 PARAMETER C_CLKOUT1_PHASE = 0
402
 PARAMETER C_CLKOUT1_GROUP = PLL0
403
 PARAMETER C_CLKOUT1_BUF = TRUE
404
 PARAMETER C_CLKOUT2_FREQ = 125000000
405
 PARAMETER C_CLKOUT2_PHASE = 0
406
 PARAMETER C_CLKOUT2_GROUP = PLL0_ADJUST
407
 PARAMETER C_CLKOUT2_BUF = TRUE
408
 PARAMETER C_CLKOUT3_FREQ = 200000000
409
 PARAMETER C_CLKOUT3_PHASE = 0
410
 PARAMETER C_CLKOUT3_GROUP = NONE
411
 PARAMETER C_CLKOUT3_BUF = TRUE
412
 PARAMETER C_CLKOUT4_FREQ = 62500000
413
 PARAMETER C_CLKOUT4_PHASE = 0
414
 PARAMETER C_CLKOUT4_GROUP = PLL0_ADJUST
415
 PARAMETER C_CLKOUT4_BUF = TRUE
416
 PARAMETER C_CLKFBOUT_FREQ = 125000000
417
 PARAMETER C_CLKFBOUT_BUF = TRUE
418
 PARAMETER HW_VER = 3.00.a
419
 PORT CLKIN = dcm_clk_s
420
 PORT CLKFBIN = SRAM_CLK_FB_s
421
 PORT CLKOUT0 = clk_125_0000MHz90PLL0_ADJUST
422
 PORT CLKOUT1 = clk_125_0000MHzPLL0
423
 PORT CLKOUT2 = clk_125_0000MHzPLL0_ADJUST
424
 PORT CLKOUT3 = clk_200_0000MHz
425
 PORT CLKOUT4 = clk_62_5000MHzPLL0_ADJUST
426
 PORT CLKFBOUT = SRAM_CLK_OUT_s
427
 PORT RST = net_gnd
428
 PORT LOCKED = Dcm_all_locked
429
END
430
 
431
BEGIN jtagppc_cntlr
432
 PARAMETER INSTANCE = jtagppc_cntlr_inst
433
 PARAMETER HW_VER = 2.01.c
434
 BUS_INTERFACE JTAGPPC0 = ppc440_0_jtagppc_bus
435
END
436
 
437
BEGIN proc_sys_reset
438
 PARAMETER INSTANCE = proc_sys_reset_0
439
 PARAMETER C_EXT_RESET_HIGH = 0
440
 PARAMETER HW_VER = 2.00.a
441
 BUS_INTERFACE RESETPPC0 = ppc_reset_bus
442
 PORT Slowest_sync_clk = clk_125_0000MHzPLL0_ADJUST
443
 PORT Ext_Reset_In = sys_rst_s
444
 PORT Dcm_locked = Dcm_all_locked
445
 PORT Bus_Struct_Reset = sys_bus_reset
446
 PORT Peripheral_Reset = sys_periph_reset
447
END
448
 
449
BEGIN xps_intc
450
 PARAMETER INSTANCE = xps_intc_0
451
 PARAMETER HW_VER = 2.00.a
452
 PARAMETER C_BASEADDR = 0x81800000
453
 PARAMETER C_HIGHADDR = 0x8180ffff
454
 BUS_INTERFACE SPLB = plb_v46_0
455
 PORT Intr = fpga_0_Ethernet_MAC_MDINT_pin&RS232_Uart_1_Interrupt
456
 PORT Irq = ppc440_0_EICC440EXTIRQ
457
END
458
 

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