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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC440_Xilinx_Virtex5_GCC/] [system.log] - Blame information for rev 591

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Line No. Rev Author Line
1 586 jeremybenn
No logfile was found.
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Xilinx Platform Studio (XPS)
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Xilinx EDK 11.2 Build EDK_LS3.47
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Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 251 - deprecated core for architecture 'virtex5fx'!
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WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 296 - deprecated core for architecture 'virtex5fx'!
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Generating Block Diagram to Buffer
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Generated Block Diagram SVG
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At Local date and time: Mon Jun 29 21:01:23 2009
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 make -f system.make program started...
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*********************************************
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Creating software libraries...
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*********************************************
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libgen -mhs system.mhs -p xc5vfx70tff1136-1  -msg __xps/ise/xmsgprops.lst system.mss
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libgen
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Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
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Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg
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Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
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   C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
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   m.mhs line 296 - deprecated core for architecture 'virtex5fx'!
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   C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
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WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
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   m.mhs line 296 - deprecated core for architecture 'virtex5fx'!
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Checking platform configuration ...
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C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.m
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IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
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hs line 288 - 1 master(s) : 1 slave(s)
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Checking port drivers...
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   C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
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WARNING:EDK:494 -
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   esis\ not found.
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WARNING:EDK:411 - pcie -
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   m.mss line 77 - deprecated driver!
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INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0:
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  - DIP_Switches_8Bit
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  - IIC_EEPROM
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  - LEDs_Positions
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  - SRAM
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Staging source files.
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Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"
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Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"
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powerpc-eabi-ar: creating ../../../lib/libxil.a
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Compiling gpio
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Compiling uartlite
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Compiling intc
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Running execs_generate.
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    -mcpu=440  -Wl,-T -Wl,/cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
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powerpc-eabi-size RTOSDemo/executable.elf
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  53754     372   86524  140650   2256a RTOSDemo/executable.elf
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        C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
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Done writing Tab View settings to:
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Xilinx EDK 11.2 Build EDK_LS3.47
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Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
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WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
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Generating Block Diagram to Buffer
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Generated Block Diagram SVG
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At Local date and time: Tue Jun 30 18:32:58 2009
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rm -f platgen.log
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rm -f implementation/system.bmm
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rm -f implementation/system.ncd
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rm -f implementation/system_map.ncd
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rm -rf implementation synthesis xst hdl
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rm -f implementation/system.ngc
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rm -f __xps/ise/_xmsgs/platgen.xmsgs
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Done!
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At Local date and time: Tue Jun 30 18:33:13 2009
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rm -f implementation/system.ncd
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Done!
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At Local date and time: Tue Jun 30 18:33:24 2009
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rm -rf ppc440_0/
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rm -f __xps/ise/_xmsgs/libgen.xmsgs
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Done!
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At Local date and time: Tue Jun 30 18:33:31 2009
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 make -f system.make programclean started...
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rm -f RTOSDemo/executable.elf
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At Local date and time: Tue Jun 30 18:33:37 2009
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 make -f system.make swclean started...
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rm -rf ppc440_0/
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rm -f libgen.log
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Done!
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Writing filter settings....
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        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
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        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
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Xilinx EDK 11.2 Build EDK_LS3.47
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Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
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WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
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Generating Block Diagram to Buffer
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Generated Block Diagram SVG
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 make -f system.make program started...
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*********************************************
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Creating software libraries...
254
*********************************************
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libgen -mhs system.mhs -p xc5vfx70tff1136-1  -msg __xps/ise/xmsgprops.lst system.mss
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libgen
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Xilinx EDK 11.2 Build EDK_LS3.47
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Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
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Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg
261
__xps/ise/xmsgprops.lst system.mss
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Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
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   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
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   251 - deprecated core for architecture 'virtex5fx'!
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   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
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   296 - deprecated core for architecture 'virtex5fx'!
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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
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   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
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   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
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Checking platform configuration ...
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C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
281
107 - 1 master(s) : 12 slave(s)
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IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
283
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
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288 - 1 master(s) : 1 slave(s)
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WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
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   446 - floating connection!
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291
 
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Performing Reset DRCs...
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Running system level update procedures...
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Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
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Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
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   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\synthesis\ not
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   found.
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WARNING:EDK:411 - pcie -
311
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mss line
312
   77 - deprecated driver!
313
WARNING:EDK:411 - emaclite -
314
 
315
 
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INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0:
317
 
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  - DIP_Switches_8Bit
319
 
320
  - IIC_EEPROM
321
  - LEDs_8Bit
322
 
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  - PCIe_Bridge
324
  - Push_Buttons_5Bit
325
 
326
  - SRAM
327
  - SysACE_CompactFlash
328
 
329
  - xps_intc_0
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331
-- Generating libraries for processor: ppc440_0 --
332
 
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335
Running DRCs.
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Running post_generate.
338
 
339
"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440  -O2 -c"
340
"EXTRA_COMPILER_FLAGS=-g"'.
341
 
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Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"
343
"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440  -O2 -c"
344
"EXTRA_COMPILER_FLAGS=-g"'.
345
Compiling common
346
powerpc-eabi-ar: creating ../../../lib/libxil.a
347
 
348
Compiling lldma
349
 
350
Compiling gpio
351
 
352
 
353
 
354
Compiling uartlite
355
 
356
Compiling intc
357
 
358
 
359
 
360
    -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
361
 
362
powerpc-eabi-size RTOSDemo/executable.elf
363
 
364
  53754     372   86524  140650   2256a RTOSDemo/executable.elf
365
 
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368
369
 
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        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
373
 
374
Done writing Tab View settings to:
375
 
376
377
 
378
Xilinx EDK 11.2 Build EDK_LS3.47
379
 
380
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
381
 
382
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
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WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
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Generating Block Diagram to Buffer
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At Local date and time: Tue Jun 30 21:05:40 2009
391
 
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Creating system netlist for hardware specification..
395
 
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platgen -p xc5vfx70tff1136-1 -lang vhdl   -msg __xps/ise/xmsgprops.lst system.mhs
397
 
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Release 11.2 - platgen Xilinx EDK 11.2 Build EDK_LS3.47
399
 
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Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
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Parse C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/system.mhs
407
 
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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
411
 
412
   251 - deprecated core for architecture 'virtex5fx'!
413
 
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415
 
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WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
417
 
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   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
421
 
422
 
423
 
424
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427
 
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Address Map for Processor ppc440_0
429
 
430
 
431
 
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  (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0
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435
 
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  (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0
437
 
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  (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0
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  (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
447
 
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   C_SPLB0_P2P value to 0
449
 
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Computing clock values...
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   'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be
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   through the clock generator IP.
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INFO:EDK:1432 - Frequency for Top-Level Input Clock
457
 
458
   performed for IPs connected to that clock port, unless they are connected
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461
 
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
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   C_PLBV46_NUM_MASTERS value to 1
465
 
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
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   C_PLBV46_NUM_SLAVES value to 12
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
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   C_PLBV46_MID_WIDTH value to 1
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
475
 
476
   value to 128
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
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480
   PARAMETER C_SPLB_DWIDTH value to 128
481
 
482
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
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   PARAMETER C_SPLB_NUM_MASTERS value to 1
485
 
486
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
487
 
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   PARAMETER C_SPLB_SMALLEST_MASTER value to 128
489
 
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
491
 
492
   value to 0x2000
493
 
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   C_PORT_DWIDTH value to 64
497
 
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01
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   C_SPLB_DWIDTH value to 128
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
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   value to 128
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
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512
   value to 128
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
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   value to 128
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
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   value to 128
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INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -
526
 
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   a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER
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   C_SPLB_DWIDTH value to 128
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INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -
530
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
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   a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER
532
   C_SPLB_SMALLEST_MASTER value to 128
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INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
534
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
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   b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER
536
   C_MPLB_DWIDTH value to 128
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INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
538
 
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   b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER
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   C_MPLB_SMALLEST_SLAVE value to 128
541
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
542
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
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   b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER
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   C_SPLB_MID_WIDTH value to 1
545
 
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   b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER
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INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
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   b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER
552
   C_SPLB_SMALLEST_MASTER value to 128
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
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   b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER
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INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
558
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
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   C_PLBV46_NUM_MASTERS value to 1
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
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   C_PLBV46_NUM_SLAVES value to 1
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
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   C_PLBV46_MID_WIDTH value to 1
569
 
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
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   ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH
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INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
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   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
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   2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding
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   PARAMETER C_SPLB_DWIDTH value to 128
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   \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER
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INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -
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   \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER
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INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
590
 
591
   ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH
592
 
593
 
594
 
595
596
 
597
INFO:EDK:1563 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
598
 
599
 
600
 
601
   The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs
602
 
603
   operation.
604
 
605
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
606
 
607
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
608
 
609
288 - 1 master(s) : 1 slave(s)
610
 
611
Checking port drivers...
612
 
613
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
614
 
615
616
 
617
618
 
619
620
 
621
INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -
622
 
623
   01_a\data\ppc440_virtex5_v2_1_0.mpd line 124 - tcl is overriding PARAMETER
624
 
625
INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -
626
 
627
 
628
 
629
INFO:EDK:1560 - IPNAME:jtagppc_cntlr INSTANCE:jtagppc_cntlr_inst -
630
 
631
 
632
 
633
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
634
 
635
 
636
 
637
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
638
 
639
   ata\xps_intc_v2_1_0.mpd line 80 - tcl is overriding PARAMETER C_KIND_OF_EDGE
640
 
641
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
642
 
643
   ata\xps_intc_v2_1_0.mpd line 81 - tcl is overriding PARAMETER C_KIND_OF_LVL
644
 
645
646
 
647
648
 
649
650
 
651
652
 
653
654
 
655
656
 
657
INFO: The PCIe_Bridge core has constraints automatically generated by XPS in
658
 
659
It can be overridden by constraints placed in the system.ucf file.
660
 
661
662
 
663
INFO: The Ethernet_MAC core has constraints automatically generated by XPS in
664
 
665
It can be overridden by constraints placed in the system.ucf file.
666
 
667
668
 
669
INFO: The DDR2_SDRAM core has constraints automatically generated by XPS in
670
 
671
It can be overridden by constraints placed in the system.ucf file.
672
 
673
674
 
675
676
 
677
678
 
679
680
 
681
 
682
 
683
Creating hardware output directories ...
684
 
685
Managing hardware (BBD-specified) netlist files ...
686
 
687
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
688
 
689
IPNAME:xps_ethernetlite INSTANCE:ethernet_mac -
690
 
691
296 - Copying (BBD-specified) netlist files.
692
 
693
 
694
 
695
Elaborating instances ...
696
 
697
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
698
 
699
700
 
701
702
 
703
 
704
 
705
Constructing platform-level connectivity ...
706
 
707
708
 
709
710
 
711
712
 
713
714
 
715
716
 
717
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
718
 
719
INSTANCE:ppc440_0 -
720
 
721
- Running XST synthesis
722
 
723
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
724
 
725
INSTANCE:xps_bram_if_cntlr_1 -
726
 
727
116 - Running XST synthesis
728
 
729
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
730
 
731
INSTANCE:rs232_uart_1 -
732
 
733
136 - Running XST synthesis
734
 
735
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
736
 
737
INSTANCE:leds_positions -
738
 
739
166 - Running XST synthesis
740
 
741
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
742
 
743
INSTANCE:dip_switches_8bit -
744
 
745
194 - Running XST synthesis
746
 
747
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
748
 
749
INSTANCE:sram -
750
 
751
221 - Running XST synthesis
752
 
753
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
754
 
755
INSTANCE:ppc440_0_splb0 -
756
 
757
288 - Running XST synthesis
758
 
759
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
760
 
761
INSTANCE:ddr2_sdram -
762
 
763
315 - Running XST synthesis
764
 
765
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
766
 
767
INSTANCE:clock_generator_0 -
768
 
769
392 - Running XST synthesis
770
 
771
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
772
 
773
INSTANCE:proc_sys_reset_0 -
774
 
775
437 - Running XST synthesis
776
 
777
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
778
 
779
780
 
781
IPNAME:ppc440_0_wrapper INSTANCE:ppc440_0 -
782
 
783
- Running NGCBUILD
784
 
785
 with local file
786
 
787
788
 
789
xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..
790
 
791
792
 
793
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/pp
794
 
795
796
 
797
798
 
799
-------------------------------
800
 
801
  No Partitions were found in this design.
802
 
803
-------------------------------
804
 
805
NGCBUILD Design Results Summary:
806
 
807
  Number of warnings:   0
808
 
809
Writing NGC file "../ppc440_0_wrapper.ngc" ...
810
 
811
Total CPU time to NGCBUILD completion:   6 sec
812
 
813
Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...
814
 
815
NGCBUILD done.
816
 
817
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
818
 
819
PMSPEC -- Overriding Xilinx file
820
 
821
822
 
823
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
824
 
825
../rs232_uart_1_wrapper.ngc
826
 
827
Reading NGO file
828
 
829
232_uart_1_wrapper/rs232_uart_1_wrapper.ngc" ...
830
 
831
Partition Implementation Status
832
 
833
834
 
835
836
 
837
838
 
839
  Number of errors:     0
840
 
841
842
 
843
Total REAL time to NGCBUILD completion:  8 sec
844
 
845
846
 
847
848
 
849
IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -
850
 
851
251 - Running NGCBUILD
852
 
853
 with local file
854
 
855
856
 
857
xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..
858
 
859
860
 
861
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/pc
862
 
863
Executing edif2ngd -noa
864
 
865
ie_bridge_wrapper_fifo_generator_v4_3.edn"
866
 
867
Release 11.2 - edif2ngd L.46 (nt)
868
 
869
INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)
870
 
871
PMSPEC -- Overriding Xilinx file 
872
 
873
Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...
874
 
875
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc
876
 
877
Loading design module
878
 
879
Loading design module
880
 
881
ie_bridge_wrapper/dpram_70_512.ngc"...
882
 
883
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc
884
 
885
886
 
887
888
 
889
-------------------------------
890
 
891
  No Partitions were found in this design.
892
 
893
-------------------------------
894
 
895
NGCBUILD Design Results Summary:
896
 
897
  Number of warnings:   0
898
 
899
Writing NGC file "../pcie_bridge_wrapper.ngc" ...
900
 
901
Total CPU time to NGCBUILD completion:   9 sec
902
 
903
Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...
904
 
905
NGCBUILD done.
906
 
907
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
908
 
909
PMSPEC -- Overriding Xilinx file
910
 
911
912
 
913
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
914
 
915
ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc
916
 
917
Reading NGO file
918
 
919
hernet_mac_wrapper/ethernet_mac_wrapper.ngc" ...
920
 
921
"ethernetlite_v1_01_b_dmem_v2.ngo"
922
 
923
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
924
 
925
INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
926
 
927
with local file 
928
 
929
Loading design module
930
 
931
hernet_mac_wrapper\ethernetlite_v1_01_b_dmem_v2.ngo"...
932
 
933
Applying constraints in "ethernet_mac_wrapper.ucf" to the design...
934
 
935
Partition Implementation Status
936
 
937
938
 
939
940
 
941
942
 
943
  Number of errors:     0
944
 
945
946
 
947
Total REAL time to NGCBUILD completion:  9 sec
948
 
949
950
 
951
952
 
953
IPNAME:ddr2_sdram_wrapper INSTANCE:ddr2_sdram -
954
 
955
315 - Running NGCBUILD
956
 
957
 with local file
958
 
959
960
 
961
xc5vfx70tff1136-1 -intstyle silent -uc ddr2_sdram_wrapper.ucf -sd ..
962
 
963
964
 
965
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/dd
966
 
967
968
 
969
 
970
 
971
-------------------------------
972
 
973
 
974
 
975
-------------------------------
976
 
977
NGCBUILD Design Results Summary:
978
 
979
  Number of warnings:   0
980
 
981
Writing NGC file "../ddr2_sdram_wrapper.ngc" ...
982
 
983
Total CPU time to NGCBUILD completion:   7 sec
984
 
985
Writing NGCBUILD log file "../ddr2_sdram_wrapper.blc"...
986
 
987
NGCBUILD done.
988
 
989
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
990
 
991
PMSPEC -- Overriding Xilinx file
992
 
993
994
 
995
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
996
 
997
../xps_intc_0_wrapper.ngc
998
 
999
Reading NGO file
1000
 
1001
s_intc_0_wrapper/xps_intc_0_wrapper.ngc" ...
1002
 
1003
 
1004
 
1005
1006
 
1007
1008
 
1009
1010
 
1011
  Number of errors:     0
1012
 
1013
 
1014
 
1015
Total REAL time to NGCBUILD completion:  1 sec
1016
 
1017
 
1018
 
1019
1020
 
1021
 
1022
 
1023
1024
 
1025
Running synthesis...
1026
 
1027
xst -ifn system_xst.scr -intstyle silent
1028
 
1029
XST completed
1030
 
1031
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
1032
 
1033
1034
 
1035
Command Line: c:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe
1036
 
1037
../__xps/ise/system.ise
1038
 
1039
Reading NGO file
1040
 
1041
ngc" ...
1042
 
1043
Loading design module "../implementation/plb_v46_0_wrapper.ngc"...
1044
 
1045
Loading design module
1046
 
1047
Loading design module "../implementation/rs232_uart_1_wrapper.ngc"...
1048
 
1049
Loading design module "../implementation/leds_positions_wrapper.ngc"...
1050
 
1051
Loading design module "../implementation/dip_switches_8bit_wrapper.ngc"...
1052
 
1053
Loading design module "../implementation/sram_wrapper.ngc"...
1054
 
1055
Loading design module "../implementation/ppc440_0_splb0_wrapper.ngc"...
1056
 
1057
Loading design module "../implementation/ddr2_sdram_wrapper.ngc"...
1058
 
1059
Loading design module "../implementation/clock_generator_0_wrapper.ngc"...
1060
 
1061
Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...
1062
 
1063
1064
 
1065
-------------------------------
1066
 
1067
  No Partitions were found in this design.
1068
 
1069
-------------------------------
1070
 
1071
NGCBUILD Design Results Summary:
1072
 
1073
 
1074
 
1075
Writing NGC file "../implementation/system.ngc" ...
1076
 
1077
 
1078
 
1079
Writing NGCBUILD log file "../implementation/system.blc"...
1080
 
1081
 
1082
 
1083
Running Xilinx Implementation tools..
1084
 
1085
 
1086
 
1087
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
1088
 
1089
 
1090
 
1091
 with local file
1092
 
1093
 
1094
 
1095
C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation
1096
 
1097
Using Flow File:
1098
 
1099
a.flw
1100
 
1101
 
1102
low.opt
1103
 
1104
 
1105
 
1106
 
1107
 
1108
 
1109
 
1110
 
1111
 
1112
#----------------------------------------------#
1113
 
1114
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
1115
 
1116
 
1117
1118
 
1119
 
1120
 
1121
 
1122
 
1123
 
1124
 
1125
 
1126
 
1127
Gathering constraint information from source properties...
1128
 
1129
1130
 
1131
 
1132
   'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_
1133
 
1134
 
1135
 
1136
 
1137
 
1138
 
1139
 
1140
 
1141
 
1142
 
1143
 
1144
   found.
1145
 
1146
 
1147
 
1148
   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
1149
 
1150
 
1151
 
1152
   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *
1153
 
1154
1155
 
1156
 
1157
 
1158
   The following new TNM groups and period specifications were generated at the
1159
 
1160
 
1161
 
1162
   1.25 HIGH 50%>
1163
 
1164
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
1165
 
1166
   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
1167
 
1168
   PLL_ADV output(s):
1169
 
1170
   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *
1171
 
1172
1173
 
1174
   'TS_sys_clk_pin', was traced into PLL_ADV instance
1175
 
1176
 
1177
 
1178
   CLKOUT3: 
1179
 
1180
 
1181
 
1182
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
1183
 
1184
   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
1185
 
1186
   PLL_ADV output(s):
1187
 
1188
   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_" TS_sys_clk_pin *
1189
 
1190
 
1191
 
1192
Checking Partitions ...
1193
 
1194
 
1195
 
1196
WARNING:NgdBuild:1212 - User specified non-default attribute value
1197
 
1198
   "clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".
1199
 
1200
 
1201
 
1202
Checking expanded design ...
1203
 
1204
   'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_
1205
 
1206
 
1207
 
1208
   'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[2].DQT_REG' has
1209
 
1210
 
1211
 
1212
   ALIGN_PIPE' has unconnected output pin
1213
 
1214
 
1215
 
1216
   has unconnected output pin
1217
 
1218
 
1219
 
1220
   has unconnected output pin
1221
 
1222
 
1223
 
1224
   RE_I' has unconnected output pin
1225
 
1226
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1227
 
1228
   E_I' has unconnected output pin
1229
 
1230
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1231
 
1232
   ' has unconnected output pin
1233
 
1234
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1235
 
1236
   ' has unconnected output pin
1237
 
1238
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1239
 
1240
   ' has unconnected output pin
1241
 
1242
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1243
 
1244
   ' has unconnected output pin
1245
 
1246
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1247
 
1248
   has unconnected output pin
1249
 
1250
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
1251
 
1252
   ' has unconnected output pin
1253
 
1254
   "PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_ad
1255
 
1256
WARNING:NgdBuild:443 - SFF primitive
1257
 
1258
   URSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has
1259
 
1260
WARNING:NgdBuild:443 - SFF primitive
1261
 
1262
   URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has
1263
 
1264
WARNING:NgdBuild:443 - SFF primitive
1265
 
1266
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
1267
 
1268
WARNING:NgdBuild:443 - SFF primitive
1269
 
1270
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
1271
 
1272
WARNING:NgdBuild:443 - SFF primitive
1273
 
1274
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
1275
 
1276
WARNING:NgdBuild:443 - SFF primitive
1277
 
1278
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
1279
 
1280
WARNING:NgdBuild:443 - SFF primitive
1281
 
1282
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B
1283
 
1284
WARNING:NgdBuild:443 - SFF primitive
1285
 
1286
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B
1287
 
1288
WARNING:NgdBuild:443 - SFF primitive
1289
 
1290
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B
1291
 
1292
WARNING:NgdBuild:443 - SFF primitive
1293
 
1294
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_B
1295
 
1296
WARNING:NgdBuild:443 - SFF primitive
1297
 
1298
   _H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin
1299
 
1300
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S
1301
 
1302
WARNING:NgdBuild:443 - SFF primitive
1303
 
1304
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected
1305
 
1306
WARNING:NgdBuild:443 - SFF primitive
1307
 
1308
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected
1309
 
1310
WARNING:NgdBuild:443 - SFF primitive
1311
 
1312
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected
1313
 
1314
WARNING:NgdBuild:443 - SFF primitive
1315
 
1316
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected
1317
 
1318
WARNING:NgdBuild:443 - SFF primitive
1319
 
1320
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected
1321
 
1322
WARNING:NgdBuild:443 - SFF primitive
1323
 
1324
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected
1325
 
1326
WARNING:NgdBuild:443 - SFF primitive
1327
 
1328
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected
1329
 
1330
WARNING:NgdBuild:443 - SFF primitive
1331
 
1332
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected
1333
 
1334
WARNING:NgdBuild:443 - SFF primitive
1335
 
1336
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected
1337
 
1338
WARNING:NgdBuild:443 - SFF primitive
1339
 
1340
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected
1341
 
1342
WARNING:NgdBuild:443 - SFF primitive
1343
 
1344
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected
1345
 
1346
WARNING:NgdBuild:443 - SFF primitive
1347
 
1348
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected
1349
 
1350
 
1351
 
1352
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected
1353
 
1354
WARNING:NgdBuild:443 - SFF primitive
1355
 
1356
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected
1357
 
1358
WARNING:NgdBuild:443 - SFF primitive
1359
 
1360
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected
1361
 
1362
WARNING:NgdBuild:443 - SFF primitive
1363
 
1364
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_CE_REG' has unconnected
1365
 
1366
 
1367
 
1368
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_RDCE_REG' has unconnected
1369
 
1370
WARNING:NgdBuild:443 - SFF primitive
1371
 
1372
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_WRCE_REG' has unconnected
1373
 
1374
 
1375
 
1376
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected
1377
 
1378
WARNING:NgdBuild:443 - SFF primitive
1379
 
1380
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_RDCE_REG' has unconnected
1381
 
1382
 
1383
 
1384
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected
1385
 
1386
 
1387
 
1388
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_CE_REG' has unconnected
1389
 
1390
WARNING:NgdBuild:443 - SFF primitive
1391
 
1392
 
1393
 
1394
WARNING:NgdBuild:443 - SFF primitive
1395
 
1396
 
1397
 
1398
WARNING:NgdBuild:443 - SFF primitive
1399
 
1400
 
1401
 
1402
WARNING:NgdBuild:443 - SFF primitive
1403
 
1404
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected
1405
 
1406
WARNING:NgdBuild:443 - SFF primitive
1407
 
1408
 
1409
 
1410
WARNING:NgdBuild:443 - SFF primitive
1411
 
1412
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected
1413
 
1414
WARNING:NgdBuild:443 - SFF primitive
1415
 
1416
 
1417
 
1418
WARNING:NgdBuild:443 - SFF primitive
1419
 
1420
 
1421
 
1422
WARNING:NgdBuild:443 - SFF primitive
1423
 
1424
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected
1425
 
1426
WARNING:NgdBuild:443 - SFF primitive
1427
 
1428
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has
1429
 
1430
WARNING:NgdBuild:443 - SFF primitive
1431
 
1432
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has
1433
 
1434
WARNING:NgdBuild:443 - SFF primitive
1435
 
1436
 
1437
 
1438
WARNING:NgdBuild:443 - SFF primitive
1439
 
1440
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has
1441
 
1442
WARNING:NgdBuild:443 - SFF primitive
1443
 
1444
 
1445
 
1446
WARNING:NgdBuild:443 - SFF primitive
1447
 
1448
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_CE_REG' has unconnected
1449
 
1450
WARNING:NgdBuild:443 - SFF primitive
1451
 
1452
 
1453
 
1454
WARNING:NgdBuild:443 - SFF primitive
1455
 
1456
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has
1457
 
1458
 
1459
 
1460
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected
1461
 
1462
 
1463
 
1464
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has
1465
 
1466
 
1467
 
1468
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has
1469
 
1470
WARNING:NgdBuild:443 - SFF primitive
1471
 
1472
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected
1473
 
1474
 
1475
 
1476
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has
1477
 
1478
WARNING:NgdBuild:443 - SFF primitive
1479
 
1480
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has
1481
 
1482
 
1483
 
1484
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected
1485
 
1486
 
1487
 
1488
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has
1489
 
1490
WARNING:NgdBuild:443 - SFF primitive
1491
 
1492
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has
1493
 
1494
WARNING:NgdBuild:443 - SFF primitive
1495
 
1496
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected
1497
 
1498
WARNING:NgdBuild:443 - SFF primitive
1499
 
1500
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has
1501
 
1502
 
1503
 
1504
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has
1505
 
1506
WARNING:NgdBuild:443 - SFF primitive
1507
 
1508
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected
1509
 
1510
 
1511
 
1512
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has
1513
 
1514
WARNING:NgdBuild:443 - SFF primitive
1515
 
1516
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has
1517
 
1518
WARNING:NgdBuild:443 - SFF primitive
1519
 
1520
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected
1521
 
1522
WARNING:NgdBuild:443 - SFF primitive
1523
 
1524
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has
1525
 
1526
WARNING:NgdBuild:443 - SFF primitive
1527
 
1528
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_WRCE_REG' has
1529
 
1530
WARNING:NgdBuild:443 - SFF primitive
1531
 
1532
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_CE_REG' has unconnected
1533
 
1534
WARNING:NgdBuild:443 - SFF primitive
1535
 
1536
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_RDCE_REG' has
1537
 
1538
WARNING:NgdBuild:443 - SFF primitive
1539
 
1540
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has
1541
 
1542
WARNING:NgdBuild:443 - SFF primitive
1543
 
1544
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_CE_REG' has unconnected
1545
 
1546
WARNING:NgdBuild:443 - SFF primitive
1547
 
1548
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has
1549
 
1550
WARNING:NgdBuild:443 - SFF primitive
1551
 
1552
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_WRCE_REG' has
1553
 
1554
WARNING:NgdBuild:443 - SFF primitive
1555
 
1556
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_CE_REG' has unconnected
1557
 
1558
WARNING:NgdBuild:443 - SFF primitive
1559
 
1560
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has
1561
 
1562
 
1563
 
1564
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has
1565
 
1566
 
1567
 
1568
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected
1569
 
1570
WARNING:NgdBuild:443 - SFF primitive
1571
 
1572
 
1573
 
1574
WARNING:NgdBuild:443 - SFF primitive
1575
 
1576
 
1577
 
1578
WARNING:NgdBuild:443 - SFF primitive
1579
 
1580
 
1581
 
1582
WARNING:NgdBuild:443 - SFF primitive
1583
 
1584
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has
1585
 
1586
WARNING:NgdBuild:443 - SFF primitive
1587
 
1588
 
1589
 
1590
WARNING:NgdBuild:443 - SFF primitive
1591
 
1592
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected
1593
 
1594
WARNING:NgdBuild:443 - SFF primitive
1595
 
1596
 
1597
 
1598
WARNING:NgdBuild:443 - SFF primitive
1599
 
1600
 
1601
 
1602
WARNING:NgdBuild:443 - SFF primitive
1603
 
1604
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_CE_REG' has unconnected
1605
 
1606
WARNING:NgdBuild:443 - SFF primitive
1607
 
1608
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_RDCE_REG' has
1609
 
1610
WARNING:NgdBuild:443 - SFF primitive
1611
 
1612
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_WRCE_REG' has
1613
 
1614
WARNING:NgdBuild:443 - SFF primitive
1615
 
1616
 
1617
 
1618
WARNING:NgdBuild:443 - SFF primitive
1619
 
1620
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_RDCE_REG' has
1621
 
1622
WARNING:NgdBuild:443 - SFF primitive
1623
 
1624
 
1625
 
1626
WARNING:NgdBuild:443 - SFF primitive
1627
 
1628
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_CE_REG' has unconnected
1629
 
1630
WARNING:NgdBuild:443 - SFF primitive
1631
 
1632
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_RDCE_REG' has
1633
 
1634
WARNING:NgdBuild:443 - SFF primitive
1635
 
1636
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has
1637
 
1638
WARNING:NgdBuild:443 - SFF primitive
1639
 
1640
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected
1641
 
1642
WARNING:NgdBuild:443 - SFF primitive
1643
 
1644
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has
1645
 
1646
WARNING:NgdBuild:443 - SFF primitive
1647
 
1648
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_WRCE_REG' has
1649
 
1650
WARNING:NgdBuild:443 - SFF primitive
1651
 
1652
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected
1653
 
1654
WARNING:NgdBuild:443 - SFF primitive
1655
 
1656
 
1657
 
1658
WARNING:NgdBuild:443 - SFF primitive
1659
 
1660
 
1661
 
1662
WARNING:NgdBuild:443 - SFF primitive
1663
 
1664
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_CE_REG' has unconnected
1665
 
1666
 
1667
 
1668
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has
1669
 
1670
 
1671
 
1672
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has
1673
 
1674
 
1675
 
1676
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected
1677
 
1678
WARNING:NgdBuild:443 - SFF primitive
1679
 
1680
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has
1681
 
1682
 
1683
 
1684
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has
1685
 
1686
WARNING:NgdBuild:443 - SFF primitive
1687
 
1688
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected
1689
 
1690
 
1691
 
1692
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected
1693
 
1694
 
1695
 
1696
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected
1697
 
1698
WARNING:NgdBuild:443 - SFF primitive
1699
 
1700
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected
1701
 
1702
WARNING:NgdBuild:443 - SFF primitive
1703
 
1704
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected
1705
 
1706
WARNING:NgdBuild:443 - SFF primitive
1707
 
1708
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected
1709
 
1710
 
1711
 
1712
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected
1713
 
1714
WARNING:NgdBuild:443 - SFF primitive
1715
 
1716
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[39].I_BKend_CE_REG' has unconnected
1717
 
1718
 
1719
 
1720
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[40].I_BKend_CE_REG' has unconnected
1721
 
1722
WARNING:NgdBuild:443 - SFF primitive
1723
 
1724
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[41].I_BKend_CE_REG' has unconnected
1725
 
1726
 
1727
 
1728
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[42].I_BKend_CE_REG' has unconnected
1729
 
1730
 
1731
 
1732
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[43].I_BKend_CE_REG' has unconnected
1733
 
1734
WARNING:NgdBuild:443 - SFF primitive
1735
 
1736
 
1737
 
1738
WARNING:NgdBuild:443 - SFF primitive
1739
 
1740
 
1741
 
1742
WARNING:NgdBuild:443 - SFF primitive
1743
 
1744
 
1745
 
1746
WARNING:NgdBuild:443 - SFF primitive
1747
 
1748
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_CE_REG' has unconnected
1749
 
1750
WARNING:NgdBuild:443 - SFF primitive
1751
 
1752
 
1753
 
1754
WARNING:NgdBuild:443 - SFF primitive
1755
 
1756
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_WRCE_REG' has
1757
 
1758
WARNING:NgdBuild:443 - SFF primitive
1759
 
1760
 
1761
 
1762
WARNING:NgdBuild:443 - SFF primitive
1763
 
1764
 
1765
 
1766
WARNING:NgdBuild:443 - SFF primitive
1767
 
1768
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_WRCE_REG' has
1769
 
1770
WARNING:NgdBuild:443 - SFF primitive
1771
 
1772
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_CE_REG' has unconnected
1773
 
1774
WARNING:NgdBuild:443 - SFF primitive
1775
 
1776
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_RDCE_REG' has
1777
 
1778
WARNING:NgdBuild:443 - SFF primitive
1779
 
1780
 
1781
 
1782
WARNING:NgdBuild:443 - SFF primitive
1783
 
1784
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_CE_REG' has unconnected
1785
 
1786
WARNING:NgdBuild:443 - SFF primitive
1787
 
1788
 
1789
 
1790
WARNING:NgdBuild:443 - SFF primitive
1791
 
1792
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_WRCE_REG' has
1793
 
1794
WARNING:NgdBuild:443 - SFF primitive
1795
 
1796
 
1797
 
1798
WARNING:NgdBuild:443 - SFF primitive
1799
 
1800
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_RDCE_REG' has
1801
 
1802
 
1803
 
1804
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_WRCE_REG' has
1805
 
1806
 
1807
 
1808
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_CE_REG' has unconnected
1809
 
1810
 
1811
 
1812
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_RDCE_REG' has
1813
 
1814
WARNING:NgdBuild:443 - SFF primitive
1815
 
1816
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_WRCE_REG' has
1817
 
1818
 
1819
 
1820
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_CE_REG' has unconnected
1821
 
1822
WARNING:NgdBuild:443 - SFF primitive
1823
 
1824
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_RDCE_REG' has
1825
 
1826
 
1827
 
1828
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has
1829
 
1830
 
1831
 
1832
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_CE_REG' has unconnected
1833
 
1834
 
1835
 
1836
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_RDCE_REG' has
1837
 
1838
 
1839
 
1840
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_WRCE_REG' has
1841
 
1842
WARNING:NgdBuild:443 - SFF primitive
1843
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1844
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_CE_REG' has unconnected
1845
   output pin
1846
WARNING:NgdBuild:443 - SFF primitive
1847
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1848
 
1849
   unconnected output pin
1850
 
1851
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1852
 
1853
   unconnected output pin
1854
 
1855
 
1856
 
1857
   output pin
1858
 
1859
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1860
 
1861
   unconnected output pin
1862
 
1863
 
1864
 
1865
   unconnected output pin
1866
 
1867
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1868
 
1869
   output pin
1870
 
1871
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1872
 
1873
   unconnected output pin
1874
 
1875
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1876
 
1877
   unconnected output pin
1878
 
1879
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1880
 
1881
   output pin
1882
 
1883
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1884
 
1885
   output pin
1886
 
1887
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1888
 
1889
   output pin
1890
 
1891
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1892
 
1893
   output pin
1894
 
1895
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1896
 
1897
   output pin
1898
 
1899
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1900
 
1901
   output pin
1902
 
1903
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1904
 
1905
   unconnected output pin
1906
 
1907
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1908
 
1909
   unconnected output pin
1910
 
1911
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1912
 
1913
 
1914
 
1915
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1916
 
1917
   unconnected output pin
1918
 
1919
 
1920
 
1921
   unconnected output pin
1922
 
1923
 
1924
 
1925
   output pin
1926
 
1927
 
1928
 
1929
   unconnected output pin
1930
 
1931
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1932
 
1933
   unconnected output pin
1934
 
1935
 
1936
 
1937
   output pin
1938
 
1939
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1940
 
1941
   unconnected output pin
1942
 
1943
 
1944
 
1945
   unconnected output pin
1946
 
1947
 
1948
 
1949
   unconnected output pin
1950
 
1951
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1952
   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_CE_REG' has
1953
   unconnected output pin
1954
WARNING:NgdBuild:443 - SFF primitive
1955
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1956
 
1957
   unconnected output pin
1958
 
1959
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1960
 
1961
   unconnected output pin
1962
 
1963
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1964
 
1965
   unconnected output pin
1966
 
1967
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1968
 
1969
   unconnected output pin
1970
 
1971
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1972
 
1973
   unconnected output pin
1974
 
1975
 
1976
 
1977
   unconnected output pin
1978
 
1979
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1980
 
1981
   unconnected output pin
1982
 
1983
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1984
 
1985
   unconnected output pin
1986
 
1987
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1988
 
1989
 
1990
 
1991
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1992
 
1993
 
1994
 
1995
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
1996
 
1997
   unconnected output pin
1998
 
1999
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2000
 
2001
   unconnected output pin
2002
 
2003
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2004
 
2005
   unconnected output pin
2006
 
2007
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2008
 
2009
   unconnected output pin
2010
 
2011
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2012
 
2013
   unconnected output pin
2014
 
2015
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2016
 
2017
   unconnected output pin
2018
 
2019
 
2020
 
2021
   unconnected output pin
2022
 
2023
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2024
 
2025
   unconnected output pin
2026
 
2027
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2028
 
2029
 
2030
 
2031
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2032
 
2033
   unconnected output pin
2034
 
2035
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2036
 
2037
   unconnected output pin
2038
 
2039
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2040
 
2041
 
2042
 
2043
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2044
 
2045
   unconnected output pin
2046
 
2047
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2048
 
2049
   unconnected output pin
2050
 
2051
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2052
 
2053
   unconnected output pin
2054
 
2055
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2056
 
2057
   unconnected output pin
2058
 
2059
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2060
 
2061
   unconnected output pin
2062
 
2063
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2064
 
2065
   unconnected output pin
2066
 
2067
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2068
 
2069
   unconnected output pin
2070
 
2071
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2072
 
2073
 
2074
 
2075
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2076
 
2077
   unconnected output pin
2078
 
2079
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2080
 
2081
   unconnected output pin
2082
 
2083
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2084
 
2085
   unconnected output pin
2086
 
2087
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2088
 
2089
   unconnected output pin
2090
 
2091
 
2092
 
2093
WARNING:NgdBuild:443 - SFF primitive
2094
 
2095
   E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin
2096
 
2097
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2098
 
2099
   output pin
2100
 
2101
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2102
 
2103
   unconnected output pin
2104
 
2105
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2106
 
2107
   unconnected output pin
2108
 
2109
 
2110
 
2111
   output pin
2112
 
2113
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2114
 
2115
   unconnected output pin
2116
 
2117
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
2118
 
2119
   unconnected output pin
2120
 
2121
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
2122
 
2123
WARNING:NgdBuild:443 - SFF primitive
2124
 
2125
   SIZE2_REG1' has unconnected output pin
2126
 
2127
 
2128
 
2129
WARNING:NgdBuild:443 - SFF primitive
2130
 
2131
   unconnected output pin
2132
 
2133
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected
2134
 
2135
WARNING:NgdBuild:440 - FF primitive
2136
 
2137
   has unconnected output pin
2138
 
2139
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'
2140
 
2141
WARNING:NgdBuild:440 - FF primitive
2142
 
2143
   has unconnected output pin
2144
 
2145
 
2146
 
2147
WARNING:NgdBuild:440 - FF primitive
2148
 
2149
   has unconnected output pin
2150
 
2151
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'
2152
 
2153
WARNING:NgdBuild:440 - FF primitive
2154
 
2155
   has unconnected output pin
2156
 
2157
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'
2158
 
2159
WARNING:NgdBuild:440 - FF primitive
2160
 
2161
   has unconnected output pin
2162
 
2163
 
2164
 
2165
WARNING:NgdBuild:440 - FF primitive
2166
 
2167
   has unconnected output pin
2168
 
2169
 
2170
 
2171
WARNING:NgdBuild:440 - FF primitive
2172
 
2173
 
2174
 
2175
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'
2176
 
2177
WARNING:NgdBuild:440 - FF primitive
2178
 
2179
   has unconnected output pin
2180
 
2181
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'
2182
 
2183
WARNING:NgdBuild:440 - FF primitive
2184
 
2185
   /gen_rden[1].u_calib_rden_r' has unconnected output pin
2186
 
2187
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
2188
 
2189
WARNING:NgdBuild:440 - FF primitive
2190
 
2191
   /gen_rden[3].u_calib_rden_r' has unconnected output pin
2192
 
2193
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
2194
 
2195
WARNING:NgdBuild:440 - FF primitive
2196
 
2197
   /gen_rden[5].u_calib_rden_r' has unconnected output pin
2198
 
2199
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
2200
 
2201
WARNING:NgdBuild:440 - FF primitive
2202
 
2203
   /gen_rden[7].u_calib_rden_r' has unconnected output pin
2204
 
2205
   "clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"
2206
 
2207
WARNING:NgdBuild:452 - logical net 'N194' has no driver
2208
 
2209
WARNING:NgdBuild:452 - logical net 'N196' has no driver
2210
 
2211
WARNING:NgdBuild:452 - logical net 'N198' has no driver
2212
 
2213
WARNING:NgdBuild:452 - logical net 'N200' has no driver
2214
 
2215
WARNING:NgdBuild:452 - logical net 'N202' has no driver
2216
 
2217
WARNING:NgdBuild:452 - logical net 'N204' has no driver
2218
 
2219
WARNING:NgdBuild:452 - logical net 'N206' has no driver
2220
 
2221
WARNING:NgdBuild:452 - logical net 'N208' has no driver
2222
 
2223
WARNING:NgdBuild:452 - logical net 'N210' has no driver
2224
 
2225
WARNING:NgdBuild:452 - logical net 'N212' has no driver
2226
 
2227
WARNING:NgdBuild:452 - logical net 'N214' has no driver
2228
 
2229
WARNING:NgdBuild:452 - logical net 'N216' has no driver
2230
 
2231
WARNING:NgdBuild:452 - logical net 'N218' has no driver
2232
 
2233
WARNING:NgdBuild:452 - logical net 'N220' has no driver
2234
 
2235
WARNING:NgdBuild:452 - logical net 'N222' has no driver
2236
 
2237
WARNING:NgdBuild:452 - logical net 'N224' has no driver
2238
 
2239
WARNING:NgdBuild:452 - logical net 'N226' has no driver
2240
 
2241
WARNING:NgdBuild:452 - logical net 'N228' has no driver
2242
 
2243
WARNING:NgdBuild:452 - logical net 'N230' has no driver
2244
 
2245
WARNING:NgdBuild:452 - logical net 'N232' has no driver
2246
 
2247
WARNING:NgdBuild:452 - logical net 'N234' has no driver
2248
 
2249
WARNING:NgdBuild:452 - logical net 'N236' has no driver
2250
 
2251
WARNING:NgdBuild:452 - logical net 'N238' has no driver
2252
 
2253
WARNING:NgdBuild:452 - logical net 'N240' has no driver
2254
 
2255
WARNING:NgdBuild:452 - logical net 'N242' has no driver
2256
 
2257
WARNING:NgdBuild:452 - logical net 'N244' has no driver
2258
 
2259
WARNING:NgdBuild:452 - logical net 'N246' has no driver
2260
 
2261
WARNING:NgdBuild:452 - logical net 'N248' has no driver
2262
 
2263
WARNING:NgdBuild:452 - logical net 'N250' has no driver
2264
 
2265
WARNING:NgdBuild:452 - logical net 'N252' has no driver
2266
 
2267
WARNING:NgdBuild:452 - logical net 'N254' has no driver
2268
 
2269
WARNING:NgdBuild:452 - logical net 'N256' has no driver
2270
 
2271
WARNING:NgdBuild:452 - logical net 'N266' has no driver
2272
 
2273
WARNING:NgdBuild:452 - logical net 'N268' has no driver
2274
 
2275
WARNING:NgdBuild:452 - logical net 'N270' has no driver
2276
 
2277
WARNING:NgdBuild:452 - logical net 'N272' has no driver
2278
 
2279
WARNING:NgdBuild:452 - logical net 'N306' has no driver
2280
 
2281
WARNING:NgdBuild:452 - logical net 'N308' has no driver
2282
 
2283
WARNING:NgdBuild:452 - logical net 'N310' has no driver
2284
 
2285
WARNING:NgdBuild:452 - logical net 'N312' has no driver
2286
 
2287
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'
2288
 
2289
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'
2290
 
2291
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'
2292
 
2293
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'
2294
 
2295
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'
2296
 
2297
2298
 
2299
-------------------------------
2300
 
2301
  No Partitions were found in this design.
2302
 
2303
-------------------------------
2304
 
2305
NGDBUILD Design Results Summary:
2306
 
2307
  Number of warnings: 348
2308
 
2309
Writing NGD file "system.ngd" ...
2310
 
2311
Total CPU time to NGDBUILD completion:  1 min  28 sec
2312
 
2313
Writing NGDBUILD log file "system.bld"...
2314
 
2315
NGDBUILD done.
2316
 
2317
2318
 
2319
#----------------------------------------------#
2320
 
2321
# map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing
2322
 
2323
#----------------------------------------------#
2324
 
2325
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
2326
 
2327
 with local file
2328
 
2329
Using target part "5vfx70tff1136-1".
2330
 
2331
WARNING:LIT:395 - The above warning message is repeated 1200 more times for the
2332
 
2333
   N195,
2334
 
2335
   N197,
2336
 
2337
   N199
2338
 
2339
Mapping design into LUTs...
2340
 
2341
   connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has
2342
 
2343
WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top
2344
 
2345
WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been
2346
 
2347
Writing file system_map.ngm...
2348
 
2349
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
2350
 
2351
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig
2352
 
2353
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
2354
 
2355
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig
2356
 
2357
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
2358
 
2359
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig
2360
 
2361
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
2362
 
2363
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig
2364
 
2365
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
2366
 
2367
   of frag REGCLKAU connected to power/ground net
2368
 
2369
   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig
2370
 
2371
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
2372
 
2373
   of frag REGCLKAL connected to power/ground net
2374
 
2375
   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig
2376
 
2377
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
2378
 
2379
   of frag REGCLKAU connected to power/ground net
2380
 
2381
   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig
2382
 
2383
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
2384
 
2385
   of frag REGCLKAL connected to power/ground net
2386
 
2387
   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig
2388
 
2389
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
2390
 
2391
   of frag RDRCLKU connected to power/ground net
2392
 
2393
   x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig
2394
 
2395
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
2396
 
2397
   of frag RDRCLKL connected to power/ground net
2398
 
2399
   x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig
2400
 
2401
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
2402
 
2403
   noeccerr.SDP
2404
 
2405
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
2406
 
2407
   noeccerr.SDP_RDRCLKU_tiesig
2408
 
2409
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
2410
 
2411
   noeccerr.SDP
2412
 
2413
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
2414
 
2415
   noeccerr.SDP_RDRCLKL_tiesig
2416
 
2417
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
2418
 
2419
   ram/SDP.WIDE_PRIM36.noeccerr.SDP
2420
 
2421
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
2422
 
2423
   ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
2424
 
2425
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
2426
 
2427
   ram/SDP.WIDE_PRIM36.noeccerr.SDP
2428
 
2429
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
2430
 
2431
   ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
2432
 
2433
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
2434
 
2435
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
2436
 
2437
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
2438
 
2439
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
2440
 
2441
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
2442
 
2443
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
2444
 
2445
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
2446
 
2447
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
2448
 
2449
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
2450
 
2451
   36.noeccerr.SDP
2452
 
2453
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
2454
 
2455
   36.noeccerr.SDP_RDRCLKU_tiesig
2456
 
2457
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
2458
 
2459
   36.noeccerr.SDP
2460
 
2461
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
2462
 
2463
   36.noeccerr.SDP_RDRCLKL_tiesig
2464
 
2465
Running delay-based LUT packing...
2466
 
2467
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM
2468
 
2469
   timing analysis.
2470
 
2471
   (.mrp).
2472
 
2473
Total REAL time at the beginning of Placer: 1 mins 55 secs
2474
 
2475
2476
 
2477
Phase 1.1  Initial Placement Analysis (Checksum:150b88e2) REAL time: 2 mins 13 secs
2478
 
2479
Phase 2.7  Design Feasibility Check
2480
 
2481
   Components associated with this bus are as follows:
2482
 
2483
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6>   IOSTANDARD = LVCMOS25
2484
 
2485
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4>   IOSTANDARD = LVCMOS18
2486
 
2487
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2>   IOSTANDARD = LVCMOS18
2488
 
2489
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0>   IOSTANDARD = LVCMOS18
2490
 
2491
2492
 
2493
   Components associated with this bus are as follows:
2494
 
2495
         Comp: fpga_0_SRAM_Mem_DQ_pin<30>   IOSTANDARD = LVDCI_33
2496
 
2497
         Comp: fpga_0_SRAM_Mem_DQ_pin<28>   IOSTANDARD = LVDCI_33
2498
 
2499
         Comp: fpga_0_SRAM_Mem_DQ_pin<26>   IOSTANDARD = LVDCI_33
2500
 
2501
         Comp: fpga_0_SRAM_Mem_DQ_pin<24>   IOSTANDARD = LVDCI_33
2502
 
2503
         Comp: fpga_0_SRAM_Mem_DQ_pin<22>   IOSTANDARD = LVDCI_33
2504
 
2505
         Comp: fpga_0_SRAM_Mem_DQ_pin<20>   IOSTANDARD = LVDCI_33
2506
 
2507
         Comp: fpga_0_SRAM_Mem_DQ_pin<18>   IOSTANDARD = LVDCI_33
2508
 
2509
         Comp: fpga_0_SRAM_Mem_DQ_pin<16>   IOSTANDARD = LVDCI_33
2510
 
2511
         Comp: fpga_0_SRAM_Mem_DQ_pin<14>   IOSTANDARD = LVCMOS33
2512
 
2513
         Comp: fpga_0_SRAM_Mem_DQ_pin<12>   IOSTANDARD = LVCMOS33
2514
 
2515
         Comp: fpga_0_SRAM_Mem_DQ_pin<10>   IOSTANDARD = LVCMOS33
2516
 
2517
         Comp: fpga_0_SRAM_Mem_DQ_pin<8>   IOSTANDARD = LVCMOS33
2518
 
2519
         Comp: fpga_0_SRAM_Mem_DQ_pin<6>   IOSTANDARD = LVCMOS33
2520
 
2521
         Comp: fpga_0_SRAM_Mem_DQ_pin<4>   IOSTANDARD = LVCMOS33
2522
 
2523
         Comp: fpga_0_SRAM_Mem_DQ_pin<2>   IOSTANDARD = LVCMOS33
2524
 
2525
         Comp: fpga_0_SRAM_Mem_DQ_pin<0>   IOSTANDARD = LVCMOS33
2526
 
2527
2528
 
2529
2530
 
2531
Phase 3.31  Local Placement Optimization (Checksum:f23945c2) REAL time: 2 mins 14 secs
2532
 
2533
Phase 4.37  Local Placement Optimization
2534
 
2535
2536
 
2537
Phase 5.33  Local Placement Optimization (Checksum:f23945c2) REAL time: 8 mins 58 secs
2538
 
2539
Phase 6.32  Local Placement Optimization
2540
 
2541
2542
 
2543
2544
 
2545
2546
 
2547
|------------------------------------------|------------------------------------------|
2548
 
2549
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2550
 
2551
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
2552
 
2553
|                                          |                                          |
2554
 
2555
| CLOCKREGION_X0Y6:                        | CLOCKREGION_X1Y6:                        |
2556
 
2557
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
2558
 
2559
|   0 center BUFIOs available, 0 in use    |                                          |
2560
 
2561
|------------------------------------------|------------------------------------------|
2562
 
2563
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2564
 
2565
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
2566
 
2567
|                                          |                                          |
2568
 
2569
| CLOCKREGION_X0Y4:                        | CLOCKREGION_X1Y4:                        |
2570
 
2571
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
2572
 
2573
|   2 center BUFIOs available, 0 in use    |                                          |
2574
 
2575
|------------------------------------------|------------------------------------------|
2576
 
2577
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2578
 
2579
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
2580
 
2581
|                                          |                                          |
2582
 
2583
| CLOCKREGION_X0Y2:                        | CLOCKREGION_X1Y2:                        |
2584
 
2585
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
2586
 
2587
|   2 center BUFIOs available, 0 in use    |                                          |
2588
 
2589
|------------------------------------------|------------------------------------------|
2590
 
2591
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2592
 
2593
      |
2594
 
2595
|   0 center BUFIOs available, 0 in use    |                                          |
2596
 
2597
|------------------------------------------|------------------------------------------|
2598
 
2599
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
2600
 
2601
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
2602
 
2603
|                                          |                                          |
2604
 
2605
2606
 
2607
Clock-Region: 
2608
 
2609
|-----------------------------------------------------------------------------------------------------------------------------------------------------------
2610
 
2611
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
2612
 
2613
|       | Upper Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region
2614
 
2615
|       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region
2616
 
2617
|       | Lower Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region
2618
 
2619
| clock |    region   |                                                                                      -----------------------------------------------
2620
 
2621
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2622
 
2623
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2624
 
2625
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2626
 
2627
2628
 
2629
  key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4
2630
 
2631
|       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |
2632
 
2633
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2634
 
2635
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2636
 
2637
|-------|-------------|------|-----|----|--------|-------
2638
 
2639
|       | Lower Region|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region
2640
 
2641
| clock |    region   |                                                                                      -----------------------------------------------
2642
 
2643
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2644
 
2645
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2646
 
2647
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2648
 
2649
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2650
 
2651
2652
 
2653
  key resource utilizations (used/available): edge-bufios - 3/4; bufrs - 0/2; regional-clock-spines - 0/4
2654
 
2655
|       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |
2656
 
2657
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2658
 
2659
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2660
 
2661
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2662
 
2663
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2664
 
2665
|  type |  expansion  |                                                                                      | 
2666
 
2667
| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |
2668
 
2669
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2670
 
2671
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2672
 
2673
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
2674
 
2675
2676
 
2677
2678
 
2679
# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:
2680
 
2681
# Number of Regional Clocking Regions in the device: 16  (4 clock spines in each)
2682
 
2683
# composed of up to 3 clock spines and cover up to 3 regional clock regions)
2684
 
2685
######################################################################################
2686
 
2687
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" driven by "BUFIO_X0Y27"
2688
 
2689
"BUFIO_X0Y27" ;
2690
 
2691
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;
2692
 
2693
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;
2694
 
2695
CLOCKREGION_X0Y6;
2696
 
2697
2698
 
2699
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_bufio_dqs" LOC =
2700
 
2701
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" TNM_NET =
2702
 
2703
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" AREA_GROUP =
2704
 
2705
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" RANGE =
2706
 
2707
2708
 
2709
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" driven by "BUFIO_X0Y11"
2710
 
2711
"BUFIO_X0Y11" ;
2712
 
2713
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;
2714
 
2715
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;
2716
 
2717
CLOCKREGION_X0Y2;
2718
 
2719
2720
 
2721
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_bufio_dqs" LOC =
2722
 
2723
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" TNM_NET =
2724
 
2725
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" AREA_GROUP =
2726
 
2727
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" RANGE =
2728
 
2729
2730
 
2731
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" driven by "BUFIO_X0Y25"
2732
 
2733
"BUFIO_X0Y25" ;
2734
 
2735
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;
2736
 
2737
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;
2738
 
2739
CLOCKREGION_X0Y6;
2740
 
2741
2742
 
2743
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_bufio_dqs" LOC =
2744
 
2745
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" TNM_NET =
2746
 
2747
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" AREA_GROUP =
2748
 
2749
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" RANGE =
2750
 
2751
2752
 
2753
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" driven by "BUFIO_X0Y26"
2754
 
2755
"BUFIO_X0Y26" ;
2756
 
2757
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;
2758
 
2759
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;
2760
 
2761
CLOCKREGION_X0Y6;
2762
 
2763
2764
 
2765
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_bufio_dqs" LOC =
2766
 
2767
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" TNM_NET =
2768
 
2769
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" AREA_GROUP =
2770
 
2771
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" RANGE =
2772
 
2773
2774
 
2775
Phase 7.2  Initial Clock and IO Placement (Checksum:7e049af9) REAL time: 9 mins 19 secs
2776
 
2777
Phase 8.36  Local Placement Optimization
2778
 
2779
2780
 
2781
.................
2782
 
2783
......
2784
 
2785
......
2786
 
2787
.....
2788
 
2789
......
2790
 
2791
......
2792
 
2793
.......
2794
 
2795
..
2796
 
2797
2798
 
2799
######################################################################################
2800
 
2801
#
2802
 
2803
# Number of Global Clock Networks: 15
2804
 
2805
# Clock Region Assignment: SUCCESSFUL
2806
 
2807
# Location of Clock Components
2808
 
2809
INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y30" ;
2810
 
2811
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.coreclk_pll_bufg" LOC = "BUFGCTRL_X0Y27" ;
2812
 
2813
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_BUFG_for_CLKFBOUT.CLKFB_BUFG_INST" LOC = "BUFGCTRL_X0Y3" ;
2814
 
2815
INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y8" ;
2816
 
2817
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT3.CLKOUT3_BUFG_INST" LOC = "BUFGCTRL_X0Y4" ;
2818
 
2819
INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y31" ;
2820
 
2821
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT4.CLKOUT4_BUFG_INST" LOC = "BUFGCTRL_X0Y6" ;
2822
 
2823
INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST" LOC = "DCM_ADV_X0Y0" ;
2824
 
2825
INST "fpga_0_clk_1_sys_clk_pin" LOC = "IOB_X1Y109" ;
2826
 
2827
INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" LOC = "IOB_X1Y217" ;
2828
 
2829
INST "fpga_0_PCIe_Bridge_RXN_pin" LOC = "IPAD_X1Y12" ;
2830
 
2831
INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" LOC = "IPAD_X1Y16" ;
2832
 
2833
INST "fpga_0_PCIe_Bridge_TXN_pin" LOC = "OPAD_X0Y8" ;
2834
 
2835
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_adv_i" LOC = "PLL_ADV_X0Y5" ;
2836
 
2837
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = "GTX_DUAL_X0Y2" ;
2838
 
2839
2840
 
2841
NET "clk_125_0000MHzPLL0" TNM_NET = "TN_clk_125_0000MHzPLL0" ;
2842
 
2843
AREA_GROUP "CLKAG_clk_125_0000MHzPLL0" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
2844
 
2845
# fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP driven by BUFGCTRL_X0Y30
2846
 
2847
TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;
2848
 
2849
2850
 
2851
NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;
2852
 
2853
AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;
2854
 
2855
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk driven by BUFGCTRL_X0Y27
2856
 
2857
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;
2858
 
2859
2860
 
2861
NET "clk_125_0000MHzPLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHzPLL0_ADJUST" ;
2862
 
2863
AREA_GROUP "CLKAG_clk_125_0000MHzPLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
2864
 
2865
# clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6> driven by BUFGCTRL_X0Y3
2866
 
2867
TIMEGRP "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" AREA_GROUP = "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;
2868
 
2869
2870
 
2871
NET "PCIe_Bridge/Bridge_Clk" TNM_NET = "TN_PCIe_Bridge/Bridge_Clk" ;
2872
 
2873
AREA_GROUP "CLKAG_PCIe_Bridge/Bridge_Clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
2874
 
2875
# fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP driven by BUFGCTRL_X0Y8
2876
 
2877
TIMEGRP "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;
2878
 
2879
2880
 
2881
NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;
2882
 
2883
AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" RANGE =   CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;
2884
 
2885
# clk_200_0000MHz driven by BUFGCTRL_X0Y4
2886
 
2887
TIMEGRP "TN_clk_200_0000MHz" AREA_GROUP = "CLKAG_clk_200_0000MHz" ;
2888
 
2889
2890
 
2891
NET "fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" TNM_NET = "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;
2892
 
2893
AREA_GROUP "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" RANGE =   CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;
2894
 
2895
# fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP driven by BUFGCTRL_X0Y31
2896
 
2897
TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;
2898
 
2899
2900
 
2901
NET "clk_125_0000MHz90PLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHz90PLL0_ADJUST" ;
2902
 
2903
AREA_GROUP "CLKAG_clk_125_0000MHz90PLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
2904
 
2905
# clk_62_5000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y6
2906
 
2907
TIMEGRP "TN_clk_62_5000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_62_5000MHzPLL0_ADJUST" ;
2908
 
2909
2910
 
2911
NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;
2912
 
2913
AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" RANGE =   CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;
2914
 
2915
# NOTE:
2916
 
2917
# assignments. The report provides range constraints for all global
2918
 
2919
#
2920
 
2921
######################################################################################
2922
 
2923
2924
 
2925
GLOBAL CLOCK NET LOADS DISTRIBUTION REPORT:
2926
 
2927
Number of Global Clock Regions : 16
2928
 
2929
2930
 
2931
2932
 
2933
 key resource utilizations (used/available): global-clocks - 2/10 ;
2934
 
2935
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2936
 
2937
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2938
 
2939
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2940
 
2941
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2942
 
2943
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |    202 |clk_125_0000MHzPLL0_ADJUST
2944
 
2945
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     46 |    750 | Total
2946
 
2947
2948
 
2949
Clock-Region: 
2950
 
2951
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2952
 
2953
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2954
 
2955
      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
2956
 
2957
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2958
 
2959
      4 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |     38 |    934 |PCIe_Bridge/Bridge_Clk
2960
 
2961
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2962
 
2963
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2964
 
2965
2966
 
2967
 key resource utilizations (used/available): global-clocks - 6/10 ;
2968
 
2969
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
2970
 
2971
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2972
 
2973
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2974
 
2975
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2976
 
2977
      0 |      0 |      0 |      0 |      0 |     18 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |clk_125_0000MHz90PLL0_ADJUST
2978
 
2979
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz
2980
 
2981
      0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>
2982
 
2983
      0 |      1 |      1 |      0 |      0 |     35 |      0 |      0 |      0 |      0 |      1 |      0 |     17 |    918 | Total
2984
 
2985
2986
 
2987
Clock-Region: 
2988
 
2989
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
2990
 
2991
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
2992
 
2993
      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
2994
 
2995
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
2996
 
2997
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      6 |    500 |PCIe_Bridge/Bridge_Clk
2998
 
2999
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     11 |    364 |clk_125_0000MHzPLL0_ADJUST
3000
 
3001
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3002
 
3003
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3004
 
3005
3006
 
3007
 key resource utilizations (used/available): global-clocks - 5/10 ;
3008
 
3009
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
3010
 
3011
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3012
 
3013
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3014
 
3015
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3016
 
3017
      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     17 |clk_125_0000MHz90PLL0_ADJUST
3018
 
3019
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz
3020
 
3021
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3022
 
3023
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3024
 
3025
3026
 
3027
 key resource utilizations (used/available): global-clocks - 4/10 ;
3028
 
3029
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
3030
 
3031
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3032
 
3033
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3034
 
3035
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3036
 
3037
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     81 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
3038
 
3039
      0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     36 |    500 |clk_125_0000MHzPLL0_ADJUST
3040
 
3041
      0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |    130 |    970 | Total
3042
 
3043
3044
 
3045
Clock-Region: 
3046
 
3047
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3048
 
3049
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
3050
 
3051
      4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)
3052
 
3053
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
3054
 
3055
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     83 |clk_125_0000MHz90PLL0_ADJUST
3056
 
3057
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      3 |clk_200_0000MHz
3058
 
3059
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3060
 
3061
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3062
 
3063
3064
 
3065
 key resource utilizations (used/available): global-clocks - 3/10 ;
3066
 
3067
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
3068
 
3069
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3070
 
3071
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3072
 
3073
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3074
 
3075
      6 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     22 |    659 |clk_125_0000MHzPLL0_ADJUST
3076
 
3077
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3078
 
3079
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3080
 
3081
3082
 
3083
 key resource utilizations (used/available): global-clocks - 5/10 ;
3084
 
3085
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
3086
 
3087
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3088
 
3089
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3090
 
3091
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3092
 
3093
      2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     34 |clk_125_0000MHz90PLL0_ADJUST
3094
 
3095
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    200 |clk_62_5000MHzPLL0_ADJUST
3096
 
3097
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3098
 
3099
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3100
 
3101
3102
 
3103
 key resource utilizations (used/available): global-clocks - 3/10 ;
3104
 
3105
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
3106
 
3107
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3108
 
3109
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3110
 
3111
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3112
 
3113
      3 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |    602 |clk_125_0000MHzPLL0_ADJUST
3114
 
3115
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3116
 
3117
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3118
 
3119
3120
 
3121
 key resource utilizations (used/available): global-clocks - 4/10 ;
3122
 
3123
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
3124
 
3125
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3126
 
3127
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3128
 
3129
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3130
 
3131
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     48 |clk_125_0000MHz90PLL0_ADJUST
3132
 
3133
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      8 |    206 |clk_62_5000MHzPLL0_ADJUST
3134
 
3135
      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |     28 |    773 | Total
3136
 
3137
3138
 
3139
Clock-Region: 
3140
 
3141
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3142
 
3143
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
3144
 
3145
     10 |      0 |      0 |      0 |     40 |     40 |     16 |      1 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
3146
 
3147
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
3148
 
3149
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     68 |    285 |PCIe_Bridge/Bridge_Clk
3150
 
3151
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     21 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP
3152
 
3153
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    118 |    639 | Total
3154
 
3155
3156
 
3157
Clock-Region: 
3158
 
3159
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3160
 
3161
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
3162
 
3163
     12 |      4 |      2 |      0 |     40 |     40 |      0 |      0 |      0 |      0 |      1 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
3164
 
3165
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
3166
 
3167
      0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg
3168
 
3169
      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |clk_125_0000MHz90PLL0_ADJUST
3170
 
3171
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz
3172
 
3173
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     15 |     12 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP
3174
 
3175
      0 |      0 |      2 |      0 |      0 |     35 |      0 |      0 |      0 |      0 |      1 |      0 |     27 |    777 | Total
3176
 
3177
3178
 
3179
Clock-Region: 
3180
 
3181
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3182
 
3183
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
3184
 
3185
      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
3186
 
3187
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
3188
 
3189
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      4 |    103 |PCIe_Bridge/Bridge_Clk
3190
 
3191
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3192
 
3193
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3194
 
3195
3196
 
3197
 key resource utilizations (used/available): global-clocks - 2/10 ;
3198
 
3199
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
3200
 
3201
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3202
 
3203
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3204
 
3205
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3206
 
3207
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     19 |clk_62_5000MHzPLL0_ADJUST
3208
 
3209
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     16 |    514 | Total
3210
 
3211
3212
 
3213
Clock-Region: 
3214
 
3215
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
3216
 
3217
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
3218
 
3219
      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
3220
 
3221
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
3222
 
3223
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     46 |    327 |clk_125_0000MHzPLL0_ADJUST
3224
 
3225
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     46 |    327 | Total
3226
 
3227
3228
 
3229
The above detailed report is the initial placement of the logic after the clock region assignment. The final placement
3230
 
3231
maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.
3232
 
3233
3234
 
3235
######################################################################################
3236
 
3237
3238
 
3239
3240
 
3241
Phase 10.3  Local Placement Optimization (Checksum:7e049af9) REAL time: 10 mins 43 secs
3242
 
3243
Phase 11.5  Local Placement Optimization
3244
 
3245
3246
 
3247
.............................
3248
 
3249
.
3250
 
3251
.....
3252
 
3253
.......
3254
 
3255
......
3256
 
3257
........
3258
 
3259
.........
3260
 
3261
.........
3262
 
3263
.......
3264
 
3265
........
3266
 
3267
.........
3268
 
3269
.........
3270
 
3271
.
3272
 
3273
.....
3274
 
3275
.
3276
 
3277
...
3278
 
3279
......
3280
 
3281
......
3282
 
3283
.......
3284
 
3285
....
3286
 
3287
......
3288
 
3289
......
3290
 
3291
......
3292
 
3293
....
3294
 
3295
....
3296
 
3297
......
3298
 
3299
...
3300
 
3301
.........
3302
 
3303
.
3304
 
3305
..
3306
 
3307
.......
3308
 
3309
.....
3310
 
3311
.....
3312
 
3313
......
3314
 
3315
.....
3316
 
3317
.....
3318
 
3319
.....
3320
 
3321
..
3322
 
3323
.......
3324
 
3325
........
3326
 
3327
Phase 12.8  Global Placement (Checksum:4ba01660) REAL time: 15 mins 18 secs
3328
 
3329
Phase 13.29  Local Placement Optimization
3330
 
3331
3332
 
3333
Phase 14.5  Local Placement Optimization (Checksum:4ba01660) REAL time: 15 mins 22 secs
3334
 
3335
Phase 15.18  Placement Optimization
3336
 
3337
3338
 
3339
Phase 16.5  Local Placement Optimization (Checksum:f81b02a1) REAL time: 18 mins 3 secs
3340
 
3341
Phase 17.34  Placement Validation
3342
 
3343
3344
 
3345
Total CPU  time to Placer completion: 17 mins 4 secs
3346
 
3347
Writing output files...
3348
 
3349
Design Summary:
3350
 
3351
Number of warnings:   50
3352
 
3353
  Number of Slice Registers:                12,128 out of  44,800   27%
3354
 
3355
    Number used as Latches:                      1
3356
 
3357
    Number used as logic:                   11,767 out of  44,800   26%
3358
 
3359
      Number using O5 output only:             282
3360
 
3361
    Number used as Memory:                     392 out of  13,120    2%
3362
 
3363
        Number using O6 output only:            12
3364
 
3365
      Number used as Single Port RAM:            4
3366
 
3367
      Number used as Shift Register:           332
3368
 
3369
    Number used as exclusive route-thru:       107
3370
 
3371
    Number using O6 output only:               382
3372
 
3373
    Number using O5 and O6:                      5
3374
 
3375
Slice Logic Distribution:
3376
 
3377
  Number of LUT Flip Flop pairs used:       17,046
3378
 
3379
    Number with an unused LUT:               4,780 out of  17,046   28%
3380
 
3381
    Number of unique control sets:           1,288
3382
 
3383
      to control set restrictions:           3,000 out of  44,800    6%
3384
 
3385
  A LUT Flip Flop pair for this architecture represents one LUT paired with
3386
 
3387
  clock, reset, set, and enable signals for a registered element.
3388
 
3389
  over-mapped for a non-slice resource or if Placement fails.
3390
 
3391
  over-mapped for a non-BRAM resource or if placement fails.
3392
 
3393
IO Utilization:
3394
 
3395
    Number of LOCed IOBs:                      255 out of     255  100%
3396
 
3397
    Number of bonded IPADs:                      4 out of      50    8%
3398
 
3399
3400
 
3401
  Number of BlockRAM/FIFO:                      23 out of     148   15%
3402
 
3403
    Number using FIFO only:                      2
3404
 
3405
      Number of 36k BlockRAM used:              16
3406
 
3407
      Number of 36k FIFO used:                   2
3408
 
3409
  Number of BUFG/BUFGCTRLs:                     15 out of      32   46%
3410
 
3411
  Number of IDELAYCTRLs:                         3 out of      22   13%
3412
 
3413
  Number of BUFIOs:                              8 out of      80   10%
3414
 
3415
  Number of GTX_DUALs:                           1 out of       8   12%
3416
 
3417
    Number of LOCed PCIEs:                       1 out of       1  100%
3418
 
3419
  Number of PPC440s:                             1 out of       1  100%
3420
 
3421
  Number of RPM macros:           64
3422
 
3423
3424
 
3425
Total REAL time to MAP completion:  18 mins 45 secs
3426
 
3427
3428
 
3429
See MAP report file "system_map.mrp" for details.
3430
 
3431
3432
 
3433
#----------------------------------------------#
3434
 
3435
# par -ise ../__xps/ise/system.ise -w -ol high system_map.ncd system.ncd
3436
 
3437
#----------------------------------------------#
3438
 
3439
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
3440
 
3441
3442
 
3443
3444
 
3445
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
3446
 
3447
3448
 
3449
   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
3450
 
3451
   overrides constraint  [system.pcf(65972)].
3452
 
3453
3454
 
3455
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
3456
 
3457
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP
3458
 
3459
INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please
3460
 
3461
3462
 
3463
3464
 
3465
3466
 
3467
3468
 
3469
   Number of BUFGs                          15 out of 32     46%
3470
 
3471
   Number of DCM_ADVs                        1 out of 12      8%
3472
 
3473
      Number of LOCed FIFO36_72_EXPs         2 out of 2     100%
3474
 
3475
   Number of GTX_DUALs                       1 out of 8      12%
3476
 
3477
      Number of LOCed IDELAYCTRLs            3 out of 3     100%
3478
 
3479
   Number of ILOGICs                       131 out of 800    16%
3480
 
3481
3482
 
3483
      Number of LOCed IOBs                 255 out of 255   100%
3484
 
3485
   Number of IODELAYs                       80 out of 800    10%
3486
 
3487
3488
 
3489
      Number of LOCed IPADs                  4 out of 4     100%
3490
 
3491
   Number of JTAGPPCs                        1 out of 1     100%
3492
 
3493
   Number of External OPADs                  2 out of 32      6%
3494
 
3495
3496
 
3497
      Number of LOCed PCIEs                  1 out of 1     100%
3498
 
3499
   Number of PLL_ADVs                        2 out of 6      33%
3500
 
3501
   Number of RAMB18X2SDPs                    5 out of 148     3%
3502
 
3503
      Number of LOCed RAMB36SDP_EXPs         1 out of 6      16%
3504
 
3505
   Number of RAMB36_EXPs                    10 out of 148     6%
3506
 
3507
3508
 
3509
      Number used as Flip Flops          12127
3510
 
3511
      Number used as LatchThrus              0
3512
 
3513
   Number of Slice LUTS                  12266 out of 44800  27%
3514
 
3515
3516
 
3517
Overall effort level (-ol):   High
3518
 
3519
3520
 
3521
Finished initial Timing Analysis.  REAL time: 52 secs
3522
 
3523
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0> has no load.  PAR will not attempt to route this
3524
 
3525
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0> has no load.  PAR will not attempt to route this
3526
 
3527
WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<30> has no load.  PAR will not attempt to route this
3528
 
3529
WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<31> has no load.  PAR will not attempt to route this
3530
 
3531
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull has no load.  PAR will not attempt to route this
3532
 
3533
Starting Router
3534
 
3535
INFO:Route:501 - One or more directed routing (DIRT) constraints generated for a specific device have been found. Note
3536
 
3537
   verify that the same connectivity is available in the target device for this implementation.
3538
 
3539
Phase  1  : 82160 unrouted;      REAL time: 1 mins 9 secs
3540
 
3541
Phase  2  : 72970 unrouted;      REAL time: 1 mins 22 secs
3542
 
3543
Phase  3  : 28783 unrouted;      REAL time: 3 mins 31 secs
3544
 
3545
Phase  4  : 28815 unrouted; (Setup:0, Hold:103206, Component Switching Limit:0)     REAL time: 3 mins 57 secs
3546
 
3547
Updating file: system.ncd with current fully routed design.
3548
 
3549
Phase  5  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs
3550
 
3551
Phase  6  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs
3552
 
3553
Phase  7  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs
3554
 
3555
Phase  8  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs
3556
 
3557
Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 7 mins 25 secs
3558
 
3559
Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 7 mins 57 secs
3560
 
3561
Total CPU time to Router completion: 7 mins 31 secs
3562
 
3563
Partition Implementation Status
3564
 
3565
3566
 
3567
3568
 
3569
3570
 
3571
3572
 
3573
Generating Clock Report
3574
 
3575
3576
 
3577
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
3578
 
3579
|clk_125_0000MHzPLL0_ |              |      |      |            |             |
3580
 
3581
+---------------------+--------------+------+------+------------+-------------+
3582
 
3583
|                  lk |BUFGCTRL_X0Y28| No   | 1481 |  0.519     |  2.085      |
3584
 
3585
|clk_62_5000MHzPLL0_A |              |      |      |            |             |
3586
 
3587
+---------------------+--------------+------+------+------------+-------------+
3588
 
3589
|            0_ADJUST | BUFGCTRL_X0Y5| No   |  165 |  0.262     |  2.028      |
3590
 
3591
|PCIe_Bridge/PCIe_Bri |              |      |      |            |             |
3592
 
3593
|comp_endpoint/core_c |              |      |      |            |             |
3594
 
3595
+---------------------+--------------+------+------+------------+-------------+
3596
 
3597
|tFlash_SysACE_CLK_pi |              |      |      |            |             |
3598
 
3599
+---------------------+--------------+------+------+------------+-------------+
3600
 
3601
|dge/comp_block_plus/ |              |      |      |            |             |
3602
 
3603
|        lk/gt_usrclk |BUFGCTRL_X0Y29| No   |    6 |  0.065     |  1.886      |
3604
 
3605
|fpga_0_Ethernet_MAC_ |              |      |      |            |             |
3606
 
3607
|                     |BUFGCTRL_X0Y30| No   |   12 |  0.086     |  1.874      |
3608
 
3609
|fpga_0_Ethernet_MAC_ |              |      |      |            |             |
3610
 
3611
|                     |BUFGCTRL_X0Y31| No   |    6 |  0.004     |  1.941      |
3612
 
3613
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
3614
 
3615
|f_top/u_phy_top/u_ph |              |      |      |            |             |
3616
 
3617
+---------------------+--------------+------+------+------------+-------------+
3618
 
3619
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
3620
 
3621
| y_io/delayed_dqs<1> |        IO Clk| No   |   18 |  0.083     |  0.380      |
3622
 
3623
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
3624
 
3625
|f_top/u_phy_top/u_ph |              |      |
3626
 
3627
| y_io/delayed_dqs<2> |        IO Clk| No   |   18 |  0.101     |  0.425      |
3628
 
3629
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
3630
 
3631
|f_top/u_phy_top/u_ph |              |      |      |            |             |
3632
 
3633
+---------------------+--------------+------+------+------------+-------------+
3634
 
3635
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
3636
 
3637
| y_io/delayed_dqs<5> |        IO Clk| No   |   18 |  0.101     |  0.425      |
3638
 
3639
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
3640
 
3641
|f_top/u_phy_top/u_ph |              |      |      |            |             |
3642
 
3643
+---------------------+--------------+------+------+------------+-------------+
3644
 
3645
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
3646
 
3647
| y_io/delayed_dqs<6> |        IO Clk| No   |   18 |  0.096     |  0.393      |
3648
 
3649
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
3650
 
3651
|f_top/u_phy_top/u_ph |              |      |      |            |             |
3652
 
3653
+---------------------+--------------+------+------+------------+-------------+
3654
 
3655
+---------------------+--------------+------+------+------------+-------------+
3656
 
3657
+---------------------+--------------+------+------+------------+-------------+
3658
 
3659
|                  pt |         Local|      |    1 |  0.000     |  0.625      |
3660
 
3661
|PCIe_Bridge/PCIe_Bri |              |      |      |            |             |
3662
 
3663
|comp_endpoint/pcie_b |              |      |      |            |             |
3664
 
3665
|  per_i/icdrreset<0> |         Local|      |    1 |  0.000     |  0.590      |
3666
 
3667
|Ethernet_MAC/Etherne |              |      |      |            |             |
3668
 
3669
+---------------------+--------------+------+------+------------+-------------+
3670
 
3671
|         _JTGC405TCK |         Local|      |    1 |  0.000     |  1.699      |
3672
 
3673
3674
 
3675
only delays for the net. Note this is different from Clock Skew which
3676
 
3677
the minimum and maximum path delays which includes logic delays.
3678
 
3679
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
3680
 
3681
Number of Timing Constraints that were not applied: 5
3682
 
3683
Asterisk (*) preceding a constraint indicates it was not met.
3684
 
3685
3686
 
3687
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
3688
 
3689
----------------------------------------------------------------------------------------------------------
3690
 
3691
  s HIGH 50%                                | HOLD        |     0.030ns|            |       0|           0
3692
 
3693
------------------------------------------------------------------------------------------------------
3694
 
3695
  lus/comp_endpoint/core_clk" PERIOD =      | HOLD        |     0.315ns|            |       0|           0
3696
 
3697
------------------------------------------------------------------------------------------------------
3698
 
3699
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
3700
 
3701
  DELAY = 0.85 ns                           |             |            |            |        |
3702
 
3703
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.015ns|     0.835ns|       0|           0
3704
 
3705
  dqs[0].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
3706
 
3707
------------------------------------------------------------------------------------------------------
3708
 
3709
  CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS"       | HOLD        |     1.026ns|            |       0|           0
3710
 
3711
------------------------------------------------------------------------------------------------------
3712
 
3713
  L0_CLK_OUT_2_ = PERIOD TIMEGRP         "c | HOLD        |     0.021ns|            |       0|           0
3714
 
3715
  LK_OUT_2_" TS_sys_clk_pin *         1.25  |             |            |            |        |
3716
 
3717
------------------------------------------------------------------------------------------------------
3718
 
3719
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
3720
 
3721
  DELAY = 0.85 ns                           |             |            |            |        |
3722
 
3723
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0
3724
 
3725
  dqs[5].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
3726
 
3727
------------------------------------------------------------------------------------------------------
3728
 
3729
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
3730
 
3731
  DELAY = 0.85 ns                           |             |            |            |        |
3732
 
3733
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0
3734
 
3735
  dqs[3].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
3736
 
3737
------------------------------------------------------------------------------------------------------
3738
 
3739
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
3740
 
3741
  DELAY = 0.85 ns                           |             |            |            |        |
3742
 
3743
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0
3744
 
3745
  dqs[6].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
3746
 
3747
------------------------------------------------------------------------------------------------------
3748
 
3749
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3750
 
3751
------------------------------------------------------------------------------------------------------
3752
 
3753
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3754
 
3755
------------------------------------------------------------------------------------------------------
3756
 
3757
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3758
 
3759
------------------------------------------------------------------------------------------------------
3760
 
3761
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3762
 
3763
------------------------------------------------------------------------------------------------------
3764
 
3765
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3766
 
3767
------------------------------------------------------------------------------------------------------
3768
 
3769
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3770
 
3771
------------------------------------------------------------------------------------------------------
3772
 
3773
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3774
 
3775
------------------------------------------------------------------------------------------------------
3776
 
3777
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
3778
 
3779
------------------------------------------------------------------------------------------------------
3780
 
3781
  ge_Clk" TO TIMEGRP "SPLB_Clk" 8 ns        | HOLD        |     0.516ns|            |       0|           0
3782
 
3783
------------------------------------------------------------------------------------------------------
3784
 
3785
  HIGH 50%                                  |             |            |            |        |
3786
 
3787
  TS_PLB_PCIe = MAXDELAY FROM TIMEGRP "SPLB | SETUP       |     1.252ns|     6.748ns|       0|           0
3788
 
3789
    DATAPATHONLY                            |             |            |            |        |
3790
 
3791
  TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | MAXDELAY    |     1.700ns|     4.300ns|       0|           0
3792
 
3793
  thernet_MAC" 6 ns                         |             |            |            |        |
3794
 
3795
  TS_clock_generator_0_clock_generator_0_PL | SETUP       |     2.073ns|     5.466ns|       0|           0
3796
 
3797
  lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |
3798
 
3799
  PHASE 2 ns HIGH 50%                       |             |            |            |        |
3800
 
3801
  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |     6.000ns|     4.000ns|       0|           0
3802
 
3803
------------------------------------------------------------------------------------------------------
3804
 
3805
  L0_CLK_OUT_4_ = PERIOD TIMEGRP         "c | HOLD        |     0.153ns|            |       0|           0
3806
 
3807
  LK_OUT_4_" TS_sys_clk_pin *         0.625 |             |            |            |        |
3808
 
3809
------------------------------------------------------------------------------------------------------
3810
 
3811
  L0_CLK_OUT_3_ = PERIOD TIMEGRP         "c | HOLD        |     0.465ns|            |       0|           0
3812
 
3813
  LK_OUT_3_" TS_sys_clk_pin *         2 HIG |             |            |            |        |
3814
 
3815
------------------------------------------------------------------------------------------------------
3816
 
3817
  UFGP" MAXSKEW = 5 ns                      |             |            |            |        |
3818
 
3819
  NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW     |     4.789ns|     0.211ns|       0|           0
3820
 
3821
------------------------------------------------------------------------------------------------------
3822
 
3823
  L0_CLK_OUT_1_ = PERIOD TIMEGRP         "c |             |            |            |        |
3824
 
3825
  LK_OUT_1_" TS_sys_clk_pin *         1.25  |             |            |            |        |
3826
 
3827
------------------------------------------------------------------------------------------------------
3828
 
3829
  GRP "TXCLK_GRP_Ethernet_MAC" TO         T |             |            |            |        |
3830
 
3831
------------------------------------------------------------------------------------------------------
3832
 
3833
  UFGP" PERIOD = 40 ns HIGH 14 ns           | HOLD        |     0.473ns|            |       0|           0
3834
 
3835
  TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FRO | SETUP       |    13.832ns|     6.168ns|       0|           0
3836
 
3837
      TIMEGRP "TNM_CLK90" TS_MC_CLK * 4     |             |            |            |        |
3838
 
3839
  TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM | SETUP       |    16.202ns|     3.798ns|       0|           0
3840
 
3841
     TIMEGRP "TNM_CLK0" TS_MC_CLK * 4       |             |            |            |        |
3842
 
3843
  TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    17.943ns|     2.057ns|       0|           0
3844
 
3845
    TS_MC_CLK * 4                           |             |            |            |        |
3846
 
3847
  TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    17.975ns|     2.025ns|       0|           0
3848
 
3849
    TS_MC_CLK * 4                           |             |            |            |        |
3850
 
3851
  TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGR | SETUP       |    18.085ns|     1.915ns|       0|           0
3852
 
3853
  TNM_CLK0" TS_MC_CLK * 4                   |             |            |            |        |
3854
 
3855
  NET "fpga_0_SysACE_CompactFlash_SysACE_CL | SETUP       |    26.710ns|     3.290ns|       0|           0
3856
 
3857
   HIGH 50%                                 |             |            |            |        |
3858
 
3859
  NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP       |    32.431ns|     7.569ns|       0|           0
3860
 
3861
------------------------------------------------------------------------------------------------------
3862
 
3863
------------------------------------------------------------------------------------------------------
3864
 
3865
  P "TNM_RDEN_SEL_MUX" TO TIMEGRP         " |             |            |            |        |
3866
 
3867
------------------------------------------------------------------------------------------------------
3868
 
3869
  s HIGH 50%                                |             |            |            |        |
3870
 
3871
3872
 
3873
Derived Constraint Report
3874
 
3875
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
3876
 
3877
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
3878
 
3879
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
3880
 
3881
| TS_MC_PHY_INIT_DATA_SEL_0     |     20.000ns|      3.798ns|          N/A|            0|            0|           21|            0|
3882
 
3883
| TS_MC_GATE_DLY                |     20.000ns|      2.025ns|          N/A|            0|            0|           40|            0|
3884
 
3885
| TS_MC_CAL_RDEN_DLY            |     20.000ns|      1.915ns|          N/A|            0|            0|            5|            0|
3886
 
3887
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
3888
 
3889
Derived Constraints for TS_sys_clk_pin
3890
 
3891
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
3892
 
3893
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
3894
 
3895
|TS_sys_clk_pin                 |     10.000ns|      4.000ns|      9.966ns|            0|            0|            0|       636358|
3896
 
3897
| erator_0_PLL0_CLK_OUT_0_      |             |             |             |             |             |             |             |
3898
 
3899
| erator_0_PLL0_CLK_OUT_1_      |             |             |             |             |             |             |             |
3900
 
3901
| erator_0_PLL0_CLK_OUT_2_      |             |             |             |             |             |             |             |
3902
 
3903
| erator_0_PLL0_CLK_OUT_3_      |             |             |             |             |             |             |             |
3904
 
3905
| erator_0_PLL0_CLK_OUT_4_      |             |             |             |             |             |             |             |
3906
 
3907
3908
 
3909
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
3910
 
3911
3912
 
3913
Generating Pad Report.
3914
 
3915
All signals are completely routed.
3916
 
3917
WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
3918
 
3919
Loading device for application Rf_Device from file '5vlx50t.nph' in environment
3920
 
3921
INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 128
3922
 
3923
   found: 128, number successful: 128
3924
 
3925
Total CPU time to PAR completion: 8 mins 19 secs
3926
 
3927
Peak Memory Usage:  653 MB
3928
 
3929
Placer: Placement generated during map.
3930
 
3931
Timing: Completed - No errors found.
3932
 
3933
Number of error messages: 0
3934
 
3935
Number of info messages: 4
3936
 
3937
Writing design to file system.ncd
3938
 
3939
3940
 
3941
PAR done!
3942
 
3943
3944
 
3945
#----------------------------------------------#
3946
 
3947
# trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf
3948
 
3949
Release 11.2 - Trace  (nt)
3950
 
3951
3952
 
3953
PMSPEC -- Overriding Xilinx file
3954
 
3955
3956
 
3957
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
3958
 
3959
WARNING:ConstraintSystem:65 - Constraint 
3960
 
3961
   "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)].
3962
 
3963
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM
3964
 
3965
   ignored during timing analysis.
3966
 
3967
   information, see the TSI report.  Please consult the Xilinx Command Line
3968
 
3969
--------------------------------------------------------------------------------
3970
 
3971
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
3972
 
3973
trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf
3974
 
3975
3976
 
3977
Physical constraint file: system.pcf
3978
 
3979
level 0)
3980
 
3981
--------------------------------------------------------------------------------
3982
 
3983
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
3984
 
3985
   unconstrained paths section(s) of the report.
3986
 
3987
   50 Ohm transmission line loading model.  For the details of this model, and
3988
 
3989
   see the device datasheet.
3990
 
3991
3992
 
3993
---------------
3994
 
3995
Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)
3996
 
3997
Constraints cover 826342 paths, 18 nets, and 74598 connections
3998
 
3999
Design statistics:
4000
 
4001
   Maximum path delay from/to any node:   7.812ns
4002
 
4003
   Maximum net skew:   0.608ns
4004
 
4005
4006
 
4007
--------------------------------------------------------------------------------
4008
 
4009
Generating Report ...
4010
 
4011
Number of warnings: 2
4012
 
4013
Total time: 1 mins 36 secs
4014
 
4015
4016
 
4017
touch __xps/system_routed
4018
 
4019
Analyzing implementation/system.par
4020
 
4021
Running Bitgen..
4022
 
4023
cd implementation; bitgen -w -f bitgen.ut system; cd ..
4024
 
4025
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
4026
 
4027
 with local file
4028
 
4029
Loading device for application Rf_Device from file '5vfx70t.nph' in environment
4030
 
4031
   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
4032
 
4033
4034
 
4035
4036
 
4037
WARNING:PhysDesignRules:1842 - One or more GTXs are being used in this design.
4038
 
4039
   Transceiver User Guide to ensure that the design SelectIO usage meets the
4040
 
4041
WARNING:PhysDesignRules:372 - Gated clock. Clock net
4042
 
4043
   rapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not good
4044
 
4045
   flip-flop.
4046
 
4047
   Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.
4048
 
4049
   data into the flip-flop.
4050
 
4051
   > is incomplete. The signal does
4052
 
4053
WARNING:PhysDesignRules:367 - The signal
4054
 
4055
   drive any load pins in the design.
4056
 
4057
   > is incomplete. The signal does not
4058
 
4059
WARNING:PhysDesignRules:367 - The signal
4060
 
4061
   drive any load pins in the design.
4062
 
4063
   is incomplete. The signal does not drive any load pins in the design.
4064
 
4065
   block:
4066
 
4067
   used.
4068
 
4069
   block:
4070
 
4071
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
4072
 
4073
   block:
4074
 
4075
   used.
4076
 
4077
   block:
4078
 
4079
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
4080
 
4081
   block:
4082
 
4083
   used.
4084
 
4085
   block:
4086
 
4087
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
4088
 
4089
   block:
4090
 
4091
   used.
4092
 
4093
   block:
4094
 
4095
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
4096
 
4097
   block:
4098
 
4099
   used.
4100
 
4101
   block:
4102
 
4103
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
4104
 
4105
   block:
4106
 
4107
   used.
4108
 
4109
   block:
4110
 
4111
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
4112
 
4113
   block:
4114
 
4115
   used.
4116
 
4117
   block:
4118
 
4119
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
4120
 
4121
   block:
4122
 
4123
   used.
4124
 
4125
   block:
4126
 
4127
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
4128
 
4129
individual error or warning messages for more details.
4130
 
4131
Saving bit stream in "system.bit".
4132
 
4133
4134
 
4135
Done!
4136
 
4137
Writing filter settings....
4138
 
4139
Done writing filter settings to:
4140
 
4141
4142
 
4143
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
4144
 
4145
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
4146
 
4147
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
4148
 
4149
Generating Block Diagram to Buffer
4150
 
4151
Generated Block Diagram SVG
4152
 
4153
At Local date and time: Sat Jul 04 20:43:06 2009
4154
 
4155
4156
 
4157
*********************************************
4158
 
4159
*********************************************
4160
 
4161
-bt implementation/system.bit -o implementation/download.bit
4162
 
4163
bitinit version Xilinx EDK 11.2 Build EDK_LS3.47
4164
 
4165
4166
 
4167
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
4168
 
4169
   251 - deprecated core for architecture 'virtex5fx'!
4170
 
4171
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
4172
 
4173
4174
 
4175
4176
 
4177
4178
 
4179
Address Map for Processor ppc440_0
4180
 
4181
  (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC
4182
 
4183
  (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0
4184
 
4185
  (0x81440000-0x8144ffff) LEDs_8Bit     plb_v46_0
4186
 
4187
  (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0
4188
 
4189
  (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0
4190
 
4191
  (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0
4192
 
4193
  (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0
4194
 
4195
  (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0
4196
 
4197
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
4198
 
4199
   C_SPLB0_P2P value to 0
4200
 
4201
Computing clock values...
4202
 
4203
   'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be
4204
 
4205
   through the clock generator IP.
4206
 
4207
INFO:EDK:1432 - Frequency for Top-Level Input Clock
4208
 
4209
   performed for IPs connected to that clock port, unless they are connected
4210
 
4211
4212
 
4213
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4214
 
4215
   C_PLBV46_NUM_MASTERS value to 1
4216
 
4217
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4218
 
4219
   C_PLBV46_NUM_SLAVES value to 12
4220
 
4221
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4222
 
4223
   C_PLBV46_MID_WIDTH value to 1
4224
 
4225
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4226
 
4227
   value to 128
4228
 
4229
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
4230
 
4231
   PARAMETER C_SPLB_DWIDTH value to 128
4232
 
4233
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
4234
 
4235
   PARAMETER C_SPLB_NUM_MASTERS value to 1
4236
 
4237
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
4238
 
4239
   PARAMETER C_SPLB_SMALLEST_MASTER value to 128
4240
 
4241
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
4242
 
4243
   value to 0x2000
4244
 
4245
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
4246
 
4247
   C_PORT_DWIDTH value to 64
4248
 
4249
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
4250
 
4251
   value to 8
4252
 
4253
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01
4254
 
4255
   C_SPLB_DWIDTH value to 128
4256
 
4257
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
4258
 
4259
   value to 128
4260
 
4261
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
4262
 
4263
   value to 128
4264
 
4265
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
4266
 
4267
   value to 128
4268
 
4269
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
4270
 
4271
   value to 128
4272
 
4273
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
4274
 
4275
   value to 128
4276
 
4277
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
4278
 
4279
   C_SPLB_DWIDTH value to 128
4280
 
4281
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
4282
 
4283
   C_SPLB_SMALLEST_MASTER value to 128
4284
 
4285
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
4286
 
4287
   C_MPLB_DWIDTH value to 128
4288
 
4289
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
4290
 
4291
   C_MPLB_SMALLEST_SLAVE value to 128
4292
 
4293
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
4294
 
4295
   C_SPLB_MID_WIDTH value to 1
4296
 
4297
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
4298
 
4299
   C_SPLB_NUM_MASTERS value to 1
4300
 
4301
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
4302
 
4303
   C_SPLB_SMALLEST_MASTER value to 128
4304
 
4305
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
4306
 
4307
   C_SPLB_DWIDTH value to 128
4308
 
4309
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4310
 
4311
   C_PLBV46_NUM_MASTERS value to 1
4312
 
4313
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4314
 
4315
   C_PLBV46_NUM_SLAVES value to 1
4316
 
4317
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4318
 
4319
   C_PLBV46_MID_WIDTH value to 1
4320
 
4321
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
4322
 
4323
   value to 128
4324
 
4325
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
4326
 
4327
   PARAMETER C_SPLB_DWIDTH value to 128
4328
 
4329
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
4330
 
4331
   C_SPLB_DWIDTH value to 128
4332
 
4333
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
4334
 
4335
   C_SPLB_MID_WIDTH value to 1
4336
 
4337
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
4338
 
4339
   C_SPLB_NUM_MASTERS value to 1
4340
 
4341
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
4342
 
4343
   value to 128
4344
 
4345
Checking platform address map ...
4346
 
4347
Initializing Memory...
4348
 
4349
data2mem -bm "implementation/system_bd" -bt "implementation/system.bit"  -bd
4350
 
4351
Memory Initialization completed successfully.
4352
 
4353
*********************************************
4354
 
4355
*********************************************
4356
 
4357
Release 11.2 - iMPACT L.46 (nt)
4358
 
4359
Preference Table
4360
 
4361
StartupClock         Auto_Correction
4362
 
4363
KeepSVF              False
4364
 
4365
UseHighz             False
4366
 
4367
UserLevel            Novice
4368
 
4369
svfUseTime           false
4370
 
4371
AutoDetecting cable. Please wait.
4372
 
4373
Checking cable driver.
4374
 
4375
 Driver version: src=2301, dest=2301.
4376
 
4377
 
4378
 
4379
 Max current requested during enumeration is 300 mA.
4380
 
4381
 Cable Type = 3, Revision = 0.
4382
 
4383
 
4384
 
4385
File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.
4386
 
4387
 
4388
 
4389
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6
4390
 
4391
 
4392
 
4393
----------------------------------------------------------------------
4394
 
4395
'1': : Manufacturer's ID = Xilinx xccace, Version : 0
4396
 
4397
----------------------------------------------------------------------
4398
 
4399
 
4400
 
4401
   Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...
4402
 
4403
4404
 
4405
----------------------------------------------------------------------
4406
 
4407
 
4408
 
4409
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
4410
 
4411
 
4412
 
4413
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
4414
 
4415
 
4416
 
4417
 
4418
 
4419
 
4420
 
4421
   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
4422
 
4423
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
4424
 
4425
done.
4426
 
4427
----------------------------------------------------------------------
4428
 
4429
----------------------------------------------------------------------
4430
 
4431
Validating chain...
4432
 
4433
5: Device Temperature: Current Reading:   72.52 C, Min. Reading:   30.69 C, Max.
4434
 
4435
5: VCCINT Supply: Current Reading:   0.993 V, Min. Reading:   0.993 V, Max.
4436
 
4437
5: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.493 V, Max.
4438
 
4439
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
4440
 
4441
'5': Programming device...
4442
 
4443
done.
4444
 
4445
CRC error                                         :         0
4446
 
4447
DCM locked                                        :         1
4448
 
4449
End of startup signal from Startup block          :         1
4450
 
4451
status of GWE                                     :         1
4452
 
4453
value of MODE pin M0                              :         1
4454
 
4455
Value of MODE pin M2                              :         1
4456
 
4457
Value driver in from INIT pad                     :         1
4458
 
4459
Value of DONE pin                                 :         1
4460
 
4461
Decryptor error Signal                            :         0
4462
 
4463
startup_state[18] CFG startup state machine       :         0
4464
 
4465
startup_state[20] CFG startup state machine       :         1
4466
 
4467
SPI Flash Type[22] Select                         :         1
4468
 
4469
SPI Flash Type[24] Select                         :         1
4470
 
4471
CFG bus width auto detection result               :         0
4472
 
4473
BPI address wrap around error                     :         0
4474
 
4475
read back crc error                               :         0
4476
 
4477
 Match_cycle = 2.
4478
 
4479
Elapsed time =     11 sec.
4480
 
4481
----------------------------------------------------------------------
4482
 
4483
----------------------------------------------------------------------
4484
 
4485
----------------------------------------------------------------------
4486
 
4487
----------------------------------------------------------------------
4488
 
4489
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
4490
 
4491
INFO:iMPACT - '5': Programing completed successfully.
4492
 
4493
4494
 
4495
4496
 
4497
4498
 
4499
 make -f system.make program started...
4500
 
4501
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
4502
 
4503
-D GCC_PPC440 -mregnames
4504
 
4505
   text    data     bss     dec     hex filename
4506
 
4507
4508
 
4509
Done!
4510
 
4511
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/; exit;"
4512
 
4513
Writing filter settings....
4514
 
4515
Done writing filter settings to:
4516
 
4517
4518
 
4519
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
4520
 
4521
Xilinx Platform Studio (XPS)
4522
 
4523
4524
 
4525
4526
 
4527
4528
 
4529
4530
 
4531
4532
 
4533
4534
 
4535
 make -f system.make hwclean started...
4536
 
4537
rm -f implementation/system.ngc
4538
 
4539
rm -f __xps/ise/_xmsgs/platgen.xmsgs
4540
 
4541
rm -f implementation/system.bit
4542
 
4543
rm -f implementation/system_bd.bmm
4544
 
4545
rm -f __xps/system_routed
4546
 
4547
rm -rf xst.srp system.srp
4548
 
4549
4550
 
4551
Done!
4552
 
4553
At Local date and time: Sun Jul 05 09:35:36 2009
4554
 
4555
4556
 
4557
rm -f libgen.log
4558
 
4559
rm -f RTOSDemo/executable.elf
4560
 
4561
4562
 
4563
4564
 
4565
4566
 
4567
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
4568
 
4569
Done writing Tab View settings to:
4570
 
4571
4572
 

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