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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC440_Xilinx_Virtex5_GCC/] [system.log] - Blame information for rev 773

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No logfile was found.
 
Xilinx Platform Studio (XPS)
Xilinx EDK 11.2 Build EDK_LS3.47
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 251 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 296 - deprecated core for architecture 'virtex5fx'!
 
Generating Block Diagram to Buffer
 
Generated Block Diagram SVG
 
At Local date and time: Mon Jun 29 21:01:23 2009
 make -f system.make program started...
 
*********************************************
Creating software libraries...
*********************************************
libgen -mhs system.mhs -p xc5vfx70tff1136-1  -msg __xps/ise/xmsgprops.lst system.mss
libgen
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg
 
 
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
   C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
 
 
 
   m.mhs line 296 - deprecated core for architecture 'virtex5fx'!
 
   C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
 
   m.mhs line 296 - deprecated core for architecture 'virtex5fx'!
 
Checking platform configuration ...
 
C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.m
 
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
 
hs line 288 - 1 master(s) : 1 slave(s)
 
Checking port drivers...
 
   C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste
 

 

 

 

 
 
 

 

 

 
WARNING:EDK:494 -
 
   esis\ not found.
 
WARNING:EDK:411 - pcie -
 
   m.mss line 77 - deprecated driver!
 
 
 
INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0:
 
  - DIP_Switches_8Bit
 
  - IIC_EEPROM
 
  - LEDs_Positions
 
 
 
  - SRAM
 
 
 

 
 
 
Staging source files.
 
 
 
Running include - 'make -s include "COMPILER=powerpc-eabi-gcc"
 
 
 
Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"
 
 
 
powerpc-eabi-ar: creating ../../../lib/libxil.a
 
 
 
Compiling gpio
 
 
 
Compiling uartlite
 
Compiling intc
 
Running execs_generate.
 
    -mcpu=440  -Wl,-T -Wl,/cygdrive/c/Temp/WA00101_002/WA00101_002/FreeRTOS/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  53754     372   86524  140650   2256a RTOSDemo/executable.elf
 

 

 

 
        C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
 
Done writing Tab View settings to:
 

 
Xilinx EDK 11.2 Build EDK_LS3.47
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
 
Generating Block Diagram to Buffer
 
Generated Block Diagram SVG
 
At Local date and time: Tue Jun 30 18:32:58 2009
 

 
rm -f platgen.log
 
rm -f implementation/system.bmm
 
rm -f implementation/system.ncd
 
rm -f implementation/system_map.ncd
 
rm -rf implementation synthesis xst hdl
 
 
 

 
 
 
 
 
rm -f implementation/system.ngc
 
rm -f __xps/ise/_xmsgs/platgen.xmsgs
 

 
Done!
 
At Local date and time: Tue Jun 30 18:33:13 2009
 

 
rm -f implementation/system.ncd
 
 
 

 
Done!
 
At Local date and time: Tue Jun 30 18:33:24 2009
 

rm -rf ppc440_0/
 
rm -f __xps/ise/_xmsgs/libgen.xmsgs


Done!

At Local date and time: Tue Jun 30 18:33:31 2009
 make -f system.make programclean started...

rm -f RTOSDemo/executable.elf


 

At Local date and time: Tue Jun 30 18:33:37 2009
 make -f system.make swclean started...

rm -rf ppc440_0/
rm -f libgen.log
 
 

 
Done!
 
Writing filter settings....

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui

 
Xilinx EDK 11.2 Build EDK_LS3.47
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
 
Generating Block Diagram to Buffer
 
Generated Block Diagram SVG

 
 make -f system.make program started...

*********************************************
Creating software libraries...
*********************************************
libgen -mhs system.mhs -p xc5vfx70tff1136-1  -msg __xps/ise/xmsgprops.lst system.mss
libgen
Xilinx EDK 11.2 Build EDK_LS3.47
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.

Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg
__xps/ise/xmsgprops.lst system.mss
 
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
   251 - deprecated core for architecture 'virtex5fx'!
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
   296 - deprecated core for architecture 'virtex5fx'!
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 

Checking platform configuration ...
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
107 - 1 master(s) : 12 slave(s)
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
288 - 1 master(s) : 1 slave(s)
 
 
WARNING:EDK:2099 - PORT:Peripheral_Reset CONNECTOR:sys_periph_reset -
 
   446 - floating connection!

 

Performing Reset DRCs...

 
 
Running system level update procedures...
 
Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...

 

 
 
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\synthesis\ not
   found.
 
WARNING:EDK:411 - pcie -
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mss line
   77 - deprecated driver!
WARNING:EDK:411 - emaclite -
 
 
INFO:EDK:1740 - List of peripherals connected to processor instance ppc440_0:
 
  - DIP_Switches_8Bit
 
  - IIC_EEPROM
  - LEDs_8Bit
 
  - PCIe_Bridge
  - Push_Buttons_5Bit
 
  - SRAM
  - SysACE_CompactFlash
 
  - xps_intc_0
 
-- Generating libraries for processor: ppc440_0 --
 

 
Running DRCs.
 
Running post_generate.
 
"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440  -O2 -c"
"EXTRA_COMPILER_FLAGS=-g"'.
 
Running libs - 'make -s libs "COMPILER=powerpc-eabi-gcc"
"ARCHIVER=powerpc-eabi-ar" "COMPILER_FLAGS=-mcpu=440  -O2 -c"
"EXTRA_COMPILER_FLAGS=-g"'.
Compiling common
powerpc-eabi-ar: creating ../../../lib/libxil.a
 
Compiling lldma
 
Compiling gpio
 
 
 
Compiling uartlite
 
Compiling intc
 
 
 
    -mcpu=440  -Wl,-T -Wl,/cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/RTOSDemo_linker_script.ld  -g    -I./ppc440_0/include/   -I../../Source/include -I../Common/include -I./RTOSDemo -I./RTOSDemo/flop  -L./ppc440_0/lib/  \
 
powerpc-eabi-size RTOSDemo/executable.elf
 
  53754     372   86524  140650   2256a RTOSDemo/executable.elf
 

 

 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
 
Done writing Tab View settings to:
 

 
Xilinx EDK 11.2 Build EDK_LS3.47
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
 
Generating Block Diagram to Buffer
 
 
 
At Local date and time: Tue Jun 30 21:05:40 2009
 

 
Creating system netlist for hardware specification..
 
platgen -p xc5vfx70tff1136-1 -lang vhdl   -msg __xps/ise/xmsgprops.lst system.mhs
 
Release 11.2 - platgen Xilinx EDK 11.2 Build EDK_LS3.47
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 

 
 
 
Parse C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/system.mhs
 

 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
 
   251 - deprecated core for architecture 'virtex5fx'!
 
 
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
 
 
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
 
 

 
 
 
Address Map for Processor ppc440_0
 
 
 
  (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0
 
 
 
  (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0
 
 
 
  (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0
 
 
 
  (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
 
   C_SPLB0_P2P value to 0
 
Computing clock values...
 
   'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be
 
   through the clock generator IP.
 
INFO:EDK:1432 - Frequency for Top-Level Input Clock
 
   performed for IPs connected to that clock port, unless they are connected
 

 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_SLAVES value to 12
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   value to 0x2000
 
 
 
   C_PORT_DWIDTH value to 64
 
 
 
 
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
 
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
 
   value to 128
INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -
 
   a\data\xps_mch_emc_v2_1_0.mpd line 82 - tool is overriding PARAMETER
   C_SPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:xps_mch_emc INSTANCE:SRAM -
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
   a\data\xps_mch_emc_v2_1_0.mpd line 84 - tool is overriding PARAMETER
   C_SPLB_SMALLEST_MASTER value to 128
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
   b\data\plbv46_pcie_v2_1_0.mpd line 86 - tool is overriding PARAMETER
   C_MPLB_DWIDTH value to 128
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
 
   b\data\plbv46_pcie_v2_1_0.mpd line 87 - tool is overriding PARAMETER
   C_MPLB_SMALLEST_SLAVE value to 128
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
   b\data\plbv46_pcie_v2_1_0.mpd line 89 - tool is overriding PARAMETER
   C_SPLB_MID_WIDTH value to 1
 
 
   b\data\plbv46_pcie_v2_1_0.mpd line 90 - tool is overriding PARAMETER
 
INFO:EDK:1560 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
 
   b\data\plbv46_pcie_v2_1_0.mpd line 91 - tool is overriding PARAMETER
   C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
   b\data\plbv46_pcie_v2_1_0.mpd line 95 - tool is overriding PARAMETER
 
INFO:EDK:1560 - IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_SLAVES value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
   ta\plb_v46_v2_1_0.mpd line 74 - tool is overriding PARAMETER C_PLBV46_DWIDTH
 
INFO:EDK:1560 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
   2_01_a\data\xps_ethernetlite_v2_1_0.mpd line 75 - tool is overriding
   PARAMETER C_SPLB_DWIDTH value to 128
 
 
   \data\xps_sysace_v2_1_0.mpd line 72 - tool is overriding PARAMETER
 
INFO:EDK:1560 - IPNAME:xps_sysace INSTANCE:SysACE_CompactFlash -
 
   \data\xps_sysace_v2_1_0.mpd line 74 - tool is overriding PARAMETER
 
 
 
 
 
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
 
   ata\xps_intc_v2_1_0.mpd line 72 - tool is overriding PARAMETER C_SPLB_DWIDTH
 
 
 

 
INFO:EDK:1563 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC -
 
 
 
   The PLB clock frequency must be greater than or equal to 50 MHz for 100 Mbs
 
   operation.
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
IPNAME:plb_v46 INSTANCE:ppc440_0_SPLB0 -
 
288 - 1 master(s) : 1 slave(s)
 
Checking port drivers...
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 

 

 

 
INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -
 
   01_a\data\ppc440_virtex5_v2_1_0.mpd line 124 - tcl is overriding PARAMETER
 
INFO:EDK:1560 - IPNAME:ppc440_virtex5 INSTANCE:ppc440_0 -
 
 
 
INFO:EDK:1560 - IPNAME:jtagppc_cntlr INSTANCE:jtagppc_cntlr_inst -
 
 
 
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
 
 
 
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
 
   ata\xps_intc_v2_1_0.mpd line 80 - tcl is overriding PARAMETER C_KIND_OF_EDGE
 
INFO:EDK:1560 - IPNAME:xps_intc INSTANCE:xps_intc_0 -
 
   ata\xps_intc_v2_1_0.mpd line 81 - tcl is overriding PARAMETER C_KIND_OF_LVL
 

 

 

 

 

 

 
INFO: The PCIe_Bridge core has constraints automatically generated by XPS in
 
It can be overridden by constraints placed in the system.ucf file.
 

 
INFO: The Ethernet_MAC core has constraints automatically generated by XPS in
 
It can be overridden by constraints placed in the system.ucf file.
 

 
INFO: The DDR2_SDRAM core has constraints automatically generated by XPS in
 
It can be overridden by constraints placed in the system.ucf file.
 

 

 

 

 
 
 
Creating hardware output directories ...
 
Managing hardware (BBD-specified) netlist files ...
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
IPNAME:xps_ethernetlite INSTANCE:ethernet_mac -
 
296 - Copying (BBD-specified) netlist files.
 
 
 
Elaborating instances ...
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 

 

 
 
 
Constructing platform-level connectivity ...
 

 

 

 

 

 
   IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
 
INSTANCE:ppc440_0 -
 
- Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
INSTANCE:xps_bram_if_cntlr_1 -
 
116 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
INSTANCE:rs232_uart_1 -
 
136 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
INSTANCE:leds_positions -
 
166 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
INSTANCE:dip_switches_8bit -
 
194 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
INSTANCE:sram -
 
221 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
INSTANCE:ppc440_0_splb0 -
 
288 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
INSTANCE:ddr2_sdram -
 
315 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
INSTANCE:clock_generator_0 -
 
392 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
INSTANCE:proc_sys_reset_0 -
 
437 - Running XST synthesis
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 

 
IPNAME:ppc440_0_wrapper INSTANCE:ppc440_0 -
 
- Running NGCBUILD
 
 with local file
 

 
xc5vfx70tff1136-1 -intstyle silent -uc ppc440_0_wrapper.ucf -sd ..
 

 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/pp
 

 

 
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
NGCBUILD Design Results Summary:
 
  Number of warnings:   0
 
Writing NGC file "../ppc440_0_wrapper.ngc" ...
 
Total CPU time to NGCBUILD completion:   6 sec
 
Writing NGCBUILD log file "../ppc440_0_wrapper.blc"...
 
NGCBUILD done.
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
PMSPEC -- Overriding Xilinx file
 

 
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
 
../rs232_uart_1_wrapper.ngc
 
Reading NGO file
 
232_uart_1_wrapper/rs232_uart_1_wrapper.ngc" ...
 
Partition Implementation Status
 

 

 

 
  Number of errors:     0
 

 
Total REAL time to NGCBUILD completion:  8 sec
 

 

 
IPNAME:pcie_bridge_wrapper INSTANCE:pcie_bridge -
 
251 - Running NGCBUILD
 
 with local file
 

 
xc5vfx70tff1136-1 -intstyle silent -uc pcie_bridge_wrapper.ucf -sd ..
 

 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/pc
 
Executing edif2ngd -noa
 
ie_bridge_wrapper_fifo_generator_v4_3.edn"
 
Release 11.2 - edif2ngd L.46 (nt)
 
INFO:NgdBuild - Release 11.2 edif2ngd L.46 (nt)
 
PMSPEC -- Overriding Xilinx file 
 
Writing module to "pcie_bridge_wrapper_fifo_generator_v4_3.ngo"...
 
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc
 
Loading design module
 
Loading design module
 
ie_bridge_wrapper/dpram_70_512.ngc"...
 
"C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\implementation\pc
 

 

 
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
NGCBUILD Design Results Summary:
 
  Number of warnings:   0
 
Writing NGC file "../pcie_bridge_wrapper.ngc" ...
 
Total CPU time to NGCBUILD completion:   9 sec
 
Writing NGCBUILD log file "../pcie_bridge_wrapper.blc"...
 
NGCBUILD done.
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
PMSPEC -- Overriding Xilinx file
 

 
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
 
ethernet_mac_wrapper.ngc ../ethernet_mac_wrapper.ngc
 
Reading NGO file
 
hernet_mac_wrapper/ethernet_mac_wrapper.ngc" ...
 
"ethernetlite_v1_01_b_dmem_v2.ngo"
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
INFO:NgdBuild - Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
with local file 
 
Loading design module
 
hernet_mac_wrapper\ethernetlite_v1_01_b_dmem_v2.ngo"...
 
Applying constraints in "ethernet_mac_wrapper.ucf" to the design...
 
Partition Implementation Status
 

 

 

 
  Number of errors:     0
 

 
Total REAL time to NGCBUILD completion:  9 sec
 

 

 
IPNAME:ddr2_sdram_wrapper INSTANCE:ddr2_sdram -
 
315 - Running NGCBUILD
 
 with local file
 

 
xc5vfx70tff1136-1 -intstyle silent -uc ddr2_sdram_wrapper.ucf -sd ..
 

 
"C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation/dd
 

 
 
 
-------------------------------
 
 
 
-------------------------------
 
NGCBUILD Design Results Summary:
 
  Number of warnings:   0
 
Writing NGC file "../ddr2_sdram_wrapper.ngc" ...
 
Total CPU time to NGCBUILD completion:   7 sec
 
Writing NGCBUILD log file "../ddr2_sdram_wrapper.blc"...
 
NGCBUILD done.
 
C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 
PMSPEC -- Overriding Xilinx file
 

 
Command Line: C:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe -p
 
../xps_intc_0_wrapper.ngc
 
Reading NGO file
 
s_intc_0_wrapper/xps_intc_0_wrapper.ngc" ...
 
 
 

 

 

 
  Number of errors:     0
 
 
 
Total REAL time to NGCBUILD completion:  1 sec
 
 
 

 
 
 

 
Running synthesis...
 
xst -ifn system_xst.scr -intstyle silent
 
XST completed
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 

 
Command Line: c:\devtools\Xilinx\11.1\ISE\bin\nt\unwrapped\ngcbuild.exe
 
../__xps/ise/system.ise
 
Reading NGO file
 
ngc" ...
 
Loading design module "../implementation/plb_v46_0_wrapper.ngc"...
 
Loading design module
 
Loading design module "../implementation/rs232_uart_1_wrapper.ngc"...
 
Loading design module "../implementation/leds_positions_wrapper.ngc"...
 
Loading design module "../implementation/dip_switches_8bit_wrapper.ngc"...
 
Loading design module "../implementation/sram_wrapper.ngc"...
 
Loading design module "../implementation/ppc440_0_splb0_wrapper.ngc"...
 
Loading design module "../implementation/ddr2_sdram_wrapper.ngc"...
 
Loading design module "../implementation/clock_generator_0_wrapper.ngc"...
 
Loading design module "../implementation/proc_sys_reset_0_wrapper.ngc"...
 

 
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
NGCBUILD Design Results Summary:
 
 
 
Writing NGC file "../implementation/system.ngc" ...
 
 
 
Writing NGCBUILD log file "../implementation/system.blc"...
 
 
 
Running Xilinx Implementation tools..
 
 
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
 
 
 with local file
 
 
 
C:/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/implementation
 
Using Flow File:
 
a.flw
 
 
low.opt
 
 
 
 
 
 
 
 
 
#----------------------------------------------#
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
 

 
 
 
 
 
 
 
 
 
Gathering constraint information from source properties...
 

 
 
   'clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_
 
 
 
 
 
 
 
 
 
 
 
   found.
 
 
 
   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
 
 
 
   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_0_" TS_sys_clk_pin *
 

 
 
 
   The following new TNM groups and period specifications were generated at the
 
 
 
   1.25 HIGH 50%>
 
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
 
   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
 
   PLL_ADV output(s):
 
   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_2_" TS_sys_clk_pin *
 

 
   'TS_sys_clk_pin', was traced into PLL_ADV instance
 
 
 
   CLKOUT3: 
 
 
 
INFO:ConstraintSystem:178 - TNM 'sys_clk_pin', used in period specification
 
   clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst.
 
   PLL_ADV output(s):
 
   PERIOD "clock_generator_0_clock_generator_0_PLL0_CLK_OUT_4_" TS_sys_clk_pin *
 
 
 
Checking Partitions ...
 
 
 
WARNING:NgdBuild:1212 - User specified non-default attribute value
 
   "clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST".
 
 
 
Checking expanded design ...
 
   'xps_bram_if_cntlr_1/xps_bram_if_cntlr_1/INCLUDE_BURST_SUPPORT.I_SLAVE_BURST_
 
 
 
   'SRAM/SRAM/EMC_CTRL_I/MEM_STEER_I/SYNC_MEM_DQT.REG_DQT_GEN[2].DQT_REG' has
 
 
 
   ALIGN_PIPE' has unconnected output pin
 
 
 
   has unconnected output pin
 
 
 
   has unconnected output pin
 
 
 
   RE_I' has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   E_I' has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   ' has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   ' has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   ' has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   ' has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   has unconnected output pin
 
   'SRAM/SRAM/MCH_PLB_IPIF_I/NO_CHNL_IF_GEN.PLBV46_SLAVE_BURST_I/I_SLAVE_ATTACHM
 
   ' has unconnected output pin
 
   "PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_ad
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_STEER_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/GEN_S_H_SIZE_REG[0].I_SIZE_S_H_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/GEN_DWIDTH_64_128.LDMUX_FDRSE
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[3].I_FDRSE_B
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[2].I_FDRSE_B
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[1].I_FDRSE_B
 
WARNING:NgdBuild:443 - SFF primitive
 
   URSTXFER.I_BUS_ADDRESS_COUNTER/I_FLEX_ADDR_CNTR/LDMUX_FDRSE_0to3[0].I_FDRSE_B
 
WARNING:NgdBuild:443 - SFF primitive
 
   _H_ADDR_REG[6].I_ADDR_S_H_REG' has unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_S
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[0].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[1].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[2].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[3].I_BKend_WRCE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[4].I_BKend_WRCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[5].I_BKend_WRCE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_RDCE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[6].I_BKend_WRCE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[7].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[8].I_BKend_RDCE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[9].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[10].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[11].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[12].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[13].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[14].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[15].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[16].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[17].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[18].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[19].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[20].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[21].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[22].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[23].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[24].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[25].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[26].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[27].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[28].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[29].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[30].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[31].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[32].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[33].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[34].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[35].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[36].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[37].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[38].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[39].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[40].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[41].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[42].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[43].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[45].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[46].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[47].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[48].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[49].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_RDCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[50].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_CE_REG' has unconnected
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[51].I_BKend_WRCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_CE_REG' has unconnected
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_RDCE_REG' has
 
 
 
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[52].I_BKend_WRCE_REG' has
 
WARNING:NgdBuild:443 - SFF primitive
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
   E_ASSIGNMENTS[0].GEN_USER_CE.GEN_ALL_CEs[53].I_BKend_CE_REG' has unconnected
   output pin
WARNING:NgdBuild:443 - SFF primitive
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   unconnected output pin
 
 
 
   output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   unconnected output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
   E_ASSIGNMENTS[2].GEN_INTRPT_CE.GEN_ALL_CEs[66].I_BKend_CE_REG' has
   unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
 
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   E_ASSIGNMENTS[3].GEN_RESET_CE.I_BKend_RDCE_REG' has unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
 
 
   output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/GEN_C
 
   unconnected output pin
 
   'PCIe_Bridge/PCIe_Bridge/comp_plbv46_slave/I_SLAVE_ATTACHMENT/I_DECODER/I_CS_
 
WARNING:NgdBuild:443 - SFF primitive
 
   SIZE2_REG1' has unconnected output pin
 
 
 
WARNING:NgdBuild:443 - SFF primitive
 
   unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/COLLISION_SYNC' has unconnected
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU15'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
 
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU35'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/TX/inst_tx_intrfce/I_TX_FIFO/BU237'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
 
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
 
 
WARNING:NgdBuild:440 - FF primitive
 
 
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU35'
 
WARNING:NgdBuild:440 - FF primitive
 
   has unconnected output pin
 
   'Ethernet_MAC/Ethernet_MAC/XEMAC_I/EMAC_I/RX/inst_rx_intrfce/I_RX_FIFO/BU237'
 
WARNING:NgdBuild:440 - FF primitive
 
   /gen_rden[1].u_calib_rden_r' has unconnected output pin
 
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
 
WARNING:NgdBuild:440 - FF primitive
 
   /gen_rden[3].u_calib_rden_r' has unconnected output pin
 
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
 
WARNING:NgdBuild:440 - FF primitive
 
   /gen_rden[5].u_calib_rden_r' has unconnected output pin
 
   'DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib
 
WARNING:NgdBuild:440 - FF primitive
 
   /gen_rden[7].u_calib_rden_r' has unconnected output pin
 
   "clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_PLL_ADV.PLL_ADV_inst"
 
WARNING:NgdBuild:452 - logical net 'N194' has no driver
 
WARNING:NgdBuild:452 - logical net 'N196' has no driver
 
WARNING:NgdBuild:452 - logical net 'N198' has no driver
 
WARNING:NgdBuild:452 - logical net 'N200' has no driver
 
WARNING:NgdBuild:452 - logical net 'N202' has no driver
 
WARNING:NgdBuild:452 - logical net 'N204' has no driver
 
WARNING:NgdBuild:452 - logical net 'N206' has no driver
 
WARNING:NgdBuild:452 - logical net 'N208' has no driver
 
WARNING:NgdBuild:452 - logical net 'N210' has no driver
 
WARNING:NgdBuild:452 - logical net 'N212' has no driver
 
WARNING:NgdBuild:452 - logical net 'N214' has no driver
 
WARNING:NgdBuild:452 - logical net 'N216' has no driver
 
WARNING:NgdBuild:452 - logical net 'N218' has no driver
 
WARNING:NgdBuild:452 - logical net 'N220' has no driver
 
WARNING:NgdBuild:452 - logical net 'N222' has no driver
 
WARNING:NgdBuild:452 - logical net 'N224' has no driver
 
WARNING:NgdBuild:452 - logical net 'N226' has no driver
 
WARNING:NgdBuild:452 - logical net 'N228' has no driver
 
WARNING:NgdBuild:452 - logical net 'N230' has no driver
 
WARNING:NgdBuild:452 - logical net 'N232' has no driver
 
WARNING:NgdBuild:452 - logical net 'N234' has no driver
 
WARNING:NgdBuild:452 - logical net 'N236' has no driver
 
WARNING:NgdBuild:452 - logical net 'N238' has no driver
 
WARNING:NgdBuild:452 - logical net 'N240' has no driver
 
WARNING:NgdBuild:452 - logical net 'N242' has no driver
 
WARNING:NgdBuild:452 - logical net 'N244' has no driver
 
WARNING:NgdBuild:452 - logical net 'N246' has no driver
 
WARNING:NgdBuild:452 - logical net 'N248' has no driver
 
WARNING:NgdBuild:452 - logical net 'N250' has no driver
 
WARNING:NgdBuild:452 - logical net 'N252' has no driver
 
WARNING:NgdBuild:452 - logical net 'N254' has no driver
 
WARNING:NgdBuild:452 - logical net 'N256' has no driver
 
WARNING:NgdBuild:452 - logical net 'N266' has no driver
 
WARNING:NgdBuild:452 - logical net 'N268' has no driver
 
WARNING:NgdBuild:452 - logical net 'N270' has no driver
 
WARNING:NgdBuild:452 - logical net 'N272' has no driver
 
WARNING:NgdBuild:452 - logical net 'N306' has no driver
 
WARNING:NgdBuild:452 - logical net 'N308' has no driver
 
WARNING:NgdBuild:452 - logical net 'N310' has no driver
 
WARNING:NgdBuild:452 - logical net 'N312' has no driver
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_terrfwd_n'
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_rerrfwd_n'
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tsrc_dsc_n'
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_tbuf_av<3>'
 
WARNING:NgdBuild:452 - logical net 'PCIe_Bridge/PCIe_Bridge/sig_trn_trem_n<4>'
 

 
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
NGDBUILD Design Results Summary:
 
  Number of warnings: 348
 
Writing NGD file "system.ngd" ...
 
Total CPU time to NGDBUILD completion:  1 min  28 sec
 
Writing NGDBUILD log file "system.bld"...
 
NGDBUILD done.
 

 
#----------------------------------------------#
 
# map -ise ../__xps/ise/system.ise -o system_map.ncd -w -pr b -ol high -timing
 
#----------------------------------------------#
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
 with local file
 
Using target part "5vfx70tff1136-1".
 
WARNING:LIT:395 - The above warning message is repeated 1200 more times for the
 
   N195,
 
   N197,
 
   N199
 
Mapping design into LUTs...
 
   connected to top level port fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin has
 
WARNING:MapLib:701 - Signal fpga_0_Ethernet_MAC_PHY_col_pin connected to top
 
WARNING:MapLib:41 - All members of TNM group "ppc440_0_PPCS0PLBMBUSY" have been
 
Writing file system_map.ngm...
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAU_tiesig
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_0_REGCLKAL_tiesig
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAU_tiesig
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1
 
   xps_bram_if_cntlr_1_bram/xps_bram_if_cntlr_1_bram/ramb36_1_REGCLKAL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
 
   of frag REGCLKAU connected to power/ground net
 
   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
 
   of frag REGCLKAL connected to power/ground net
 
   er_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst_REGCLKAL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
 
   of frag REGCLKAU connected to power/ground net
 
   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/pcie_mim_wrapp
 
   of frag REGCLKAL connected to power/ground net
 
   er_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst_REGCLKAL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
 
   of frag RDRCLKU connected to power/ground net
 
   x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk_if/ll_bridge/r
 
   of frag RDRCLKL connected to power/ground net
 
   x_bridge/fifo_inst/oq_fifo/Mram_regBank_RDRCLKL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
 
   noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
 
   noeccerr.SDP_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
 
   noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/Comp_FIFO/CompFIFO_64.dpram/BU2/U0
 
   noeccerr.SDP_RDRCLKL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
 
   ram/SDP.WIDE_PRIM36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
 
   ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
 
   ram/SDP.WIDE_PRIM36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_master_bridge/RxSFIFO_64.RxSFIFO/BU2/U0/grf.rf/m
 
   ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
 
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
 
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
 
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/GEN_TX_64_FIFO.comp_tx_pkt_fifo/COM
 
   nit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDRCLKL_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
 
   36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
 
   36.noeccerr.SDP_RDRCLKU_tiesig
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
 
   36.noeccerr.SDP
 
   PCIe_Bridge/PCIe_Bridge/comp_slave_bridge/comp_rx_fifo/GEN_64.COMP_RX_RAM/BU2
 
   36.noeccerr.SDP_RDRCLKL_tiesig
 
Running delay-based LUT packing...
 
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM
 
   timing analysis.
 
   (.mrp).
 
Total REAL time at the beginning of Placer: 1 mins 55 secs
 

 
Phase 1.1  Initial Placement Analysis (Checksum:150b88e2) REAL time: 2 mins 13 secs
 
Phase 2.7  Design Feasibility Check
 
   Components associated with this bus are as follows:
 
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<6>   IOSTANDARD = LVCMOS25
 
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<4>   IOSTANDARD = LVCMOS18
 
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<2>   IOSTANDARD = LVCMOS18
 
         Comp: fpga_0_LEDs_8Bit_GPIO_IO_pin<0>   IOSTANDARD = LVCMOS18
 

 
   Components associated with this bus are as follows:
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<30>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<28>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<26>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<24>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<22>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<20>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<18>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<16>   IOSTANDARD = LVDCI_33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<14>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<12>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<10>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<8>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<6>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<4>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<2>   IOSTANDARD = LVCMOS33
 
         Comp: fpga_0_SRAM_Mem_DQ_pin<0>   IOSTANDARD = LVCMOS33
 

 

 
Phase 3.31  Local Placement Optimization (Checksum:f23945c2) REAL time: 2 mins 14 secs
 
Phase 4.37  Local Placement Optimization
 

 
Phase 5.33  Local Placement Optimization (Checksum:f23945c2) REAL time: 8 mins 58 secs
 
Phase 6.32  Local Placement Optimization
 

 

 

 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
 
|                                          |                                          |
 
| CLOCKREGION_X0Y6:                        | CLOCKREGION_X1Y6:                        |
 
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
 
|   0 center BUFIOs available, 0 in use    |                                          |
 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
 
|                                          |                                          |
 
| CLOCKREGION_X0Y4:                        | CLOCKREGION_X1Y4:                        |
 
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
 
|   2 center BUFIOs available, 0 in use    |                                          |
 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
 
|                                          |                                          |
 
| CLOCKREGION_X0Y2:                        | CLOCKREGION_X1Y2:                        |
 
|   4 Regional Clock Spines, 0 in use      |   4 Regional Clock Spines, 0 in use      |
 
|   2 center BUFIOs available, 0 in use    |                                          |
 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
      |
 
|   0 center BUFIOs available, 0 in use    |                                          |
 
|------------------------------------------|------------------------------------------|
 
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
 
|   4 edge BUFIOs available, 0 in use      |   4 edge BUFIOs available, 0 in use      |
 
|                                          |                                          |
 

 
Clock-Region: 
 
|-----------------------------------------------------------------------------------------------------------------------------------------------------------
 
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
 
|       | Upper Region|  24  |  2  |  0 |   60   |   60   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the upper region
 
|       |CurrentRegion|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the current region
 
|       | Lower Region|  24  |  0  |  0 |   80   |   80   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region
 
| clock |    region   |                                                                                      -----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 

 
  key resource utilizations (used/available): edge-bufios - 3/4; center-bufios - 0/2; bufrs - 0/2; regional-clock-spines - 0/4
 
|       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|-------
 
|       | Lower Region|  24  |  4  |  0 |   40   |   40   |  3200 |  1600 |  4800 |   0  |   0  |  0  |   0  | <- Available resources in the lower region
 
| clock |    region   |                                                                                      -----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 

 
  key resource utilizations (used/available): edge-bufios - 3/4; bufrs - 0/2; regional-clock-spines - 0/4
 
|       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|  type |  expansion  |                                                                                      | 
 
| BUFIO |             |   0  |  0  |  0 |    9   |    0   |     0 |     0 |
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
 

 

 
# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:
 
# Number of Regional Clocking Regions in the device: 16  (4 clock spines in each)
 
# composed of up to 3 clock spines and cover up to 3 regional clock regions)
 
######################################################################################
 
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" driven by "BUFIO_X0Y27"
 
"BUFIO_X0Y27" ;
 
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;
 
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7>" ;
 
CLOCKREGION_X0Y6;
 

 
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_bufio_dqs" LOC =
 
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" TNM_NET =
 
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" AREA_GROUP =
 
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<0>" RANGE =
 

 
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" driven by "BUFIO_X0Y11"
 
"BUFIO_X0Y11" ;
 
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;
 
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4>" ;
 
CLOCKREGION_X0Y2;
 

 
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_bufio_dqs" LOC =
 
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" TNM_NET =
 
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" AREA_GROUP =
 
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1>" RANGE =
 

 
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" driven by "BUFIO_X0Y25"
 
"BUFIO_X0Y25" ;
 
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;
 
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5>" ;
 
CLOCKREGION_X0Y6;
 

 
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_bufio_dqs" LOC =
 
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" TNM_NET =
 
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" AREA_GROUP =
 
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2>" RANGE =
 

 
# IO-Clock "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" driven by "BUFIO_X0Y26"
 
"BUFIO_X0Y26" ;
 
"TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;
 
"CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6>" ;
 
CLOCKREGION_X0Y6;
 

 
INST "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/u_bufio_dqs" LOC =
 
NET "DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" TNM_NET =
 
TIMEGRP "TN_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" AREA_GROUP =
 
AREA_GROUP "CLKAG_DDR2_SDRAM/DDR2_SDRAM/u_ddr2_top/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<3>" RANGE =
 

 
Phase 7.2  Initial Clock and IO Placement (Checksum:7e049af9) REAL time: 9 mins 19 secs
 
Phase 8.36  Local Placement Optimization
 

 
.................
 
......
 
......
 
.....
 
......
 
......
 
.......
 
..
 

 
######################################################################################
 
#
 
# Number of Global Clock Networks: 15
 
# Clock Region Assignment: SUCCESSFUL
 
# Location of Clock Components
 
INST "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y30" ;
 
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.coreclk_pll_bufg" LOC = "BUFGCTRL_X0Y27" ;
 
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/PLL_INST/Using_BUFG_for_CLKFBOUT.CLKFB_BUFG_INST" LOC = "BUFGCTRL_X0Y3" ;
 
INST "fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y8" ;
 
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT3.CLKOUT3_BUFG_INST" LOC = "BUFGCTRL_X0Y4" ;
 
INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP/BUFG" LOC = "BUFGCTRL_X0Y31" ;
 
INST "clock_generator_0/clock_generator_0/Using_PLL0.PLL0_INST/Using_BUFG_for_CLKOUT4.CLKOUT4_BUFG_INST" LOC = "BUFGCTRL_X0Y6" ;
 
INST "clock_generator_0/clock_generator_0/Using_DCM0.DCM0_INST/DCM_INST/Using_DCM_ADV.DCM_ADV_INST" LOC = "DCM_ADV_X0Y0" ;
 
INST "fpga_0_clk_1_sys_clk_pin" LOC = "IOB_X1Y109" ;
 
INST "fpga_0_Ethernet_MAC_PHY_tx_clk_pin" LOC = "IOB_X1Y217" ;
 
INST "fpga_0_PCIe_Bridge_RXN_pin" LOC = "IPAD_X1Y12" ;
 
INST "fpga_0_PCIe_Diff_Clk_IBUF_DS_N_pin" LOC = "IPAD_X1Y16" ;
 
INST "fpga_0_PCIe_Bridge_TXN_pin" LOC = "OPAD_X0Y8" ;
 
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/use_pll.pll_adv_i" LOC = "PLL_ADV_X0Y5" ;
 
INST "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = "GTX_DUAL_X0Y2" ;
 

 
NET "clk_125_0000MHzPLL0" TNM_NET = "TN_clk_125_0000MHzPLL0" ;
 
AREA_GROUP "CLKAG_clk_125_0000MHzPLL0" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
 
# fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP driven by BUFGCTRL_X0Y30
 
TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP" ;
 

 
NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" ;
 
AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/gt_usrclk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5 ;
 
# PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk driven by BUFGCTRL_X0Y27
 
TIMEGRP "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" AREA_GROUP = "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk" ;
 

 
NET "clk_125_0000MHzPLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHzPLL0_ADJUST" ;
 
AREA_GROUP "CLKAG_clk_125_0000MHzPLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
 
# clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6> driven by BUFGCTRL_X0Y3
 
TIMEGRP "TN_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" AREA_GROUP = "CLKAG_clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>" ;
 

 
NET "PCIe_Bridge/Bridge_Clk" TNM_NET = "TN_PCIe_Bridge/Bridge_Clk" ;
 
AREA_GROUP "CLKAG_PCIe_Bridge/Bridge_Clk" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
 
# fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP driven by BUFGCTRL_X0Y8
 
TIMEGRP "TN_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP" ;
 

 
NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" ;
 
AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/clocking_i/clkfbin" RANGE =   CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;
 
# clk_200_0000MHz driven by BUFGCTRL_X0Y4
 
TIMEGRP "TN_clk_200_0000MHz" AREA_GROUP = "CLKAG_clk_200_0000MHz" ;
 

 
NET "fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" TNM_NET = "TN_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" ;
 
AREA_GROUP "CLKAG_fpga_0_SRAM_ZBT_CLK_OUT_pin_OBUF" RANGE =   CLOCKREGION_X1Y6, CLOCKREGION_X1Y7 ;
 
# fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP driven by BUFGCTRL_X0Y31
 
TIMEGRP "TN_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" AREA_GROUP = "CLKAG_fpga_0_Ethernet_MAC_PHY_tx_clk_pin_BUFGP" ;
 

 
NET "clk_125_0000MHz90PLL0_ADJUST" TNM_NET = "TN_clk_125_0000MHz90PLL0_ADJUST" ;
 
AREA_GROUP "CLKAG_clk_125_0000MHz90PLL0_ADJUST" RANGE =   CLOCKREGION_X0Y0, CLOCKREGION_X1Y0, CLOCKREGION_X0Y1, CLOCKREGION_X1Y1, CLOCKREGION_X0Y2, CLOCKREGION_X1Y2, CLOCKREGION_X0Y3, CLOCKREGION_X1Y3, CLOCKREGION_X0Y4, CLOCKREGION_X1Y4, CLOCKREGION_X0Y5, CLOCKREGION_X1Y5, CLOCKREGION_X0Y6, CLOCKREGION_X1Y6, CLOCKREGION_X0Y7, CLOCKREGION_X1Y7 ;
 
# clk_62_5000MHzPLL0_ADJUST driven by BUFGCTRL_X0Y6
 
TIMEGRP "TN_clk_62_5000MHzPLL0_ADJUST" AREA_GROUP = "CLKAG_clk_62_5000MHzPLL0_ADJUST" ;
 

 
NET "PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" TNM_NET = "TN_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" ;
 
AREA_GROUP "CLKAG_PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg" RANGE =   CLOCKREGION_X0Y6, CLOCKREGION_X0Y7 ;
 
# NOTE:
 
# assignments. The report provides range constraints for all global
 
#
 
######################################################################################
 

 
GLOBAL CLOCK NET LOADS DISTRIBUTION REPORT:
 
Number of Global Clock Regions : 16
 

 

 
 key resource utilizations (used/available): global-clocks - 2/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |    202 |clk_125_0000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     46 |    750 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      4 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |     38 |    934 |PCIe_Bridge/Bridge_Clk
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 6/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      0 |      0 |      0 |     18 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |clk_125_0000MHz90PLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz
 
      0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |clock_generator_0/clock_generator_0/PLL0_CLK_OUT<6>
 
      0 |      1 |      1 |      0 |      0 |     35 |      0 |      0 |      0 |      0 |      1 |      0 |     17 |    918 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      6 |    500 |PCIe_Bridge/Bridge_Clk
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     11 |    364 |clk_125_0000MHzPLL0_ADJUST
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 5/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     17 |clk_125_0000MHz90PLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 4/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     81 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/core_clk
 
      0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |     36 |    500 |clk_125_0000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      5 |      0 |      0 |      0 |      0 |      0 |      0 |    130 |    970 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
      4 |      0 |      0 |      0 |     60 |     60 |      0 |      0 |      1 |      0 |      2 |     16 |    640 |   1280 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     83 |clk_125_0000MHz90PLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      3 |clk_200_0000MHz
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 3/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      6 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     22 |    659 |clk_125_0000MHzPLL0_ADJUST
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 5/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      2 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     34 |clk_125_0000MHz90PLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    200 |clk_62_5000MHzPLL0_ADJUST
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 3/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      3 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     20 |    602 |clk_125_0000MHzPLL0_ADJUST
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 4/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     48 |clk_125_0000MHz90PLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      8 |    206 |clk_62_5000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |     28 |    773 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
     10 |      0 |      0 |      0 |     40 |     40 |     16 |      1 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     68 |    285 |PCIe_Bridge/Bridge_Clk
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     21 |fpga_0_SysACE_CompactFlash_SysACE_CLK_pin_BUFGP
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |    118 |    639 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
     12 |      4 |      2 |      0 |     40 |     40 |      0 |      0 |      0 |      0 |      1 |      0 |   1600 |   3200 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      1 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |PCIe_Bridge/PCIe_Bridge/comp_block_plus/comp_endpoint/pcie_blk/REFCLKOUT_bufg
 
      0 |      0 |      0 |      0 |      0 |     27 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      2 |clk_125_0000MHz90PLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      1 |      0 |      0 |      0 |clk_200_0000MHz
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     15 |     12 |fpga_0_Ethernet_MAC_PHY_rx_clk_pin_BUFGP
 
      0 |      0 |      2 |      0 |      0 |     35 |      0 |      0 |      0 |      0 |      1 |      0 |     27 |    777 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      1 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      4 |    103 |PCIe_Bridge/Bridge_Clk
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 

 
 key resource utilizations (used/available): global-clocks - 2/10 ;
 
   BRAM |    DCM |    PLL |     GT | ILOGIC | OLOGIC |   MULT |  TEMAC |    PPC |   PCIE | IDLYCT | BUFGCT |    LUT |     FF | <- (Types of Resources in this  Region)
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     19 |clk_62_5000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     16 |    514 | Total
 

 
Clock-Region: 
 
--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+--------+----------------------------------------
 
   FIFO |        |        |        |        |        |        |        |        |        |        |        |        |        |
 
      8 |      0 |      0 |      0 |     40 |     40 |     16 |      0 |      0 |      0 |      1 |      0 |   1920 |   2880 | <- (Available Resources in this Region)
 
        |        |        |        |        |        |        |        |        |        |        |        |        |        | 
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     46 |    327 |clk_125_0000MHzPLL0_ADJUST
 
      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |      0 |     46 |    327 | Total
 

 
The above detailed report is the initial placement of the logic after the clock region assignment. The final placement
 
maybe moved to adjacent clock-regions as long as the "number of clocks per region" constraint is not violated.
 

 
######################################################################################
 

 

 
Phase 10.3  Local Placement Optimization (Checksum:7e049af9) REAL time: 10 mins 43 secs
 
Phase 11.5  Local Placement Optimization
 

 
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Phase 12.8  Global Placement (Checksum:4ba01660) REAL time: 15 mins 18 secs
 
Phase 13.29  Local Placement Optimization
 

 
Phase 14.5  Local Placement Optimization (Checksum:4ba01660) REAL time: 15 mins 22 secs
 
Phase 15.18  Placement Optimization
 

 
Phase 16.5  Local Placement Optimization (Checksum:f81b02a1) REAL time: 18 mins 3 secs
 
Phase 17.34  Placement Validation
 

 
Total CPU  time to Placer completion: 17 mins 4 secs
 
Writing output files...
 
Design Summary:
 
Number of warnings:   50
 
  Number of Slice Registers:                12,128 out of  44,800   27%
 
    Number used as Latches:                      1
 
    Number used as logic:                   11,767 out of  44,800   26%
 
      Number using O5 output only:             282
 
    Number used as Memory:                     392 out of  13,120    2%
 
        Number using O6 output only:            12
 
      Number used as Single Port RAM:            4
 
      Number used as Shift Register:           332
 
    Number used as exclusive route-thru:       107
 
    Number using O6 output only:               382
 
    Number using O5 and O6:                      5
 
Slice Logic Distribution:
 
  Number of LUT Flip Flop pairs used:       17,046
 
    Number with an unused LUT:               4,780 out of  17,046   28%
 
    Number of unique control sets:           1,288
 
      to control set restrictions:           3,000 out of  44,800    6%
 
  A LUT Flip Flop pair for this architecture represents one LUT paired with
 
  clock, reset, set, and enable signals for a registered element.
 
  over-mapped for a non-slice resource or if Placement fails.
 
  over-mapped for a non-BRAM resource or if placement fails.
 
IO Utilization:
 
    Number of LOCed IOBs:                      255 out of     255  100%
 
    Number of bonded IPADs:                      4 out of      50    8%
 

 
  Number of BlockRAM/FIFO:                      23 out of     148   15%
 
    Number using FIFO only:                      2
 
      Number of 36k BlockRAM used:              16
 
      Number of 36k FIFO used:                   2
 
  Number of BUFG/BUFGCTRLs:                     15 out of      32   46%
 
  Number of IDELAYCTRLs:                         3 out of      22   13%
 
  Number of BUFIOs:                              8 out of      80   10%
 
  Number of GTX_DUALs:                           1 out of       8   12%
 
    Number of LOCed PCIEs:                       1 out of       1  100%
 
  Number of PPC440s:                             1 out of       1  100%
 
  Number of RPM macros:           64
 

 
Total REAL time to MAP completion:  18 mins 45 secs
 

 
See MAP report file "system_map.mrp" for details.
 

 
#----------------------------------------------#
 
# par -ise ../__xps/ise/system.ise -w -ol high system_map.ncd system.ncd
 
#----------------------------------------------#
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 

 

 
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
 

 
   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
 
   overrides constraint  [system.pcf(65972)].
 

 
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)
 
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP
 
INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please
 

 

 

 

 
   Number of BUFGs                          15 out of 32     46%
 
   Number of DCM_ADVs                        1 out of 12      8%
 
      Number of LOCed FIFO36_72_EXPs         2 out of 2     100%
 
   Number of GTX_DUALs                       1 out of 8      12%
 
      Number of LOCed IDELAYCTRLs            3 out of 3     100%
 
   Number of ILOGICs                       131 out of 800    16%
 

 
      Number of LOCed IOBs                 255 out of 255   100%
 
   Number of IODELAYs                       80 out of 800    10%
 

 
      Number of LOCed IPADs                  4 out of 4     100%
 
   Number of JTAGPPCs                        1 out of 1     100%
 
   Number of External OPADs                  2 out of 32      6%
 

 
      Number of LOCed PCIEs                  1 out of 1     100%
 
   Number of PLL_ADVs                        2 out of 6      33%
 
   Number of RAMB18X2SDPs                    5 out of 148     3%
 
      Number of LOCed RAMB36SDP_EXPs         1 out of 6      16%
 
   Number of RAMB36_EXPs                    10 out of 148     6%
 

 
      Number used as Flip Flops          12127
 
      Number used as LatchThrus              0
 
   Number of Slice LUTS                  12266 out of 44800  27%
 

 
Overall effort level (-ol):   High
 

 
Finished initial Timing Analysis.  REAL time: 52 secs
 
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_sb_txrem_n<0> has no load.  PAR will not attempt to route this
 
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_TxREMn<0> has no load.  PAR will not attempt to route this
 
WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<30> has no load.  PAR will not attempt to route this
 
WARNING:Par:288 - The signal xps_bram_if_cntlr_1_port_BRAM_Addr<31> has no load.  PAR will not attempt to route this
 
WARNING:Par:288 - The signal PCIe_Bridge/PCIe_Bridge/sig_MB_RxFull has no load.  PAR will not attempt to route this
 
Starting Router
 
INFO:Route:501 - One or more directed routing (DIRT) constraints generated for a specific device have been found. Note
 
   verify that the same connectivity is available in the target device for this implementation.
 
Phase  1  : 82160 unrouted;      REAL time: 1 mins 9 secs
 
Phase  2  : 72970 unrouted;      REAL time: 1 mins 22 secs
 
Phase  3  : 28783 unrouted;      REAL time: 3 mins 31 secs
 
Phase  4  : 28815 unrouted; (Setup:0, Hold:103206, Component Switching Limit:0)     REAL time: 3 mins 57 secs
 
Updating file: system.ncd with current fully routed design.
 
Phase  5  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs
 
Phase  6  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs
 
Phase  7  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs
 
Phase  8  : 0 unrouted; (Setup:0, Hold:103693, Component Switching Limit:0)     REAL time: 5 mins 9 secs
 
Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 7 mins 25 secs
 
Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 7 mins 57 secs
 
Total CPU time to Router completion: 7 mins 31 secs
 
Partition Implementation Status
 

 

 

 

 
Generating Clock Report
 

 
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
 
|clk_125_0000MHzPLL0_ |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|                  lk |BUFGCTRL_X0Y28| No   | 1481 |  0.519     |  2.085      |
 
|clk_62_5000MHzPLL0_A |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|            0_ADJUST | BUFGCTRL_X0Y5| No   |  165 |  0.262     |  2.028      |
 
|PCIe_Bridge/PCIe_Bri |              |      |      |            |             |
 
|comp_endpoint/core_c |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|tFlash_SysACE_CLK_pi |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|dge/comp_block_plus/ |              |      |      |            |             |
 
|        lk/gt_usrclk |BUFGCTRL_X0Y29| No   |    6 |  0.065     |  1.886      |
 
|fpga_0_Ethernet_MAC_ |              |      |      |            |             |
 
|                     |BUFGCTRL_X0Y30| No   |   12 |  0.086     |  1.874      |
 
|fpga_0_Ethernet_MAC_ |              |      |      |            |             |
 
|                     |BUFGCTRL_X0Y31| No   |    6 |  0.004     |  1.941      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
 
|f_top/u_phy_top/u_ph |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
 
| y_io/delayed_dqs<1> |        IO Clk| No   |   18 |  0.083     |  0.380      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
 
|f_top/u_phy_top/u_ph |              |      |
 
| y_io/delayed_dqs<2> |        IO Clk| No   |   18 |  0.101     |  0.425      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
 
|f_top/u_phy_top/u_ph |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
 
| y_io/delayed_dqs<5> |        IO Clk| No   |   18 |  0.101     |  0.425      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
 
|f_top/u_phy_top/u_ph |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|M/u_ddr2_top/u_mem_i |              |      |      |            |             |
 
| y_io/delayed_dqs<6> |        IO Clk| No   |   18 |  0.096     |  0.393      |
 
|DDR2_SDRAM/DDR2_SDRA |              |      |      |            |             |
 
|f_top/u_phy_top/u_ph |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
+---------------------+--------------+------+------+------------+-------------+
 
+---------------------+--------------+------+------+------------+-------------+
 
|                  pt |         Local|      |    1 |  0.000     |  0.625      |
 
|PCIe_Bridge/PCIe_Bri |              |      |      |            |             |
 
|comp_endpoint/pcie_b |              |      |      |            |             |
 
|  per_i/icdrreset<0> |         Local|      |    1 |  0.000     |  0.590      |
 
|Ethernet_MAC/Etherne |              |      |      |            |             |
 
+---------------------+--------------+------+------+------------+-------------+
 
|         _JTGC405TCK |         Local|      |    1 |  0.000     |  1.699      |
 

 
only delays for the net. Note this is different from Clock Skew which
 
the minimum and maximum path delays which includes logic delays.
 
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
 
Number of Timing Constraints that were not applied: 5
 
Asterisk (*) preceding a constraint indicates it was not met.
 

 
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing
 
----------------------------------------------------------------------------------------------------------
 
  s HIGH 50%                                | HOLD        |     0.030ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  lus/comp_endpoint/core_clk" PERIOD =      | HOLD        |     0.315ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
 
  DELAY = 0.85 ns                           |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.015ns|     0.835ns|       0|           0
 
  dqs[0].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS"       | HOLD        |     1.026ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  L0_CLK_OUT_2_ = PERIOD TIMEGRP         "c | HOLD        |     0.021ns|            |       0|           0
 
  LK_OUT_2_" TS_sys_clk_pin *         1.25  |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
 
  DELAY = 0.85 ns                           |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.045ns|     0.805ns|       0|           0
 
  dqs[5].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
 
  DELAY = 0.85 ns                           |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0
 
  dqs[3].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/gen_ |             |            |            |        |
 
  DELAY = 0.85 ns                           |             |            |            |        |
 
  NET         "DDR2_SDRAM/DDR2_SDRAM/u_ddr2 | MAXDELAY    |     0.047ns|     0.803ns|       0|           0
 
  dqs[6].u_iob_dqs/en_dqs_sync"         MAX |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  _top/u_mem_if_top/u_phy_top/u_phy_io/en_d |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  ge_Clk" TO TIMEGRP "SPLB_Clk" 8 ns        | HOLD        |     0.516ns|            |       0|           0
 
------------------------------------------------------------------------------------------------------
 
  HIGH 50%                                  |             |            |            |        |
 
  TS_PLB_PCIe = MAXDELAY FROM TIMEGRP "SPLB | SETUP       |     1.252ns|     6.748ns|       0|           0
 
    DATAPATHONLY                            |             |            |            |        |
 
  TSRXIN_Ethernet_MAC = MAXDELAY FROM TIMEG | MAXDELAY    |     1.700ns|     4.300ns|       0|           0
 
  thernet_MAC" 6 ns                         |             |            |            |        |
 
  TS_clock_generator_0_clock_generator_0_PL | SETUP       |     2.073ns|     5.466ns|       0|           0
 
  lock_generator_0_clock_generator_0_PLL0_C |             |            |            |        |
 
  PHASE 2 ns HIGH 50%                       |             |            |            |        |
 
  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE |     6.000ns|     4.000ns|       0|           0
 
------------------------------------------------------------------------------------------------------
 
  L0_CLK_OUT_4_ = PERIOD TIMEGRP         "c | HOLD        |     0.153ns|            |       0|           0
 
  LK_OUT_4_" TS_sys_clk_pin *         0.625 |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  L0_CLK_OUT_3_ = PERIOD TIMEGRP         "c | HOLD        |     0.465ns|            |       0|           0
 
  LK_OUT_3_" TS_sys_clk_pin *         2 HIG |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  UFGP" MAXSKEW = 5 ns                      |             |            |            |        |
 
  NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_B | NETSKEW     |     4.789ns|     0.211ns|       0|           0
 
------------------------------------------------------------------------------------------------------
 
  L0_CLK_OUT_1_ = PERIOD TIMEGRP         "c |             |            |            |        |
 
  LK_OUT_1_" TS_sys_clk_pin *         1.25  |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  GRP "TXCLK_GRP_Ethernet_MAC" TO         T |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  UFGP" PERIOD = 40 ns HIGH 14 ns           | HOLD        |     0.473ns|            |       0|           0
 
  TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FRO | SETUP       |    13.832ns|     6.168ns|       0|           0
 
      TIMEGRP "TNM_CLK90" TS_MC_CLK * 4     |             |            |            |        |
 
  TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM | SETUP       |    16.202ns|     3.798ns|       0|           0
 
     TIMEGRP "TNM_CLK0" TS_MC_CLK * 4       |             |            |            |        |
 
  TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    17.943ns|     2.057ns|       0|           0
 
    TS_MC_CLK * 4                           |             |            |            |        |
 
  TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "T | SETUP       |    17.975ns|     2.025ns|       0|           0
 
    TS_MC_CLK * 4                           |             |            |            |        |
 
  TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGR | SETUP       |    18.085ns|     1.915ns|       0|           0
 
  TNM_CLK0" TS_MC_CLK * 4                   |             |            |            |        |
 
  NET "fpga_0_SysACE_CompactFlash_SysACE_CL | SETUP       |    26.710ns|     3.290ns|       0|           0
 
   HIGH 50%                                 |             |            |            |        |
 
  NET "fpga_0_Ethernet_MAC_PHY_tx_clk_pin_B | SETUP       |    32.431ns|     7.569ns|       0|           0
 
------------------------------------------------------------------------------------------------------
 
------------------------------------------------------------------------------------------------------
 
  P "TNM_RDEN_SEL_MUX" TO TIMEGRP         " |             |            |            |        |
 
------------------------------------------------------------------------------------------------------
 
  s HIGH 50%                                |             |            |            |        |
 

 
Derived Constraint Report
 
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
 
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 
| TS_MC_PHY_INIT_DATA_SEL_0     |     20.000ns|      3.798ns|          N/A|            0|            0|           21|            0|
 
| TS_MC_GATE_DLY                |     20.000ns|      2.025ns|          N/A|            0|            0|           40|            0|
 
| TS_MC_CAL_RDEN_DLY            |     20.000ns|      1.915ns|          N/A|            0|            0|            5|            0|
 
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 
Derived Constraints for TS_sys_clk_pin
 
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
 
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
 
|TS_sys_clk_pin                 |     10.000ns|      4.000ns|      9.966ns|            0|            0|            0|       636358|
 
| erator_0_PLL0_CLK_OUT_0_      |             |             |             |             |             |             |             |
 
| erator_0_PLL0_CLK_OUT_1_      |             |             |             |             |             |             |             |
 
| erator_0_PLL0_CLK_OUT_2_      |             |             |             |             |             |             |             |
 
| erator_0_PLL0_CLK_OUT_3_      |             |             |             |             |             |             |             |
 
| erator_0_PLL0_CLK_OUT_4_      |             |             |             |             |             |             |             |
 

 
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
 

 
Generating Pad Report.
 
All signals are completely routed.
 
WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
 
Loading device for application Rf_Device from file '5vlx50t.nph' in environment
 
INFO:ParHelpers:197 - Number of "Exact" mode Directed Routing Constraints: 128
 
   found: 128, number successful: 128
 
Total CPU time to PAR completion: 8 mins 19 secs
 
Peak Memory Usage:  653 MB
 
Placer: Placement generated during map.
 
Timing: Completed - No errors found.
 
Number of error messages: 0
 
Number of info messages: 4
 
Writing design to file system.ncd
 

 
PAR done!
 

 
#----------------------------------------------#
 
# trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf
 
Release 11.2 - Trace  (nt)
 

 
PMSPEC -- Overriding Xilinx file
 

 
c:\devtools\Xilinx\11.1\ISE;C:\devtools\Xilinx\11.1\EDK.
 
WARNING:ConstraintSystem:65 - Constraint 
 
   "PCIe_Bridge/Bridge_Clk" PERIOD = 8 ns HIGH 50%;> [system.pcf(65972)].
 
WARNING:Timing:3223 - Timing constraint TS_MC_RDEN_SEL_MUX = MAXDELAY FROM
 
   ignored during timing analysis.
 
   information, see the TSI report.  Please consult the Xilinx Command Line
 
--------------------------------------------------------------------------------
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
trce -ise ../__xps/ise/system.ise -e 3 -xml system.twx system.ncd system.pcf
 

 
Physical constraint file: system.pcf
 
level 0)
 
--------------------------------------------------------------------------------
 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
 
   unconstrained paths section(s) of the report.
 
   50 Ohm transmission line loading model.  For the details of this model, and
 
   see the device datasheet.
 

 
---------------
 
Timing errors: 0  Score: 0 (Setup/Max: 0, Hold: 0)
 
Constraints cover 826342 paths, 18 nets, and 74598 connections
 
Design statistics:
 
   Maximum path delay from/to any node:   7.812ns
 
   Maximum net skew:   0.608ns
 

 
--------------------------------------------------------------------------------
 
Generating Report ...
 
Number of warnings: 2
 
Total time: 1 mins 36 secs
 

 
touch __xps/system_routed
 
Analyzing implementation/system.par
 
Running Bitgen..
 
cd implementation; bitgen -w -f bitgen.ut system; cd ..
 
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
 with local file
 
Loading device for application Rf_Device from file '5vfx70t.nph' in environment
 
   "system" is an NCD, version 3.2, device xc5vfx70t, package ff1136, speed -1
 

 

 
WARNING:PhysDesignRules:1842 - One or more GTXs are being used in this design.
 
   Transceiver User Guide to ensure that the design SelectIO usage meets the
 
WARNING:PhysDesignRules:372 - Gated clock. Clock net
 
   rapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not good
 
   flip-flop.
 
   Ethernet_MAC/Ethernet_MAC/phy_tx_clk_i is sourced by a combinatorial pin.
 
   data into the flip-flop.
 
   > is incomplete. The signal does
 
WARNING:PhysDesignRules:367 - The signal
 
   drive any load pins in the design.
 
   > is incomplete. The signal does not
 
WARNING:PhysDesignRules:367 - The signal
 
   drive any load pins in the design.
 
   is incomplete. The signal does not drive any load pins in the design.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
   block:
 
   used.
 
   block:
 
   Flip-flop but the SRVAL_Q1 set/reset value is not configured.
 
individual error or warning messages for more details.
 
Saving bit stream in "system.bit".
 

 
Done!
 
Writing filter settings....
 
Done writing filter settings to:
 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 237 - deprecated core for architecture 'virtex5fx'!
 
WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\_xps_tempmhsfilename.mhs line 282 - deprecated core for architecture 'virtex5fx'!
 
Generating Block Diagram to Buffer
 
Generated Block Diagram SVG
 
At Local date and time: Sat Jul 04 20:43:06 2009
 

 
*********************************************
 
*********************************************
 
-bt implementation/system.bit -o implementation/download.bit
 
bitinit version Xilinx EDK 11.2 Build EDK_LS3.47
 

 
WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge -
 
   251 - deprecated core for architecture 'virtex5fx'!
 
   C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line
 

 

 

 
Address Map for Processor ppc440_0
 
  (0000000000-0x0fffffff) DDR2_SDRAM    ppc440_0_PPC440MC
 
  (0x81400000-0x8140ffff) Push_Buttons_5Bit     plb_v46_0
 
  (0x81440000-0x8144ffff) LEDs_8Bit     plb_v46_0
 
  (0x81600000-0x8160ffff) IIC_EEPROM    plb_v46_0
 
  (0x83600000-0x8360ffff) SysACE_CompactFlash   plb_v46_0
 
  (0x85c00000-0x85c0ffff) PCIe_Bridge   plb_v46_0
 
  (0xe0000000-0xefffffff) PCIe_Bridge   plb_v46_0
 
  (0xffffe000-0xffffffff) xps_bram_if_cntlr_1   plb_v46_0
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\ppc440_virtex5_v1_
 
   C_SPLB0_P2P value to 0
 
Computing clock values...
 
   'fpga_0_PCIe_Diff_Clk_IBUF_DS_P_pin' is not specified. Clock DRCs will not be
 
   through the clock generator IP.
 
INFO:EDK:1432 - Frequency for Top-Level Input Clock
 
   performed for IPs connected to that clock port, unless they are connected
 

 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_SLAVES value to 12
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_bram_if_cntlr_
 
   PARAMETER C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   value to 0x2000
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   C_PORT_DWIDTH value to 64
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a
 
   value to 8
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_uartlite_v1_01
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_gpio_v2_00_a\d
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_iic_v2_01_a\da
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_mch_emc_v3_00_
 
   C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_MPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_MPLB_SMALLEST_SLAVE value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_SMALLEST_MASTER value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_pcie_v3_00_
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_NUM_SLAVES value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   C_PLBV46_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\plb_v46_v1_04_a\da
 
   value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_ethernetlite_v
 
   PARAMETER C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_DWIDTH value to 128
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_MID_WIDTH value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_sysace_v1_01_a
 
   C_SPLB_NUM_MASTERS value to 1
 
   C:\devtools\Xilinx\11.1\EDK\hw\XilinxProcessorIPLib\pcores\xps_intc_v2_00_a\d
 
   value to 128
 
Checking platform address map ...
 
Initializing Memory...
 
data2mem -bm "implementation/system_bd" -bt "implementation/system.bit"  -bd
 
Memory Initialization completed successfully.
 
*********************************************
 
*********************************************
 
Release 11.2 - iMPACT L.46 (nt)
 
Preference Table
 
StartupClock         Auto_Correction
 
KeepSVF              False
 
UseHighz             False
 
UserLevel            Novice
 
svfUseTime           false
 
AutoDetecting cable. Please wait.
 
Checking cable driver.
 
 Driver version: src=2301, dest=2301.
 
 
 
 Max current requested during enumeration is 300 mA.
 
 Cable Type = 3, Revision = 0.
 
 
 
File version of c:/devtools/Xilinx/11.1/ISE/data/xusb_xp2.hex = 2401.
 
 
 
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc5vfx70t, Version : 6
 
 
 
----------------------------------------------------------------------
 
'1': : Manufacturer's ID = Xilinx xccace, Version : 0
 
----------------------------------------------------------------------
 
 
 
   Reading c:/devtools/Xilinx/11.1/ISE/acecf/data/xccace.bsd...
 

 
----------------------------------------------------------------------
 
 
 
INFO:iMPACT:501 - '1': Added Device xc95144xl successfully.
 
 
 
'4': : Manufacturer's ID = Xilinx xcf32p, Version : 15
 
 
 
 
 
 
 
   Reading c:/devtools/Xilinx/11.1/ISE/xcfp/data/xcf32p.bsd...
 
INFO:iMPACT:501 - '1': Added Device xcf32p successfully.
 
done.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
Validating chain...
 
5: Device Temperature: Current Reading:   72.52 C, Min. Reading:   30.69 C, Max.
 
5: VCCINT Supply: Current Reading:   0.993 V, Min. Reading:   0.993 V, Max.
 
5: VCCAUX Supply: Current Reading:   2.496 V, Min. Reading:   2.493 V, Max.
 
INFO:iMPACT:501 - '5': Added Device xc5vfx70t successfully.
 
'5': Programming device...
 
done.
 
CRC error                                         :         0
 
DCM locked                                        :         1
 
End of startup signal from Startup block          :         1
 
status of GWE                                     :         1
 
value of MODE pin M0                              :         1
 
Value of MODE pin M2                              :         1
 
Value driver in from INIT pad                     :         1
 
Value of DONE pin                                 :         1
 
Decryptor error Signal                            :         0
 
startup_state[18] CFG startup state machine       :         0
 
startup_state[20] CFG startup state machine       :         1
 
SPI Flash Type[22] Select                         :         1
 
SPI Flash Type[24] Select                         :         1
 
CFG bus width auto detection result               :         0
 
BPI address wrap around error                     :         0
 
read back crc error                               :         0
 
 Match_cycle = 2.
 
Elapsed time =     11 sec.
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
----------------------------------------------------------------------
 
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
 
INFO:iMPACT - '5': Programing completed successfully.
 

 

 

 
 make -f system.make program started...
 
powerpc-eabi-gcc -O0 /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/BlockQ.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/blocktim.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/comtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/countsem.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/death.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/dynamic.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/flash.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/GenQTest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/integer.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/QPeek.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/recmutex.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../Common/Minimal/semtest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/tasks.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/list.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/queue.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/croutine.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/portasm.S /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/GCC/PPC440_Xilinx/port.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/../../../Source/portable/MemMang/heap_2.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop-reg-test.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/flop/flop.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/partest/partest.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/serial/serial.c /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/RTOSDemo/main.c  -o RTOSDemo/executable.elf \
 
-D GCC_PPC440 -mregnames
 
   text    data     bss     dec     hex filename
 

 
Done!
 
start xbash -noblock -q -c "cd /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/; xmd -xmp system.xmp -opt etc/xmd_ppc440_0.opt -lp /cygdrive/c/E/Dev/FreeRTOS/WorkingCopy3/Demo/PPC440_Xilinx_Virtex5_GCC/; exit;"
 
Writing filter settings....
 
Done writing filter settings to:
 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.gui
 
Xilinx Platform Studio (XPS)
 

 

 

 

 

 

 
 make -f system.make hwclean started...
 
rm -f implementation/system.ngc
 
rm -f __xps/ise/_xmsgs/platgen.xmsgs
 
rm -f implementation/system.bit
 
rm -f implementation/system_bd.bmm
 
rm -f __xps/system_routed
 
rm -rf xst.srp system.srp
 

 
Done!
 
At Local date and time: Sun Jul 05 09:35:36 2009
 

 
rm -f libgen.log
 
rm -f RTOSDemo/executable.elf
 

 

 

 
        C:\E\Dev\FreeRTOS\WorkingCopy3\Demo\PPC440_Xilinx_Virtex5_GCC\__xps\system.filters
 
Done writing Tab View settings to:
 

 
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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [PPC440_Xilinx_Virtex5_GCC/] [system.log] - Blame information for rev 773

Line No.	Rev	Author	Line
1	586	jeremybenn	`No logfile was found.`
2
3			`Xilinx Platform Studio (XPS)`
4			`Xilinx EDK 11.2 Build EDK_LS3.47`
5
6			`Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.`
7
8			`WARNING:EDK:1582 - IPNAME:plbv46_pcie INSTANCE:PCIe_Bridge - C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 251 - deprecated core for architecture 'virtex5fx'!`
9
10			`WARNING:EDK:1582 - IPNAME:xps_ethernetlite INSTANCE:Ethernet_MAC - C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\system.mhs line 296 - deprecated core for architecture 'virtex5fx'!`
11
12			`Generating Block Diagram to Buffer`
13
14			`Generated Block Diagram SVG`
15
16			`At Local date and time: Mon Jun 29 21:01:23 2009`
17			`make -f system.make program started...`
18
19			`*********************************************`
20			`Creating software libraries...`
21			`*********************************************`
22			`libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg __xps/ise/xmsgprops.lst system.mss`
23			`libgen`
24
25			`Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.`
26
27			`Command Line: libgen -mhs system.mhs -p xc5vfx70tff1136-1 -msg`
28
29
30
31			`Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.`
32
33			`C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste`
34
35
36
37			`m.mhs line 296 - deprecated core for architecture 'virtex5fx'!`
38
39			`C:\Temp\WA00101_002\WA00101_002\FreeRTOS\Demo\PPC440_Xilinx_Virtex5_GCC\syste`
40