OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [RX600_RX62N-RDK_GNURX/] [RTOSDemo/] [GNU-Files/] [start.asm] - Blame information for rev 603

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 585 jeremybenn
/*------------------------------------------------------------------------
2
                                                                       |
3
   FILE        : start.asm                                             |
4
   DATE        :  Wed, Aug 25, 2010                                    |
5
   DESCRIPTION :   Reset Program                                       |
6
   CPU TYPE    :    Other                                              |
7
                                                                       |
8
   This file is generated by KPIT GNU Project Generator (Ver.4.5).     |
9
                                                                       |
10
------------------------------------------------------------------------*/
11
 
12
 
13
 
14
        /*Start.asm*/
15
 
16
        .list
17
        .section .text
18
        .global _start   /*global Start routine */
19
 
20
#ifdef CPPAPP
21
___dso_handle:
22
        .global ___dso_handle
23
#endif
24
 
25
        .extern _hw_initialise  /*external Sub-routine to initialise Hardware*/
26
        .extern _data
27
        .extern _mdata
28
        .extern _ebss
29
        .extern _bss
30
        .extern _edata
31
        .extern _main
32
        .extern _ustack
33
        .extern _istack
34
        .extern _rvectors
35
#if DEBUG
36
        .extern _exit
37
#endif
38
 
39
 
40
_start:
41
/* initialise user stack pointer */
42
        mvtc    #_ustack,USP
43
 
44
/* initialise interrupt stack pointer */
45
        mvtc    #_istack,ISP
46
 
47
/* setup intb */
48
        mvtc    #_rvectors_start, intb  /* INTERRUPT VECTOR ADDRESS  definition */
49
 
50
/* setup FPSW */
51
        mvtc    #100h, fpsw
52
 
53
/* load data section from ROM to RAM */
54
 
55
        mov     #_mdata,r2      /* src ROM address of data section in R2 */
56
        mov     #_data,r1       /* dest start RAM address of data section in R1 */
57
        mov     #_edata,r3      /* end RAM address of data section in R3 */
58
        sub    r1,r3            /* size of data section in R3 (R3=R3-R1) */
59
        smovf                   /* block copy R3 bytes from R2 to R1 */
60
 
61
/* bss initialisation : zero out bss */
62
 
63
        mov     #00h,r2         /* load R2 reg with zero */
64
        mov     #_ebss, r3  /* store the end address of bss in R3 */
65
        mov     #_bss, r1       /* store the start address of bss in R1 */
66
        sub   r1,r3             /* size of bss section in R3 (R3=R3-R1) */
67
        sstr.b
68
 
69
/* call the hardware initialiser */
70
        bsr.a   _hw_initialise
71
        nop
72
 
73
/* setup PSW */
74
//      mvtc    #10000h, psw                    /* Set Ubit & Ibit for PSW */
75
 
76
/* change PSW PM to user-mode */
77
//      MVFC   PSW,R1
78
//      OR     #00100000h,R1
79
//      PUSH.L R1
80
//      MVFC   PC,R1
81
//      ADD    #10,R1
82
//      PUSH.L R1
83
//      RTE
84
//      NOP
85
//      NOP
86
 
87
/* start user program */
88
        bsr.a   _main
89
 
90
/* call to exit*/
91
_exit:
92
        bsr.a   _exit
93
 
94
        .end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.